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IT1174447B - Multielaboratore perfezionato - Google Patents

Multielaboratore perfezionato

Info

Publication number
IT1174447B
IT1174447B IT27918/78A IT2791878A IT1174447B IT 1174447 B IT1174447 B IT 1174447B IT 27918/78 A IT27918/78 A IT 27918/78A IT 2791878 A IT2791878 A IT 2791878A IT 1174447 B IT1174447 B IT 1174447B
Authority
IT
Italy
Prior art keywords
processor
perfected
perfected multi
Prior art date
Application number
IT27918/78A
Other languages
English (en)
Other versions
IT7827918A0 (it
Original Assignee
Ibm
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ibm filed Critical Ibm
Publication of IT7827918A0 publication Critical patent/IT7827918A0/it
Application granted granted Critical
Publication of IT1174447B publication Critical patent/IT1174447B/it

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0815—Cache consistency protocols
    • G06F12/0817—Cache consistency protocols using directory methods
    • G06F12/0828—Cache consistency protocols using directory methods with concurrent directory accessing, i.e. handling multiple concurrent coherency transactions

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Multi Processors (AREA)
IT27918/78A 1977-10-06 1978-09-21 Multielaboratore perfezionato IT1174447B (it)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US05/840,070 US4136386A (en) 1977-10-06 1977-10-06 Backing store access coordination in a multi-processor system

Publications (2)

Publication Number Publication Date
IT7827918A0 IT7827918A0 (it) 1978-09-21
IT1174447B true IT1174447B (it) 1987-07-01

Family

ID=25281374

Family Applications (1)

Application Number Title Priority Date Filing Date
IT27918/78A IT1174447B (it) 1977-10-06 1978-09-21 Multielaboratore perfezionato

Country Status (6)

Country Link
US (1) US4136386A (it)
JP (1) JPS5459047A (it)
DE (1) DE2841041A1 (it)
FR (1) FR2405515B1 (it)
GB (1) GB1555300A (it)
IT (1) IT1174447B (it)

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US5023776A (en) * 1988-02-22 1991-06-11 International Business Machines Corp. Store queue for a tightly coupled multiple processor configuration with two-level cache buffer storage
US5032985A (en) * 1988-07-21 1991-07-16 International Business Machines Corporation Multiprocessor system with memory fetch buffer invoked during cross-interrogation
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US5222224A (en) * 1989-02-03 1993-06-22 Digital Equipment Corporation Scheme for insuring data consistency between a plurality of cache memories and the main memory in a multi-processor system
ATE157183T1 (de) * 1989-07-06 1997-09-15 Digital Equipment Corp Eingabewarteschlange für speichersubsysteme
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JP3102495B2 (ja) * 1989-12-28 2000-10-23 株式会社日立製作所 仮想記憶管理方法
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US5249283A (en) * 1990-12-24 1993-09-28 Ncr Corporation Cache coherency method and apparatus for a multiple path interconnection network
JP2743608B2 (ja) * 1991-03-27 1998-04-22 日本電気株式会社 共有レジスタ制御方式
US5265233A (en) * 1991-05-17 1993-11-23 Sun Microsystems, Inc. Method and apparatus for providing total and partial store ordering for a memory in multi-processor system
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US5666515A (en) * 1993-02-18 1997-09-09 Unisys Corporation Information processing system having multiple modules and a memory on a bus, where any module can lock an addressable portion of the memory by sending retry signals to other modules that try to read at the locked address
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US5623628A (en) * 1994-03-02 1997-04-22 Intel Corporation Computer system and method for maintaining memory consistency in a pipelined, non-blocking caching bus request queue
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US5940826A (en) * 1997-01-07 1999-08-17 Unisys Corporation Dual XPCS for disaster recovery in multi-host computer complexes
US5949970A (en) * 1997-01-07 1999-09-07 Unisys Corporation Dual XPCS for disaster recovery
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US7305524B2 (en) * 2004-10-08 2007-12-04 International Business Machines Corporation Snoop filter directory mechanism in coherency shared memory system
US8949549B2 (en) * 2008-11-26 2015-02-03 Microsoft Corporation Management of ownership control and data movement in shared-memory systems
CN101692173B (zh) * 2009-10-16 2011-11-23 北京联合大学生物化学工程学院 双单片机共用一个串行存储器电路
US10769068B2 (en) 2017-11-10 2020-09-08 International Business Machines Corporation Concurrent modification of shared cache line by multiple processors

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US3771137A (en) * 1971-09-10 1973-11-06 Ibm Memory control in a multipurpose system utilizing a broadcast
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Also Published As

Publication number Publication date
US4136386A (en) 1979-01-23
GB1555300A (en) 1979-11-07
DE2841041A1 (de) 1979-08-09
JPS5459047A (en) 1979-05-12
FR2405515A1 (fr) 1979-05-04
JPS5733623B2 (it) 1982-07-17
IT7827918A0 (it) 1978-09-21
FR2405515B1 (fr) 1985-11-29

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Legal Events

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TA Fee payment date (situation as of event date), data collected since 19931001

Effective date: 19950928