IT1154407B - DATA PROCESSOR WITH PERFECT MEMORY MANAGEMENT - Google Patents

DATA PROCESSOR WITH PERFECT MEMORY MANAGEMENT

Info

Publication number: IT1154407B
Authority: IT; Italy
Prior art keywords: data processor; memory management; perfect memory; perfect; management
Prior art date: 1981-01-07

Application number

IT67010/82A

Other languages

Italian (it)

Other versions

IT8267010A0 (en

Inventor

Horace H Tsiang

Original Assignee

Wang Laboratories

Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)

1981-01-07

Filing date

1982-01-06

Publication date

1987-01-21

1982-01-06 Application filed by Wang Laboratories filed Critical Wang Laboratories

1982-01-06 Publication of IT8267010A0 publication Critical patent/IT8267010A0/en

1987-01-21 Application granted granted Critical

1987-01-21 Publication of IT1154407B publication Critical patent/IT1154407B/en

Classifications

- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F12/0844—Multiple simultaneous or quasi-simultaneous cache accessing
- G06F12/0855—Overlapped cache accessing, e.g. pipeline
- G06F12/0857—Overlapped cache accessing, e.g. pipeline by multiple requestors

Landscapes

Engineering & Computer Science (AREA)
Theoretical Computer Science (AREA)
Physics & Mathematics (AREA)
General Engineering & Computer Science (AREA)
General Physics & Mathematics (AREA)
Memory System Of A Hierarchy Structure (AREA)
Multi Processors (AREA)

IT67010/82A 1981-01-07 1982-01-06 DATA PROCESSOR WITH PERFECT MEMORY MANAGEMENT IT1154407B (en)

Applications Claiming Priority (1)

Application Number	Priority Date	Filing Date	Title
US22315481A	1981-01-07	1981-01-07

Publications (2)

Publication Number	Publication Date
IT8267010A0 IT8267010A0 (en)	1982-01-06
IT1154407B true IT1154407B (en)	1987-01-21

Family

ID=22835271

Family Applications (1)

Application Number	Title	Priority Date	Filing Date
IT67010/82A IT1154407B (en)	1981-01-07	1982-01-06	DATA PROCESSOR WITH PERFECT MEMORY MANAGEMENT

Country Status (10)

Country	Link
JP (1)	JPS57169990A (en)
BE (1)	BE891723A (en)
CA (1)	CA1175581A (en)
CH (1)	CH656470A5 (en)
DE (1)	DE3200042A1 (en)
FR (1)	FR2497596B1 (en)
GB (1)	GB2090681B (en)
IT (1)	IT1154407B (en)
NL (1)	NL8200043A (en)
SE (1)	SE445270B (en)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number	Priority date	Publication date	Assignee	Title
JPS617967A (en) *	1984-06-15	1986-01-14	インタ−ナショナル　ビジネス　マシ−ンズ　コ−ポレ−ション	I/o controller
AU5634086A (en) *	1985-05-06	1986-11-13	Wang Laboratories, Inc.	Information processing system with enhanced instruction execution and support control
US4814981A (en) *	1986-09-18	1989-03-21	Digital Equipment Corporation	Cache invalidate protocol for digital data processing system
DE3920883A1 (en) *	1989-06-26	1991-01-03	Siemens Ag	METHOD AND ARRANGEMENT FOR INCREASING THE PROCESSING SPEED OF THE CENTRAL UNIT OF A DATA PROCESSING SYSTEM
JPH03189845A (en) *	1989-12-13	1991-08-19	Internatl Business Mach Corp <Ibm>	Hierarchical memory system and cache memory subsystem
JPH0756815A (en) *	1993-07-28	1995-03-03	Internatl Business Mach Corp <Ibm>	Cache operating method and cache
JP5494643B2 (en)	2009-02-20	2014-05-21	旭硝子株式会社	Electret manufacturing method and electrostatic induction conversion element

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number	Priority date	Publication date	Assignee	Title
US3588829A (en) *	1968-11-14	1971-06-28	Ibm	Integrated memory system with block transfer to a buffer store
JPS51148334A (en) *	1975-06-16	1976-12-20	Hitachi Ltd	Buffer memory control method
JPS5441291A (en) *	1977-09-09	1979-04-02	Sagami Chem Res Center	Cluster fixed substance, production thereof and catalyst
US4169284A (en) *	1978-03-07	1979-09-25	International Business Machines Corporation	Cache control for concurrent access
US4208716A (en) *	1978-12-11	1980-06-17	Honeywell Information Systems Inc.	Cache arrangement for performing simultaneous read/write operations
GB2037039B (en) *	1978-12-11	1983-08-17	Honeywell Inf Systems	Cache memory system

1981
- 1981-12-29 SE SE8107832A patent/SE445270B/en not_active IP Right Cessation
1982
- 1982-01-04 DE DE19823200042 patent/DE3200042A1/en active Granted
- 1982-01-05 GB GB8200166A patent/GB2090681B/en not_active Expired
- 1982-01-06 IT IT67010/82A patent/IT1154407B/en active
- 1982-01-07 BE BE0/207010A patent/BE891723A/en not_active IP Right Cessation
- 1982-01-07 NL NL8200043A patent/NL8200043A/en unknown
- 1982-01-07 CH CH78/82A patent/CH656470A5/en not_active IP Right Cessation
- 1982-01-07 CA CA000393741A patent/CA1175581A/en not_active Expired
- 1982-01-07 FR FR828200156A patent/FR2497596B1/en not_active Expired
- 1982-01-07 JP JP57000648A patent/JPS57169990A/en active Granted

Also Published As

Publication number	Publication date
DE3200042A1 (en)	1982-08-19
GB2090681A (en)	1982-07-14
CH656470A5 (en)	1986-06-30
FR2497596B1 (en)	1989-03-03
SE8107832L (en)	1982-07-08
JPS57169990A (en)	1982-10-19
CA1175581A (en)	1984-10-02
IT8267010A0 (en)	1982-01-06
NL8200043A (en)	1982-08-02
GB2090681B (en)	1985-11-20
BE891723A (en)	1982-04-30
JPH0353657B2 (en)	1991-08-15
SE445270B (en)	1986-06-09
FR2497596A1 (en)	1982-07-09
DE3200042C2 (en)	1991-03-07

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Legal Events

Date	Code	Title	Description
1999-10-27	TA	Fee payment date (situation as of event date), data collected since 19931001	Effective date: 19980127