IL42051A - System for memorising and processing data - Google Patents

Claims (5)

1. System for memorising and processing information data, comprising an interface circuit (IP) receiving impulses emitted by peripheral devices by means of at least one terminal check device, characterized in that It consists of a taxation memor (ME) divided into two parts for the validation of the impulses and for the storing of the information, respectively, an exploration circuit by multiplexor (MX) connected on the one hand with the output of the interface circuit (IP) and, on the other hand, with an analyzer circuit (AN) permitting to effect simultaneously the identification of the person requiring the information and the accounting of the taxation memory (ME) , the said analyzing circuit (AN) validating the ta impulses.

2. System according to Claim 1, characterized in that the said analyzer (AN) is linked to a first sub-group (DA) of memory boxes, with an output register (RSE) assigned to the said sub-group, and with an adder assigned to a second sub-group (DN) of the memory, the states of the interface circuits (IF) being recorded in a cyclic manner in binary logic in the said first sub-group, the state of each circuit recorded at the preceding cycle being recorded in the output register, the said cyclic states being analysed by gate circuits of the analyzes (AN) , so that the latter accepts a charge pulse only when the cyclic scanning of the latter generates at least two consecutive levels 1 (crest of the gate pulse) followed by two consecutive levels 0 (trough of the gate pulse), the said pulse thus validated then being handled by the adder in order to be accounted in the second sub-group (DN) of the memory. 42051/2

3. System according to any of claims 1 to 4, in which the skeleton of the memory is composed of semi-conductive MOS typ boxes having a capacity of n one-bit words, the said bits bei common to a single output of the box, characterised in that t said memory \s constituted by the grouping in parallel of the said boxes, at a rate of one bit per box, the said grouping be ing divided into two sub-groups so that the first sub-group ( enabling the validation of the charge pulses is composed of a determined number (3) of boxes, and that the second sub-group (DN) enabling the storing of the number of said pulses in decimal coded binary code , is composed of a number of boxes whic may be increased by multiples of four.

4. System according to any of claims 1 to 5, in which a second part of elements is connected to a second sub-group of boxes of the memory, the said elements being constituted by an adder (AD) formed by a series of adding units such as the units ad-'der (ADU), the tens adder (ADD), the hundreds adder (ADC), the thousands adder- (ADM), the said units comprise respectively four binary weights (1, 2, 4, 8) enabling them to add a maximu of l6 bits corresponding to l6 charge pulseSj characterised in that the outputs of the weights 2 and 8 of the said elements are connected respectively to the corresponding inputs of an AND gate (Pi>) and to a first corresponding input of the exclus OR gates *(P6 and P7), the, output of the AND gate (P5) being connected up as a common point to the second input of the exclusive OR gates (P6 and P7) and to the addition input (EA) of the adder unit of the following row, the outputs of the exclusive OR gates (P6 and P7) being connected up respectively to 42051/2 the input of the memory boxes (B2, B8) for recording the weight 2 and Θ and the weight outputs 1 and 4 of the adder being connected up respectively to the inputs of the memory boxes (Bl and B4) for recording the weights 1 and 4, so that Nthe AND gate (Ρί>) may enable position 10 of the adding unit to be detected and, consequently, a bit to be transmitted to the adder unit of the following order, whereas the exclusive OR gates (P6 and P7) enable the resetting to zero of the adding unit which has reached position 10, the said adder units thus enabling the recording of the charges in decimal coded binary code in the memory.

5. System according to any of claims 1 to 6, characterised in that the address counters (CA) are linked to the said translator (TR) to which the said counters communicate the binary number of each interface circuit scanned, so that the said translator may convert the said binary numbers into geographical numbers designating the peripheral charge devices, such as telephone extension number, hotel room number, corresponding to the said interface circuits scanned. , For the Applicants DR. REINHpLD COHN AND PARTNERS