IES74961B2 - An ISDN card for a private automatic branch exchange - Google Patents

Abstract

A PABX which comprises a motherboard (1) and an ISDN card (2), both of which are provided with respective microprocessors (3,21), for controlling their respective operations. The microprocessor (21) of the ISDN card (2) operates independently of the microprocessor (3) of the motherboard (1). Communication between the motherboard (1) and the ISDN card (2) is through a mailbox circuit (43) which facilitates the transfer of messages between the motherboard (1) and the ISDN card (2) in packets of four bits, the four bit packets being transferred one at a time. Packets of a message received by the ISDN card (2) are stored in a receive buffer (44) until all the packets of the message have been received, and the message is then written into a RAM (23) of the ISDN card (2), for subsequent execution. Packets of a message received by the motherboard (1) are stored in a receiver buffer (9) until all the packets of a message are received, and the message is then written to a RAM (5) by the microprocessor (3) for subsequent execution.

Description

The present invention relates to an ISDN card for a private automatic branch exchange (PABX) for connecting into an analogue motherboard of the PABX for adapting the PABX for connection to a pair of ISDN exchange lines. The invention also relates to a PABX which comprises an analogue motherboard, with the ISDN card connected to the motherboard.

According to the invention there is provided an ISDN card for a private automatic branch exchange (PABX) for connecting into an analogue motherboard of the PABX for adapting the PABX for connection to a pair of ISDN exchange lines, the ISDN card comprising a microprocessor for controlling the ISDN card, a readonly memory (ROM) for storing firmwear for controlling the microprocessor, a random access memory (RAM) for storing commands and data to be transferred between the ISDN card and the motherboard, an ISDN interface means for interfacing the ISDN card with at least one analogue exchange line under the control of the microprocessor, and an analogue interface means for interfacing the ISDN card with a pair of ISDN lines under the control of the microprocessor, a communicating means for communicating the ISDN card with the motherboard through a four wire communicating system through which addresses, data and commands are transmitted between the ISDN card and the motherboard in packets each of four bits, one packet at a time, the 5 packets being temporarily stored in the communicating means until read therefrom, and a flag means for indicating the status of the communicating means.

In one embodiment of the invention a receive buffer is provided for storing the four bit packets of a message until all the packets of the message have been received from the communicating means, at which stage the respective messages are transferred to the RAM for subsequent execution by the microprocessor.

In another embodiment of the invention each message for the motherboard from the ISDN card is divided into four bit packets and a transmit buffer is provided for storing the packets of a message to be transmitted to the motherboard until the message has been transmitted through the communicating means to the motherboard.

In one embodiment of the invention the communicating means comprises a fifth control wire for transmitting a clock signal with each four bit packet.

In another embodiment of the invention the communicating means comprises a sixth and a seventh wire for communicating the flag means with the motherboard. Preferably, one of the sixth and seventh wires communicates the flag means for indicating to the motherboard that the ISDN card has read a previously transmitted packet from the communicating means, and the other of the sixth and seventh wires communicates the flag means for indicating to the motherboard that a packet is stored in the communicating means which is to be read by the motherboard.

In another embodiment of the invention the communicating means comprises an eighth wire for facilitating transmission of a select signal between the ISDN card and the motherboard.

In a further embodiment of the invention the communicating means comprises a ninth wire for applying a signal for latching each four bit packet to the receive buffer and from the transmit buffer.

Preferably, the ISDN card operates under the control of a subroutine for seizing one or both of the ISDN exchange lines.

Advantageously, the subroutine seizes the ISDN exchange line on the microprocessor receiving a message through the communicating means from the motherboard instructing the ISDN card to seize the one or both ISDN exchange lines.

Additionally, the invention provides a PABX comprising 5 an analogue motherboard having provision for receiving at least two exchange lines, and one extension line, and an ISDN card according to the invention connected to the motherboard by the communicating means, the motherboard comprising a microprocessor, and the respective microprocessors of the ISDN card and the motherboard communicating entirely through the communicating means .

In one embodiment of the invention a receive buffer is provided on the motherboard for storing the respective four bit packets of a message received from the ISDN card until all packets of the message have been received, and the stored packets forming the message are then read by the microprocessor of the motherboard and executed.

In another embodiment of the invention the microprocessor on the ISDN card operates independently of the microprocessor on the motherboard.

In another embodiment of the invention the microprocessor on the motherboard on power up of the PABX operates under the control of a first subroutine which tests if the ISDN card is installed by issuing a predetermined first test signal on the communicating means, and awaits a first predetermined response on the communicating means from the ISDN card.

In a further embodiment of the invention the microprocessor on the motherboard operates under the control of a second subroutine for issuing a second predetermined test signal for determining if the ISDN card is connected to a pair of ISDN exchange lines, and awaits a second predetermined response on the communicating means from the ISDN card indicating that the ISDN card is connected to a pair of ISDN exchange lines.

The invention will be more clearly understood from the following description of a preferred embodiment thereof which is given by way of example only with reference to the accompanying drawings, in which: Fig. 1 is a circuit diagram of a PABX according to the invention comprising a motherboard and an ISDN card also according to the invention connected to the motherboard, Figs. 2 to 4 are representations of signals communicating addresses, data and commands between the motherboard and the ISDN card of Fig. 1.

Referring to the drawings and initially to Fig. 1, there is illustrated a circuit diagram of a PABX which comprises an analogue motherboard indicated generally by the reference numeral 1, and an ISDN card also according to the invention indicated generally by the reference numeral 2 connected to the analogue motherboard, for adapting the PABX for connection to a pair of ISDN exchange lines.

The motherboard 1 comprises a microprocessor 3 for controlling the motherboard 1. A read-only memory (ROM) 4 stores firmwear controlling the microprocessor 3. A random access memory (RAM) 5 stores data and commands to be executed by the microprocessor 3. An interface circuit 6, the details of which are not illustrated in Fig. 1, but will be well known to those skilled in the art interfaces the motherboard 1 with two analogue exchange lines which may be connected to the motherboard 1. An interface circuit 7, the details of which are also not illustrated in Fig. 1 interfaces the motherboard 1 with extension lines. In this embodiment of the invention the motherboard has the capacity to receive eight extension lines. An interface circuit 8 is provided on the motherboard 1 for interfacing the motherboard 1 with the ISDN card 2 as will be described below. A receive buffer 9 on the motherboard 1 is provided for storing messages in four bit packets received from the ISDN card 2, and a transmit buffer 10 is provided on the motherboard 1 for storing messages in four bit packets to be transmitted to the ISDN card 2.

A microprocessor 21 on the ISDN card 2 controls the operation of the ISDN card 2, and operates independently of the microprocessor 3 on the motherboard 1. A read-only memory (ROM) 22 stores firmwear for controlling the microprocessor 21, and a random access memory (RAM) 23 stores data and commands to be executed by the microprocessor 21. An ISDN interface means for interfacing the ISDN card 2 with two ISDN exchange lines, comprises an ISAC-S chip 25 which is supplied by Siemens. The interface means also comprises a transformer/choke assembly, namely, an APC9017TX1 module 26 which includes a transmit and receive transformer. An analogue interface means, namely, an analogue to digital converter is provided by a SICOFI chip 27, which is located between the ISAC-S chip 25 and the APC9017TX1 module 26 for interfacing the ISDN card 2 with two analogue exchange lines. An output port 28 on the ISDN card 2 is provided from the APC9017TX1 module 26 for receiving a cable (not shown) which terminates in an RJ45 jack plug for connecting the ISDN card 2 into the two ISDN exchange lines. A connector 34, which is illustrated in broken lines, is also provided on the ISDN card 2 from the APC9017TX1 module 26 for connecting into a corresponding connector (not shown) on the motherboard 1, for in turn facilitating the connection of the output from the APC9017TX1 module 26 to be connected to the interface circuit 6 on the motherboard 1 for facilitating connection of the ISDN card 2 to two analogue exchange lines through the motherboard 1. Two transformers 29 and 30 are provided for also connecting the ISDN card 2 to two analogue exchange lines.

The ISDN card 2 and the motherboard 1 communicate through a connecting means, in this embodiment of the invention provided by a mailbox circuit 43 located on the ISDN card 2 and operated under the control of the microprocessor 21. The mailbox circuit 43 is connected to the motherboard 1 by a nine-wire connection, which is implemented by nine parallel sockets 40 located on the motherboard 1 which are connected to the interface circuit 8, and nine pin connectors 41 which are located on the ISDN card 2 and are connected to the mailbox circuit 43, and are releasably engagable with the sockets 40. All communications between the motherboard and the ISDN card 2 are carried out through the mailbox circuit 43. Four of the sockets 40 and pins 41 are address and data paths, namely, the paths a & dlz a & d2, a & d4, and a & d8. Address and data is transferred between the motherboard 1 and the ISDN card in packets each of four bits, one packet at a time, in other words, four bits at a time. The remaining five sockets 40 and pins 41 form paths for controlling the transfer of addresses and data between the motherboard 1 and the ISDN card 2. One of the paths, namely, the path sel2 is a select line as will be described below. Another of the paths, namely, the P_ALE path acts in combination with the paths rdl and lpl for acting as a flagging means for indicating to the microprocessor 3 of the motherboard 1 the status of the mailbox circuit 43. The last of the nine paths, namely, the xchl path carries a clock signal between the interface circuit 8 on the motherboard 1 and the mailbox circuit 43.

The mailbox circuit 43 is configured for storing a four bit packet until it has been read by the microprocessor 21 of the ISDN card 2 or the microprocessor 3 of the motherboard 1, depending on the direction of flow of messages. Messages which are to be transferred between the motherboard 1 and the ISDN card 2 are formed into four bit packets. Each message to be transmitted from the motherboard 1 to the ISDN card 2 when formed into a series of eight bit packets is stored in the transmit buffer 10, and transmitted one packet at a time through the mailbox circuit 43. The packets forming a message are latched into a receive buffer 44 on the ISDN card 2 and are stored in the receive buffer 44 until all the packets of a message have been received. At that stage the message is transferred to the ram 23 by the microprocessor 21. A transmit buffer 45 is provided on the ISDN card 2 for storing the four bit packets of a message to be transmitted from the ISDN card 2 to the motherboard 1 until all the packets of the message have been transmitted through the mailbox circuit 43. The four bit packets are read by the microprocessor 3 of the motherboard 1 one at a time from the mailbox circuit 43 and are latched into the receive buffer 9 until all the packets of the message have been received. The message is then transferred from the receive buffer 9 to the RAM 5 of the motherboard 1 for subsequent execution by the microprocessor 3.

Referring now to Figs. 2 to 4 the operation of the mailbox circuit 43 will now be described. Before the motherboard 1 can read or write to the ISDN card 2 it must first observe the present situation and it does this by monitoring the state of the flags /MP21_WR_FLAG and /MP21_RD_FLAG, see Fig. 2. To do this the following steps are taken: 1. When the address on the A&D bus is set and P_ALE pulses low the address is latched into the receive buffer 44. 2. When sel2 pulses high it causes /MOTHERBOARD1_STATUS to pulse low which in turn causes status flags to be placed on the A&D bus.

If /MP21_WR_FLAG is low the motherboard knows that the ISDN card 2 has read the previous four bit packet and can now receive the next four bit packet of a message.

If /MP21_RD_FLAG is high the motherboard knows that there is a new four bit packet to be read from the ISDN card.

After examining the flags to see if the microprocessor 15 21 has read the previous four bit packet and if it has then the motherboard will write the next four bit packet to the mailbox circuit 43.

This is carried out in the sequence illustrated in Fig. 3. 1. When the A&D lines are set and P_ALE pulses low the address is latched into the receiver buffer 44. 2. When a four bit packet is placed on the A&D bus and SEL2 pulses high it causes /MOTHERBOARD1_WRITE to go low. The four bit packet is latched into IC12 on the rising edge of /MOTHERBOARD1_WRITE. 3. When /MOTHERBOARD1_WRITE goes low it causes the /MP21_WR_FLAG to be set high indicating to the motherboard that no more four bit packets should be sent. At the same time an interrupt is sent to the microprocessor 21 to tell it that a four bit packet is ready to be read. When the microprocessor 21 reads the four bit packet the /MP21_WR_FLAG is again set to low and therefore indicates to the motherboard 1 that the next four bit packet may be sent.

If when the motherboard checks the flags and discovers that the microprocessor 21 has written the four bit packet to the transmit buffer 45, for example, /MP21_RD_FLAG is high, then the sequence illustrated in Fig. 4 is undertaken in order that the four bit packet may be read to the motherboard 1. 1. When the A&D lines are set and P_ALE pulses low this address is latched into the mailbox circuit 43. 2. When SEL2 pulses high it causes /MOTHERBOARD_RD to pulse low which in turn causes a four bit packet to be placed on the A&D bus . 3. On the rising edge of the /MOTHERBOARD_RD signal the flags are set on to indicate to the microprocessor 21 that the four bit packet has been read.

The following is a brief description of communication between the motherboard 1 and the ISDN card 2. Every five milliseconds a main programme controlling the microprocessor 3 checks the mailbox circuit 43. It first checks if there is a read four bit packet from the ISDN card 2 waiting in the mailbox circuit 43. If there is, then the 4-bit packet is read and saved in the receive buffer 9. Next it checks if there is a write four bit packet for the ISDN card 2 in the transmit buffer 10. If there is then it checks whether the ISDN card 2 is ready to receive more four bit packets. If it is ready then the main programme controlling the microprocessor 3 gets the packet from the transmit buffer 10 and writes it into the mailbox circuit 43. If the ISDN card 2 is not ready then the main programme controlling the microprocessor 3 will try again during the next interrupt.

After power up, the motherboard 1 executes its normal power up routines. It then initialises the pointers and buffers used for the ISDN card 2. Next the main programme controlling the microprocessor 3 tests if an ISDN card 2 is installed or not. It sends a test message, namely, a Parameters message to the ISDN card 2 and waits for a response from the ISDN card 2. The ISDN card 2 should respond by sending a Parameter Acknowledge message. If a correct response is received, this means that an ISDN card 2 is installed. If no response is received, the main programme controlling the microprocessor 3 will send another Parameters message and wait for a response. If there is still no response, this means that an ISDN card 2 is not installed and the corresponding exchange lines are analogue.

If an ISDN card 2 is installed the main programme controlling the microprocessor 3 tests if the corresponding exchange lines are connected to ISDN exchange lines. This is implemented by modifying the existing exchange line states which were used for testing analogue lines. For each ISDN exchange line, it sends a Setup message to the ISDN card 2 and waits for the ISDN card 2 to respond with a Seized message. If a Seized message is received the main programme controlling the microprocessor 3 marks the exchange line as connected. But if a correct response is not received, it marks the exchange line as not connected and will repeat the test every five minutes approximately.

A main scan loop in the main programme controlling the microprocessor 3 does most of the high level work such as the extension and the exchange line finite state machines. Also in the main loop the main programme controlling the microprocessor 3 checks whether there is a full message from the ISDN card 2 waiting in the receive buffer 2.

If there is a full message ready then the main programme controlling the microprocessor 3 takes the message. It validates the message, decodes the message and then takes the appropriate action that its required. In most cases, this will consist of sending an internal message to the state for the ISDN exchange line. Examples of messages are Incoming call, Incoming MSN call, Channel Seized, Call Connect and Call Disconnect. Any further actions required will be implemented by the appropriate exchange line states.

The handling of incoming calls on the ISDN exchange lines by the motherboard 1 is as follows. In the states which handle incoming calls, the microprocessor 3 can handle ISDN card 2 messages Incoming call and Incoming MSN call. If either message is detected then the state programme starts ringing the appropriate extension. It also sends a Ringing message to the ISDN card 2 to indicate that the call is being handled.

This is done by a dedicated routine which generates the full Ringing message in a temporary buffer (not shown). Then a routine is called which moves the message from the temporary buffer (not shown) into the next free position in the transmit buffer 10. Once in the transmit buffer 10, a mailbox circuit 43 write routine sends the message to the ISDN card 2 in the four bit packets .

Once the Ringing message has been sent the handling of an incoming ISDN call is the same as that for an analogue call. So the same states are used until an extension answers the incoming call. When an ISDN call is answered then a Connect message is sent to the ISDN card 2. This is done by calling a dedicated routine which generates the Connect message. Once the Connect message is sent, the extension and the external party are connected the same as for an analogue call.

When the call is completed either party can terminate the call by hanging up. If the extension hangs up, then the exchange line executes the normal clear down states as for an analogue line. But in addition it sends a Disconnect message to the ISDN card 2 to terminate the call. The exchange line then enters the idle state and starts testing for new messages. Unlike analogue exchange lines, an ISDN exchange line can terminate a call by hanging up. In this case the corresponding exchange line states check for a Disconnect message from the ISDN card 2. If Disconnect is detected then the ISDN exchange line disconnects itself from the extension, informs the extension and then executes the normal clear down states.

In order to initiate an outgoing call the main programme controlling the microprocessor 3 calls a dedicated routine which sends a Setup message to the ISDN card 2. For normal, manually dialled calls overlap dialling mode is used. For speed dialling numbers and last number redial, enbloc dialling mode is used where the Setup message contains the full external number to be dialled. After sending the Setup message, the microprocessor 3 waits for a Seized message from the ISDN card 2.

When a Seized message is received when using enbloc dialling, the microprocessor 3 waits for a Connect message from the ISDN card 2. When a Seized message is received when using overlap dialling, the microprocessor 3 sends each digit to the ISDN card 2 5 using Digit messages. This is done by calling a dedicated routine which sends a Digit message to the ISDN card 2. When all the digits have been sent, the microprocessor 3 waits for a Connect message. Once a Connect message is received from the ISDN card 2, the extension and the external party are connected the same as for an analogue call. When the call is completed either party can terminate the call by hanging up, similar to incoming calls.

The invention is not limited to the embodiment hereinbefore described which may be varied in construction and detail.

Claims (5)

1. An ISDN card for a private automatic branch exchange (PABX) for connecting into an analogue motherboard of the PABX for adapting the PABX for connection to a pair of ISDN exchange lines, the ISDN card comprising a microprocessor for controlling the ISDN card, a read-only memory (ROM) for storing firmwear for controlling the microprocessor, a random access memory (RAM) for storing commands and data to be transferred between the ISDN card and the motherboard, an ISDN interface means for interfacing the ISDN card with at least one analogue exchange line under the control of the microprocessor, and an analogue interface means for interfacing the ISDN card with a pair of ISDN lines under the control of the microprocessor, a communicating means for communicating the ISDN card with the motherboard through a four wire communicating system through which addresses, data and commands are transmitted between the ISDN card and the motherboard in packets each of four bits, one packet at a time, the packets being temporarily stored in the communicating means until read therefrom, and a flag means for indicating the status of the communicating means .

2. An ISDN card as claimed in Claim 1 in which a receive buffer is provided for storing the four bit packets of a message until all the packets of the message have been received from the communicating means, at which stage the respective messages are transferred to the RAM for subsequent execution by the 5 microprocessor, and a transmit buffer is provided for storing the packets of a message to be transmitted to the motherboard until the message has been transmitted through the communicating means to the motherboard.

3. An ISDN card substantially as described herein 10 with reference to and as illustrated in the accompanying drawings .

4. A PABX comprising an analogue motherboard having provision for receiving at least two exchange lines, and one extension line, and an ISDN card as claimed in 15 any preceding claim connected to the motherboard by the communicating means, the motherboard comprising a microprocessor, and the respective microprocessors of the ISDN card and the motherboard communicating entirely through the communicating means. 20

5. A PABX substantially as described herein with reference to and as illustrated in the accompanying drawings .