IE85200B1 - A method and device for interfacing two incompatible devices - Google Patents

Description

A method and device for interfacing two incompatible devices The present invention relates to a method and a device for interfacing two incompatible devices, and in particular, the invention relates to a CAPl-to- Synchronous serial bridge device for providing a communication link between a Common Application lSDN Programming interface (CAPl) compatible device and a synchronous serial compatible device.

Telecommunication standards provide the industry with a framework which allows telecommunications devices from varioustelecommunications solution providers to communicate with each other. Low to medium cost telecommunications devices such as mobile phones and computers have a relatively short technology life span.

Demand by consumers for the latest available features ensures that these devices are constantly upgraded to the latest technology and are designed to be compatible with the latest standards. The establishment of integrated Services Digital Network (lSDN) networks and the associated telecommunications revolution has resulted in a telecommunication standard known as Common Application lSDN Programming Interface (CAPI) which provides a framework for developers of lSDN hardware and software solutions, which standardises the industry for developing compatible solutions.

However, the technology associated with high cost telecommunications devices such as non-standard encryption devices have a much longer life span. Due to the relatively small number of consumers which require such high cost devices as compared with the demand for mobile phones, and the relatively high cost associated with upgrading such devices, the technology associated with such devices and the telecommunications standards associated with them is archaic when compared with modern telecommunications devices. Such archaic devices are still capable of adequately fulfilling their primary role in a modern telecommunications network. However, due to the fact, in general, such devices were provided to be synchronous serial compatible they are unsuitable for communicating directly with modern CAPI compatible devices. Most modern telecommunications networks tend to incorporate CAPl compatible devices such as PCs and laptop computers. Typically in mobile hardware solutions, routers are required to interface modern CAPI technology with synchronous serial hardware.

There is therefore a need for a device for facilitating communication between a CAPI compatible device and a synchronous serial compatible device without the need to incorporate relatively expensive hardware in a telecommunications network.

The present invention is directed towards providing such a device, and the invention is also directed towards providing a method for interfacing two incompatible devices with each other.

According to the invention there is provided a CAPI-to-Synchronous serial bridge device for interfacing a CAPI compatible first device and a synchronous serial compatible second device, the CAPI-to-Synchronous serial bridge device comprising a first receiving means for receiving a CAPI message from the first device, an executing means for converting the received CAPI message to a synchronous command, a first relaying means for relaying the synchronous command to the second device, a second receiving means for receiving data from the second device in response to the synchronous command, a second relaying means for relaying the data received from the second device to the first device, and a control means for controlling the operation of the CAPI-to-Synchronous serial bridge device, wherein a storing means is provided for storing predetermined operating instructions as CAPI software functions cross-referenced with corresponding synchronous commands, and the executing means is responsive to a received CAPI message for reading the corresponding synchronous command from the storing means for converting the received CAPI message to a synchronous command. in one embodiment of the invention the control means comprises a first establishing means for establishing if the second device is operable to interface with the CAPI-to- Synchronous serial bridge device. in a further embodiment of the invention the predetermined operating instructions instruct the first device to provide a framework for facilitating the communication of data between the second device and the first device.

Preferably, the storing means is accessible to the first device for reading instructions stored thereon. Advantageously, the storing means is provided by an electronic storing means.

In one embodiment of the invention the storing means is provided by at least one compact disk.

In another embodiment of the invention the control means is operable to access resources located on the first device. Preferably, the control means is operable to access memory located on the first device.

In one embodiment of the invention the control means comprises a second establishing means for establishing if data is available from the second device.

In another embodiment of the invention a CAPI compatible interface means is provided for interfacing with the first device and a synchronous serial interface means is provided for interfacing with the second device. Preferably, the CAPI compatible interface means is directly linked to the first device. Advantageously, the CAPI compatible interface means is operable to receive CAPI messages from at least one CAPI application which is co-operable with the first device for communicating data.

In one embodiment of the invention a monitoring means is provided for monitoring incoming data to the CAPI-to-Synchronous serial bridge device from the first device for identifying if a CAP| message is received.

In another embodiment of the invention the control means is responsive to the monitoring means detecting a first request message from the first device for initiating communication between the first device and the CAPI-to-Synchronous serial bridge device. Preferably, the control means is responsive to the monitoring means detecting the first request message from the first device for allocating memory for storing further CAPI messages received from the first device.

In another embodiment of the invention the control means is adapted for allocating the memory for storing further CAPI messages in the first device.

In a further embodiment of the invention the control means is responsive to the monitoring means detecting a release message from the first device for releasing the allocated memory, and releasing communication established between the first device and the CAPI-to-Synchronous serial bridge device. Preferably, the control means is responsive to the monitoring means detecting the release message being received within a first predetermined time period from receipt of the first message for releasing the allocated memory and releasing communication established between the first device and the CAPI-to-Synchronous serial bridge device.

In another embodiment of the invention the control means is responsive to the monitoring means detecting a connect message received from the first device for establishing communication between the first device and the second device.

Preferably, the control means is responsive to the monitoring means detecting the connect message being received from the first device within a second predetermined time period. Advantageously, the second predetermined time period commences at the end of the first time period.

In one embodiment of the invention the control means is responsive to the monitoring means detecting the listen from the first device for preparing the synchronous serial interface means for receiving and transmitting data between the CAPI-to-Synchronous serial device and the second device. Preferably, the control means is responsive to the monitoring means detecting the listen message being received within a third predetermined time period for preparing the synchronous serial interface means for receiving and transmitting data between the CAPI-to- Synchronous serial device and the second device. Advantageously, the third predetermined time period commences at the end of the second predetermined time period. lx) LII In a further embodiment of the invention the control means is responsive to the monitoring means detecting the connect message from the first device for activating the synchronous serial interface means for receiving and transmitting data between the CAP|—to-Synchronous serial bridge device and the second device. Preferably, the control means is responsive to the monitoring means detecting the connect message from the first device for setting an indicating means for indicating to the second device that the CAP|—to-Synchronous serial bridge device is operable to interface with the second device.

In one embodiment of the invention the first establishing means is responsive to the monitoring means detecting the connect message for determining if the second device is operable to interface with the CAP|—to-Synchronous serial bridge device.

Preferably, the first establishing means is responsive to the monitoring means detecting the connect message for determining if the second device is operable within a fourth predetermined time period for interfacing with the CAP|—to- Synchronous serial bridge device. Advantageously, the fourth predetermined time period commences at the end of the third predetermined time period.

In one embodiment of the invention the control means is responsive to the monitoring means detecting the release message for releasing the allocated memory and releasing communication established between the first device and the CAP|—to- Synchronous serial bridge device if the second device is not operable to interface with the CAP|—to-Synchronous serial bridge device during the fourth predetermined time period.

In another embodiment of the invention the control means is responsive to the monitoring means detecting the release message from the first device during a fifth predetermined time period for releasing the allocated memory and the communication established between the first device and the CAP|—to-Synchronous serial bridge device. Preferably, the fifth predetermined time period commences at the end of the fourth predetermined time period.

In another embodiment of the invention the control means is responsive to the monitoring means detecting a disconnect message for operating the monitoring means to monitor for the release message. Preferably, the control means is responsive to the monitoring means detecting the disconnect message within a sixth predetermined time period for operating the monitoring means to monitor for the release message. Advantageously, the sixth predetermined time period commences at the end of the fifth predetermined time period.

In a further embodiment of the invention the control means is responsive to the second device not being operable within a seventh predetermined time period after the sixth predetermined time period for operating the monitoring means to monitor for the release message.

In one embodiment of the invention the control means is responsive to the monitoring means detecting a data request message from the first device for converting the data request message to a synchronous command for initiating data transmission from the second device to the first device.

Preferably, the control means is responsive to the monitoring means detecting the data request message from the first device within an eighth predetermined time period for converting the data request message to a synchronous command for initiating data transmission between the second device and the first device.

Advantageously, the eighth predetermined time period commences at the end of the seventh predetermined time period.

Preferably, the second establishing means is responsive to the data request message for determining if data is available from the second device.

Advantageously, the second establishing means is responsive to the data request message being received within a ninth predetermined time period for determining if data is available from the second device, and preferably, the ninth predetermined time period commences at the end of the eighth predetermined time period.

In one embodiment of the invention the control means is responsive to the second establishing means for operating the second receiving means for retrieving data from Q: ‘.11 the second device.

In another embodiment of the invention the control means is responsive to the second receiving means retrieving data from the second device for relaying the retrieved data to the first device for communicating to the at least one CAPI application. in one embodiment of the invention the control means comprises a central processing unit, and the central processing unit is programmed to act as the monitoring means, the first establishing means, the second establishing means, the executing means, the first receiving means, the second receiving means, the first relaying means, and the second relaying means.

In another embodiment of the invention the CAPI-to-synchronous serial bridge device is provided in the form of a Personal Computer Memory Card International Association (PCMCIA) card. in another embodiment of the invention a Peripheral Component Interconnect (PCI) card is provided.

The invention also provides a method for communicating between a CAPI compatible first device and a synchronous serial compatible second device, the method comprising the steps of providing a CAPI-to-Synchronous serial bridge device for interfacing the CAPl compatible first device and the synchronous serial compatible second device, providing a first receiving means in the CAPI-to- Synchronous serial bridge device for receiving a CAPI message from the first device, providing an executing means in the CAPI-to-Synchronous serial bridge device for converting the received CAPI message to a synchronous command, providing a first relaying means in the CAPI-to-Synchronous serial bridge device for relaying the synchronous command to the second device, providing a second receiving means in the CAPI-to-Synchronous serial bridge device for receiving data from the second device in response to the synchronous command, and providing a second relaying means in the CAPI-to-Synchronous serial bridge device for relaying the data received from the second device to the first device, wherein the method further comprises providing a storing means for storing predetermined operating instructions as CAPI software instructions cross-referenced with corresponding synchronous commands, and providing the executing means to be responsive to a received CAPI message for reading the corresponding synchronous command from the storing means for converting the CAPI message to a synchronous command. in one embodiment of the invention the method further comprises the steps of operating the first receiving means for receiving a CAPI message from the first device, operating the executing means for converting the received CAPI message to a synchronous command, operating the first relaying means for relaying the synchronous command to the second device, operating the second receiving means for receiving data from the second device in response to the synchronous command, and operating the second relaying means for relaying the data received from the second device to the first device.

The invention will be more clearly understood from the following description of a preferred embodiment thereof, which is given by way of example only, with reference to the accompanying drawings: Fig. 1 is a block diagram of a CAPI-to-Synchronous serial bridge device according to the invention for interfacing a CAPI compatible first device and a synchronous serial compatible second device, Fig. 2 is a block diagram illustrating the system level of a communication system utilising the device of Fig. 1, Fig. 3 is a block diagram of the communication system of Fig. 2, and Fig. 4 is a flow chart representation of a sub-routine of a computer programme for controlling the operation of the CAPI-to-Synchronous serial bridge device of Fig. 1.

Referring to the drawings, there is illustrated a CAPI-to-Synchronous serial bridge device according to the invention indicated generally by the reference numeral 1 for interfacing a CAPI compatible first device, in this case a laptop computer 2, with a synchronous serial compatible second device, in this case an encryption device 3, see Fig. 3. The CAPI-to-Synchronous serial bridge device 1 comprises a Personal Computer Memory Card international Association (PCMCIA) card 6, see Fig. 1, for inserting in a PCMCIA slot of the laptop computer 2. The PCMCIA card 6 comprises a control means provided by a microprocessor 7 for controlling the overall operations of the PCMCIA card 6. A storing means comprising a compact disk (CD) 9 stores operating instructions for instructing the laptop computer 2 to provide a CAPl interface layer 10 for facilitating the communication of data between the laptop computer 2 and the CAPI-to-Synchronous serial bridge device 1, see Fig. 2. The CD 9 also stores predetermined instructions as CAPl software functions for instructing the microprocessor 7 to convert received CAPl messages into corresponding synchronous commands, with the synchronous commands cross-referenced with the CAPl messages, and drivers for allowing the hardware of the PCMCIA card 6 communicate with the hardware of the laptop computer 2. A CAPl compatible interface means on the PCMCIA card 6 is provided by a PCMCIA plug 12 which is operable for releasably engaging the corresponding PCMCIA slot (not shown) of the laptop computer 2 for directly coupling the PCMCIA card 6 to the laptop computer 2.

A synchronous serial interface means on the PCMCIA card 6 is provided by a port which is adapted for receiving a connector 16 of a data bus 18 for communicating data between the encryption device 3 and the CAPI-to-Synchronous serial bridge device 1.

A central processing unit (not shown) of the laptop computer 2 is communicable with a plurality of CAPl applications 20 which are installed on the laptop computer 2. The CAPI-to-Synchronous serial bridge device 1 is operable to receive a CAPl message from any one of the CAP! applications 20 at any one time. The CAPI-to- Synchronous serial bridge device 1 appears to the operating system of the laptop computer 2 as a CAPl service provider. The encryption device 3, the laptop computer 2, the CAPI-to-Synchronous serial bridge device 1 and any one of CAP] applications 20, form a communication system 26 which facilitates the exchange of data between the two incompatible devices, namely, the CAPl application 20 in the laptop computer 2 and the encryption device 3.

In this embodiment of the invention, the microprocessor 7 is programmed to operate as a first receiving means for receiving CAPl messages from any one of the CAPl applications 20, an executing means for converting received CAPl messages to corresponding synchronous commands, a first relaying means for relaying synchronous commands to the encryption device 3 via plug 12, a second receiving means for receiving data from the encryption device 3 in response to the encryption device 3 receiving a synchronous command from one of the CAPI applications 20, and a second relaying means for relaying data received from the encryption device 3 via port 15 to the laptop computer 2. The microprocessor is also programmed to operate as a first establishing means for establishing if the encryption device 3 is operable to interface with the PVMCIA card 6, and as a second establishing means for establishing if data is available from the encryption device 3.

An example of the operation of the system 26 will be given with a description of the system operating with one of the CAPI applications 20, which is a CAPI cryptographic application 23. An interface communication link is opened between the cryptographic application 23 and the encryption device 3 by the cryptographic application 23 logging its presence to the CAPI-to-Synchronous serial bridge device 1. The cryptographic application 23 logs its presence to the CAPI-to-Synchronous serial bridge device 1 by sending a request in the format of a CAPI message, as will be described below, to the CAPI-to-Synchronous serial bridge device 1 via the CAPI interface layer 10 of the laptop computer 2. The microprocessor 7 allocates memory (not shown) located in the laptop computer 2 for dealing with further requests from the cryptographic application 23, and monitors to establish if further requests are received from the cryptographic application 23. If the CAPI-to-Synchronous serial bridge device 1 receives a further request from the cryptographic application 23, the microprocessor 7 executes an operation in response to the received request. The microprocessor 7 ceases to monitor for further requests from the cryptographic application 23 when the cryptographic application 23 logs off from the CAPI-to- Synchronous serial bridge device 1, and the memory which was allocated by the microprocessor 7 is released.

The microprocessor 7 monitors incoming data to the CAPI-to-Synchronous serial bridge device 1 from the cryptographic application 23 for command messages for interfacing the cryptographic application 23 with the encryption device 3. The command messages for which monitoring is carried out by the microprocessor 7 are as follows. A first request message, namely, a CAPl_REGlSTER message is issued by the cryptographic application 23 for logging its presence with the CAPI-to- Synchronous serial bridge device 1 for informing the microprocessor 7 what memory requirements and resources are needed by the cryptographic application 23. On receipt of the CAPl_REG|STER message the microprocessor 7 allocates specific memory and resources (not shown) in the laptop computer 2 for dealing with further messages from the cryptographic application 23, and the microprocessor 7 monitors for the next message from the cryptographic application 23.

A release message, namely, a CAPl_RELEASE message is sent by the cryptographic application 23 for logging off its presence from the CAPI-to- Synchronous serial bridge device 1. On receipt of a CAPl_RELEASE message the microprocessor 7 releases the established link between the cryptographic application 23 and the CAPI-to-Synchronous serial bridge device 1, it also instructs the microprocessor 7 to release memory and resources in the laptop computer 2 which had been allocated in response to the CAP|_REGlSTER message, and the microprocessor 7 monitors for the next CAPl_REGlSTER message.

A connect message, namely, a CONNECT_REQ message is issued by the cryptographic application 23 to indicate that the port 15 is to be activated for receiving and transmitting data between the laptop computer 2 and the encryption device 3, and to initiate a dial sequence on the CAPI-to-Synchronous serial bridge device 1 for creating an active connection between the cryptographic application 23 and the encryption device 3. The microprocessor 7 on receipt of a CONNECT_REQ message generates an indicating means in the format of a Data Terminal Ready (DTR) signal, which is relayed to the encryption device 3 to indicate to the encryption device 3 that communication is being established between the cryptographic application 23 and the encryption device 3.

A listen message, namely, a LlSTEN_REQ message is issued by the cryptographic application 23 to indicate that the port 15 is to be prepared for transmitting and receiving data between the CAPI-to-Synchronous serial bridge device 1 and the encryption device 3, and to inform the CAPI-to-Synchronous serial bridge device 1 that the cryptographic application 23 will in the future require an active connection between the cryptographic application 23 and the encryption device 3, however, the connection remains inactive until the cryptographic application 23 subsequently instructs the CAPI-to-Synchronous serial bridge device 1 to create an active connection. No data can be communicated between the cryptographic Application 23 and the encryption device 3 until an active connection is re-established.

A disconnect message, namely, a DlSCONNECT_REQ message issued by the cryptographic application 23 indicates that the active connection between the cryptographic Application 23 and the encryption device 3 should be terminated. The microprocessor 7 in response to the D|SCONNECT_REQ message deactivates the active connection.

A data request message, namely, a DATA_B3_REQ message is issued by the cryptographic application 23 to indicate that the microprocessor 7 is to initiate the transmission of data between the encryption device 3 and the cryptographic application 23. The DATA_B3_REQ contains a pointer which addresses a memory location on the laptop computer 2 where data on the laptop computer 2 is stored for transmission to the encryption device 3. The microprocessor 7 retrieves the data from the memory location addressed by the pointer and relays it to the encryption device 3.

Synchronous commands which are installed from the CD 9 and saved on the laptop computer 2 allow the microprocessor 7 to cross reference CAPI messages with synchronous commands. When a synchronous command is stored at the address of the pointer, the microprocessor 7 retrieves the synchronous command and relays it to the encryption device 3, the encryption device 3 operates accordingly in response to the received synchronous command.

Operation of the CAPI-to-Synchronous serial bridge device 1 in response to the messages received from the cryptographic application 23 will now be described with reference to Fig. 4, which illustrates a flow chart of a sub-routine of a computer programme for controlling the operation of the CAPI-to-Synchronous serial bridge device.

Block 30 monitors for a CAPl_REG|STER message from the cryptographic application 23, and on a CAPl_REGlSTER message being received, the sub-routine is activated and allocates memory (not shown) located in the laptop computer 2 for storing subsequent CAPl messages received from the cryptographic application 23.

The sub-routine then moves to block 31, which determines if a CAPLRELEASE message is received during a first predetermined time period of 10 milliseconds after receipt of the CAPl_REG|STER message. If block 31 determines that a CAPl_RELEASE message is received within the first predetermined time period, the sub—routine moves to block 32, which causes the sub-routine to terminate, resulting in the microprocessor 7 releasing the memory which has been allocated in the laptop computer 2, and releasing the communication link between the cryptographic application 23 and the CAPl-to-Synchronous serial bridge device 1. The sub-routine is then returned to block 30, which awaits the next CAPl_REG|STER message from either the cryptographic application 23 or another one of the CAPl applications 20.

If block 31 determines that a CAP|_RELEASE message is not received during the first predetermined time period, the sub—routine moves to block 33, which determines if a CONNECT_REQ message is received during a second predetermined time period also of 10 milliseconds, after the first predetermined time period has timed out. If block 33 determines that a CONNECT_REQ message is received during the second predetermined time period, the sub-routine moves to block 34, which activates the port 15 for receiving and transmitting data between the CAP|-to- Synchronous serial bridge device 1 and the encryption device 3. When the port 15 is fully activated, the sub-routine moves to block 35, which instructs the microprocessor 7 to raise a DTR signal and to relay the DTR signal to the encryption device 3 to indicate to the encryption device 3 that communication is being established between the cryptographic application 23 and the encryption device 3, and that the CAPl-to-Synchronous serial bridge device 1 is operable to interface with the encryption device 3. The sub-routine then moves to block 36, which will be described below. if block 33 determines that a CONNECT_REQ message is not received during the second predetermined time period, the sub-routine moves to block 37, which determines if a LlSTEN_REQ message is received during a third predetermined time period also of 10 milliseconds, which is timed after the second predetermined time period has timed out. If block 37 determines that a LlSTEN_REQ message is received during the third predetermined time period, the sub-routine moves to block 38, which prepares the port 15 for receiving and transmitting data between the CAPI- to-Synchronous serial bridge device 1 and the cryptographic application 23. When the port 15 is prepared for communicating data, the sub-routine moves to block 36, which will be described below. if block 37 determines that a LlSTEN_REQ message is not received during the third predetermined time period, the sub-routine moves to block 31, which has already been described.

Turning now to block 36, block 36 determines if the encryption device 3 is operable to interface with the CAP|—to—Synchronous serial bridge device 1 during a fourth predetermined time period of 200,000 milliseconds in response to the CONNECT_REQ message, or during an infinite time period in response to the LlSTEN_REQ message. If block 36 determines that the encryption device 3 is not operable to interface with the CAPI-to-Synchronous serial bridge device 1, the sub- routine moves to block 39. Block 39 deactivates the port 15 to its original state, and when the port 15 has been deactivated, the sub-routine moves to block 31, which has already been described. it block 36 determines that the encryption device 3 is operable to interface the CAPl—to-Synchronous serial bridge device 1 with the encryption device 3, the sub-routine moves to block 40, which affirms to the CAPl—to- Synchronous serial bridge device 1 that the interface communication link has been established between the cryptographic application 23 and the encryption device 3.

The sub-routine then moves to block 41, which determines if a CAPl_RELEASE message is received during a fifth predetermined time period of 10 milliseconds.

Timing of the fifth predetermined time period commences in response to block 40 affirming the establishment of the interface communication link between the cryptographic application 23 and the encryption device 3. if block 41 determines that a CAPl_RELEASE message is received during the fifth predetermined time period, the sub-routine moves to block 32, which has already been described. it block 41 determines that a CAPl_RELEASE message is not received during the fifth predetermined time period, the sub-routine moves to block 42, which checks if a DlSCONNECT__REQ message is received during a sixth predetermined time period of 10 milliseconds, which is timed after the fifth predetermined time period has timed out. if block 42 determines that a DlSCONNECT_REQ message is received during the sixth predetermined time period, the sub-routine moves to block 31, which has already been described. lf block 42 determines that a D|SCONNECT_REQ message is not received during the sixth predetermined time period, the sub-routine moves to block 43. Block 43 checks if the encryption device 3 is operable to interface with the CAPl—to—Synchronous serial bridge device 1 during a seventh predetermined time period of 10 seconds, which is timed after the sixth predetermined time period is timed out. if block 43 determines that the encryption device 3 is not operable to interface with the CAPI-to-Synchronous serial bridge device 1 during the seventh predetermined time period, the sub-routine moves to block 31, which has already been described.

If block 43 determines that the encryption device 3 is operable to interface with the CAPl—to—Synchronous serial bridge device 1 during the seventh predetermined time period, the sub-routine moves to block 44. Block 44 checks if a DATA_B3_REQ message is received during an eighth predetermined time period of 10 milliseconds, which is timed after the seventh predetermined time period has timed out. if block 44 determines that a DATA_B3_REQ message is received, the sub-routine moves to block 45, which instructs the microprocessor 7 to convert the DATA_B3_REQ message to a synchronous command for initiating the transmission of requested data by the cryptographic application 23 from the encryption device 3 to the cryptographic application 23. The sub-routine then moves to block 46, which instructs the microprocessor to check if any data is available from the encryption device 3. If block 46 determines that data is available from the encryption device 3, the sub-routine moves to block 47, which controls the microprocessor 7 to retrieve the data from the encryption device 3 and to relay the retrieved data to the cryptographic application 23 via the CAPl interface layer 10 of the laptop computer 2.

If, on the other hand, block 44 determines that a DATA_B3_REQ message is not received during the eighth predetermined time period, the sub—routine moves directly to block 46, which has already been described.

In use the PCMCIA card 6 is inserted into the PCMCIA slot (not shown) of the laptop computer 2. The laptop computer 2 is powered up, the BIOS of the laptop computer 2 scans its PCMCIA bus for hardware. Once the CAPI-to-Synchronous serial bridge device 1 is detected, the operating system of the laptop computer 2 requests that the drivers associated with the PCMCIA card 2 are installed on the laptop computer 2, the CD 9 is inserted into a CD ROM disk drive (not shown) of the laptop computer2.

When the drivers are installed from the CD 9 on the laptop computer 2, the PCMCIA card 6 appears to the operating system of the laptop computer 2 as a CAPI service provider. The encryption device 3 is coupled to the port 15 of the CAPI-to- Synchronous serial bridge device 1 by the connector 16 of the data bus 18.

When the cryptographic application 23 wishes to interface with the encryption device 2, the cryptographic application 23 calls the CAPI-to-Synchronous serial bridge device 1 by sending the CAPl_REG|STER message to the CAPI-to-Synchronous serial bridge device 1 via the CAPI interface layer 10 of the laptop computer 2 to initiate the creation of an interface communication link between the cryptographic application 23 and the encryption device 3. The microprocessor 7 allocates memory (not shown) in the laptop computer 2 for dealing with requests from the cryptographic application 23 once it receives the CAPl_REGlSTER message from the cryptographic application 23. The microprocessor 7 monitors during the first predetermined time period the incoming data to the CAPl-to—Synchronous serial bridge device 1 for a CAPl_RELEASE message. If a CAP|_RELEASE message is received, the microprocessor 7 releases the memory which it allocated for the cryptographic application 23, and terminates operations and awaits the next CAPl~REGlSTER message from the cryptographic application 23 or one of the other CAPI applications 20. However, if the microprocessor 7 doesn’t receive a CAPl_RELEASE message during the first predetermined time period, the microprocessor 7 subsequently monitors for the CONNECT_REQ message during the second predetermined time period. If the microprocessor 7 receives the CONNECT_REQ message during the second predetermined time period, the port 15 is activated for transmitting and receiving data between the CAPI-Synchronous serial bridge device 1 and the encryption device 3. When the port 15 is activated the microprocessor 7 generates a DTR signal and relays the DTR signal to the encryption device 3 for indicating that it is ready for the encryption device 3 to interface with it.

The microprocessor 7 subsequently determines during the third predetermined time period if the encryption device 3 is operable to interface with the CAPl-to- Synchronous serial bridge device 1. If the encryption device 3 is inoperable to interface with the CAP|—to—Synchronous serial bridge device 1 during the third predetermined time period, the port 15 is deactivated and the microprocessor 7 monitors for a CAP|_RELEASE message from the cryptographic application 23. In the event that the encryption device 3 is operable to interface with the CAP|—to- Synchronous serial bridge device 1 during the third predetermined time period, the microprocessor 7 determines during the fourth predetermined time period ifa CAPl_RELEASE message is received. If a CAPl_RELEASE message is received during the fourth predetermined time period, the microprocessor 7 releases the memory (not shown) on the laptop computer 2 which had been allocated for the cryptographic application 23, and terminates operations until a further CAPl_REGlSTER message from either the cryptographic application 23 or some other CAPI application 20.

If a CAP|_RELEASE message is not received during the fourth predetermined time period, the microprocessor 7 determines during the fifth predetermined time period if a DlSCONNECT_REQ message is received. In the event that a DlSCONNECT_REQ message is received during the fifth predetermined time period, the microprocessor 7 monitors for a CAPl_RELEASE message from the cryptographic application 23.

However, if a DlSCONNECT_REQ message is not received during the fifth predetermined time period, the microprocessor 7 determines during the sixth predetermined time period if the encryption device 3 is operable to interface with the R) U1 CAPI-to-Synchronous serial bridge device 1. In the event that the encryption device 3 is not operable to interface with the CAP|—to-Synchronous serial bridge device 1 during the sixth predetermined time period, the microprocessor 7 monitors fora CAPl_RELEASE message from the cryptographic application 23. If the encryption device 3 is operable to interface with the CAP|—to-Synchronous serial bridge device 1 during the sixth predetermined time period, the microprocessor 7 determines during the seventh predetermined time period if a DATA_B3_REQ message is received. in the event that the DATA_B3_REQ message is received during the seventh predetermined time period, the microprocessor 7 converts the DATA_B3_REQ message to a synchronous command for initiating the process for the transmission of data requested by the cryptographic application 23 from the encryption device 3 to the CAP|—to-Synchronous serial bridge device 1. The microprocessor 7 subsequently determines during the eighth predetermined time period if any data is available from the encryption device 3. If data is available from the encryption device 3, the microprocessor 7 retrieves the data from the encryption device 3 and relays the data to the cryptographic application 23.

While the CAPI-to-Synchronous serial bridge device 1 has been described as creating a communication link between the cryptographic application 23 and the encryption device 3 via the CAPI interface layer 10, it will be readily apparent to those skilled in the art that the CAP|—to-Synchronous serial bridge device 1 could be used for creating a communication link between the encryption device 3 and applications which are compatible with other telecommunications protocols such as the Telephony Application Programming Interface (TAPI) as illustrated in Fig. 2 provided that a TAPI interface layer is provided on the laptop computer 2 which is communicable with the CAPI application interface layer 10 for translating TAPI messages to CAPI messages and vice versa.

While the CAPI-to-Synchronous serial bridge device has been described as comprising a PCMCIA card, it is envisaged that the device may comprise a PCI card or any suitable hardware device operable to communicate with a CAPI compatible device and a synchronous compatible device.

While the CAP|—to-Synchronous serial bridge device has been described as being directly linked to the laptop computer, it is envisaged that the device may be provided as a portable independent device remotely linked to the CAPI compatible device.

While the CAPI-to-Synchronous serial bridge device has been described as comprising a port for interfacing with the synchronous serial compatible device, it is envisaged that any suitable interfacing means may be provided for interfacing with the synchronous serial compatible device.

While the CAP|—to-Synchronous serial bridge device has been described as performing operations within predetermined time periods of specific times, it will be appreciated that the predetermined time periods may be of any other suitable times.

While the operation of the CAPI-to-Synchronous serial bridge device has been described for enabling communication between a CAPI cryptographic application 23 and the encryption device 3, it will be readily apparent to those skilled in the art that the CAP|—to-Synchronous serial bridge device may be used for enabling communication between any CAPI application and the device 3. Needless to say, the commands used by the other CAPI applications will correspond with the commands used by the CAPI cryptographic application 23.

Claims (51)

Claims

1. A CAPI-to-Synchronous serial bridge device for interfacing a CAPI compatible first device and a synchronous serial compatible second device, the CAPI-to-Synchronous serial bridge device comprising a first receiving means for receiving a CAPI message from the first device, an executing means for converting the received CAPI message to a synchronous command, a first relaying means for relaying the synchronous command to the second device, a second receiving means for receiving data from the second device in response to the synchronous command, a second relaying means for relaying the data received from the second device to the first device, and a control means for controlling the operation of the CAPI-to- Synchronous serial bridge device, wherein a storing means is provided for storing predetermined operating instructions as CAPI software functions cross-referenced with corresponding synchronous commands, and the executing means is responsive to a received CAPI message for reading the corresponding synchronous command from the storing means for converting the received CAPI message to a synchronous command.

2. A CAPI-to-Synchronous serial bridge device as claimed in Claim 1 in which the predetermined operating instructions instruct the first device to provide a framework for facilitating the communication of data between the second device and the first device.

3. A CAPI-to-Synchronous serial bridge device as claimed in Claim 1 or 2 in which the storing means is accessible to the first device for reading instructions stored thereon.

4. A CAPI-to-Synchronous serial bridge device as claimed in any preceding claim in which the storing means is provided by an electronic storing means.

5. A CAPI-to-Synchronous serial bridge device as claimed in Claim 4 in which the storing means is provided by at least one compact disk.

6. A CAPI-to-Synchronous serial bridge device as claimed in any preceding claim in which the control means is operable to access resources located on the first device.

7. A CAPI-to-Synchronous serial bridge device as claimed in any preceding claim in which the control means is operable to access memory located on the first device.

8. A CAPl—to-Synchronous serial bridge device as claimed in any preceding claim in which a CAPI compatible interface means is provided for interfacing with the first device and a synchronous serial interface means is provided for interfacing with the second device.

9. A CAPI-to-Synchronous serial bridge device as claimed in Claim 8 in which the CAPI compatible interface means is directly linked to the first device.

10. A CAPI-to-Synchronous serial bridge device as claimed in Claim 8 or 9 in which the CAPI compatible interface means is operable to receive CAPI messages from at least one CAPI application which is co—operable with the first device for communicating data.

11. A CAPI-to-Synchronous serial bridge device as claimed in any of Claims 8 to 10 in which a monitoring means is provided for monitoring incoming data to the CAPl—to-Synchronous serial bridge device from the first device for identifying if a CAPI message is received.

12. A CAPI-to-Synchronous serial bridge device as claimed in Claim 11 in which the control means is responsive to the monitoring means detecting a first request message from the first device for initiating communication between the first device and the CAPI-to-Synchronous serial bridge device.

13. A CAPI-to-Synchronous serial bridge device as claimed in Claim 12 in which the control means is responsive to the monitoring means detecting the first request message from the first device for allocating memory for storing further CAPI messages received from the first device.

14. A CAPI-to-Synchronous serial bridge device as claimed in Claim 13 in which the control means is adapted for allocating the memory for storing further CAPI messages in the first device.

15. A CAPI-to-Synchronous serial bridge device as claimed in Claim 13 or 14 in which the control means is responsive to the monitoring means detecting a release message from the first device for releasing the allocated memory, and releasing communication established between the first device and the CAPI-to-Synchronous serial bridge device.

16. A CAPI-to-Synchronous serial bridge device as claimed in Claim 15 in which the control means is responsive to the monitoring means detecting the release message being received within a first predetermined time period from receipt of the first message for releasing the allocated memory and releasing communication established between the first device and the CAPI-to-Synchronous serial bridge device.

17. A CAPI-to-Synchronous serial bridge device as claimed in Claim 15 or 16 in which the control means is responsive to the monitoring means detecting a connect message received from the first device for establishing communication between the first device and the second device.

18. A CAPI-to-Synchronous serial bridge device as claimed in Claim 17 in which the control means is responsive to the monitoring means detecting the connect message being received from the first device within a second predetermined time period.

19. A CAPI-to-Synchronous serial bridge device as claimed in Claim 18 in which the second predetermined time period commences at the end of the first time period.

20. A CAPI-to-Synchronous serial bridge device as claimed in any of Claims to 19 in which the control means is responsive to the monitoring means detecting the listen from the first device for preparing the synchronous serial interface means for receiving and transmitting data between the CAPI-to-Synchronous serial device and the second device.

21. A CAPI-to-Synchronous serial bridge device as claimed in Claim 20 in which the control means is responsive to the monitoring means detecting the listen message being received within a third predetermined time period for preparing the synchronous serial interface means for receiving and transmitting data between the CAPI-to-Synchronous serial device and the second device.

22. A CAPI-to-Synchronous serial bridge device as claimed in Claim 21 in which the third predetermined time period commences at the end of the second predetermined time period.

23. A CAPl-to-Synchronous serial bridge device as claimed in any of Claims 17 to 22 in which the control means is responsive to the monitoring means detecting the connect message from the first device for activating the synchronous serial interface means for receiving and transmitting data between the CAPI-to-Synchronous serial bridge device and the second device.

24. A CAPI-to-Synchronous serial bridge device as claimed in any of Claims 17 to 23 in which the control means is responsive to the monitoring means detecting the connect message from the first device for setting an indicating means for indicating to the second device that the CAPI-to-Synchronous serial bridge device is operable to interface with the second device.

25. A CAPI-to-Synchronous serial bridge device as claimed in any of Claims 17 to 24 in which the control means comprises a first establishing means for establishing if the second device is operable to interface with the CAPI-to- Synchronous serial bridge device.

26. A CAPI-to-Synchronous serial bridge device as claimed in Claim 25 in which 24 the first establishing means is responsive to the monitoring means detecting the connect message for determining if the second device is operable to interface with the CAPI-to-Synchronous serial bridge device.

27. A CAPI-to-Synchronous serial bridge device as claimed in Claim 26 in which the first establishing means is responsive to the monitoring means detecting the connect message for determining if the second device is operable within a fourth predetermined time period for interfacing with the CAPI-to-Synchronous serial bridge device.

28. A CAPI-to-Synchronous serial bridge device as claimed in Claim 29 in which the fourth predetermined time period commences at the end of the third predetermined time period.

29. A CAPI-to-Synchronous serial bridge device as claimed in Claim 27 or 28 in which the control means is responsive to the monitoring means detecting the release message for releasing the allocated memory and releasing communication established between the first device and the CAPI-to-Synchronous serial bridge device if the second device is not operable to interface with the CAPI-to- Synchronous serial bridge device during the fourth predetermined time period.

30. A CAPI-to-Synchronous serial bridge device as claimed in any of Claims 27 to 29 in which the control means is responsive to the monitoring means detecting the release message from the first device during a fifth predetermined time period for releasing the allocated memory and the communication established between the first device and the CAPl-to-Synchronous serial bridge device.

31. A CAPI-to-Synchronous serial bridge device as claimed in Claim 30 in which the fifth predetermined time period commences at the end of the fourth predetermined time period.

32. A CAPI-to-Synchronous serial bridge device as claimed in any of Claims 27 to 31 in which the control means is responsive to the monitoring means detecting a 25 disconnect message for operating the monitoring means to monitor for the release message.

33. A CAPI-to-Synchronous serial bridge device as claimed in Claim 32 in which the control means is responsive to the monitoring means detecting the disconnect message within a sixth predetermined time period for operating the monitoring means to monitor for the release message.

34. A CAPI-to-Synchronous serial bridge device as claimed in Claim 33 in which the sixth predetermined time period commences at the end of the fifth predetermined time period.

35. A CAPI-to-Synchronous serial bridge device as claimed in Claim 33 or 34 in which the control means is responsive to the second device not being operable within a seventh predetermined time period after the sixth predetermined time period for operating the monitoring means to monitor for the release message.

36. A CAPI-to-Synchronous serial bridge device as claimed in Claim 35 in which the control means is responsive to the monitoring means detecting a data request message from the first device for converting the data request message to a synchronous command for initiating data transmission from the second device to the first device.

37. A CAPI-to-Synchronous serial bridge device as claimed in any of Claims 36 in which the control means is responsive to the monitoring means detecting the data request message from the first device within an eighth predetermined time period for converting the data request message to a synchronous command for initiating data transmission between the second device and the first device.

38. A CAPI-to-Synchronous serial bridge device as claimed in Claim 37 in which the eighth predetermined time period commences at the end of the seventh predetermined time period.

39. A CAPI-to-Synchronous serial bridge device as claimed in Claim 38 in which the control means comprises a second establishing means for establishing if data is available from the second device.

40. A CAPI-to-Synchronous serial bridge device as claimed in Claim 39 in which the second establishing means is responsive to the data request message for determining if data is available from the second device.

41. A CAPI-to-Synchronous serial bridge device as claimed in Claim 40 in which the second establishing means is responsive to the data request message being received within a ninth predetermined time period for determining if data is available from the second device.

42. A CAPI-to-Synchronous serial bridge device as claimed in Claim 41 in which the ninth predetermined time period commences at the end of the eighth predetermined time period.

43. A CAPI-to-Synchronous serial bridge device as claimed in any of Claims 39 to 42 in which the control means is responsive to the second establishing means for operating the second receiving means for retrieving data from the second device.

44. A CAPI-to-Synchronous serial bridge device as claimed in any of Claims 39 to 43 in which the control means is responsive to the second receiving means retrieving data from the second device for relaying the retrieved data to the first device for communicating to the at least one CAPl application.

45. A CAPI-to-Synchronous serial bridge device as claimed in any of Claims 39 to 44 in which the control means comprises a central processing unit, and the central processing unit is programmed to act as the monitoring means, the first establishing means, the second establishing means, the executing means, the first receiving means, the second receiving means, the first relaying means, and the second relaying means.

46. A CAPI-to-Synchronous serial bridge device as claimed in any preceding claim in which the CAPI-to-synchronous serial bridge device is provided in the form of a Personal Computer Memory Card International Association (PCMCIA) card.

47. A CAPI-to-Synchronous serial bridge device as claimed in any preceding claim in which a Peripheral Component interconnect (PCI) card is provided.

48. A CAPI-to-Synchronous serial bridge device substantially as described herein with reference to and as illustrated in the accompanying drawings.

49. A method for communicating between a CAPI compatible first device and a synchronous serial compatible second device, the method comprising the steps of: providing a CAPI-to-Synchronous serial bridge device for interfacing the CAPI compatible first device and the synchronous serial compatible second device, providing a first receiving means in the CAPI-to-Synchronous serial bridge device for receiving a CAPI message from the first device, providing an executing means in the CAPI-to-Synchronous serial bridge device for converting the received CAPI message to a synchronous command, providing a first relaying means in the CAPI-to-Synchronous serial bridge device for relaying the synchronous command to the second device, providing a second receiving means in the CAPI-to-Synchronous serial bridge device for receiving data from the second device in response to the synchronous command, and providing a second relaying means in the CAPI-to-Synchronous serial bridge device for relaying the data received from the second device to the first device, wherein the method further comprises: providing a storing means for storing predetermined operating instructions as CAPI software instructions cross-referenced with corresponding synchronous commands, and providing the executing means to be responsive to a received CAPI message for reading the corresponding synchronous command from the storing means for converting the CAPI message to a synchronous command. 28

50. A method as claimed in Claim 49 in which the method further comprises the steps of operating the first receiving means for receiving a CAPI message from the first device, operating the executing means for converting the received CAPI message to a synchronous command, operating the first relaying means for relaying the synchronous command to the second device, operating the second receiving means for receiving data from the second device in response to the synchronous command, and operating the second relaying means for relaying the data received from the second device to the first device.

51. A method for interfacing a CAPI compatible first device and a synchronous serial compatible second device, the method being substantially as described herein with reference to and as illustrated in the accompanying drawings.