IE20080066A1

IE20080066A1 - On-chip testing

Info

Publication number: IE20080066A1
Application number: IE20080066A
Authority: IE
Inventors: Ciaran Macnamee; Michael Higgins; Brendan Mullane
Original assignee: Univ Limerick
Priority date: 2007-01-30
Filing date: 2008-01-30
Publication date: 2008-09-17
Also published as: WO2008093312A1

Abstract

A system-on-chip (SoC) comprises a processor (10), a system bus (11), and embedded cores (4), and a dedicated test controller (3) connected to the system bus (11) by a system bus interface (12). The test controller (3) reuses the system bus (11) to route structural test vectors to the cores to implement Test Access Mechanisms (TAMs). The test controller (3) treats external automatic test equipment as a memory and autonomously performs on-chip testing while retrieving data from the automatic test equipment. The test controller (3) interfaces with the cores (4) via wrappers (6), each of which has an instruction register for controlling the test controller access. The system bus master is the general purpose processor (10). The test controller (3) and the core wrappers (4) allow concurrent testing and the test controller (3) controls a scan-chain testing technique using scan chains in the cores (4) to isolate semiconductor faults through a test wrapper.

Description

The IEEE 1500 standard [1] for embedded core test wrappers provides for access to all types of embedded digital cores regardless of their function or their implementation. Some of the elements of the well-documented and used IEEE 1149.1 standard have been re-used in this standard. IEEE 1500 wrappers are advantageous for not only the ease for test access but also to provide isolation for each core when the chip is in test mode so that the test outputs from one core will not damage the inputs of another core.

A prior technique to transport test vectors to and from embedded cores is through the use of a user-defined ‘Test Bus’. Adding a Test Bus to an SoC generates several overheads such as increased interconnection complexity and additional silicon area used. A dedicated test access mechanism (TAM), which is only used to deliver test vectors for testing the on-chip cores adds to the overall cost of the chip because it requires extra routing or wiring resources. To reduce costs these test access mechanisms or buses have usually been quite narrow.

Literature has discussed re-use of the system bus as a means to transport test vectors to and from the embedded cores An approach to such system bus reuse is described in [2] in which an Advanced Microcontroller Bus Architecture (AMBA) was reused for functional testing through the use of a Test Interface Controller (TIC) acting as a bus master. Reference [3] describes a test controller, which requires a dedicated on-chip test interface (Test Access Mechanism, TAM) to route the test vectors to each of the IEEE 1500 wrapped cores in the system.

Conventional ATE lacks the ability to adapt to varying chip packages and chip structures. Heretofore, on-chip test controllers have been treated by the ATE as a target rather than an initiator for test. Reference [3] details a dedicated test processor -2that requires an on-chip general purpose processor to carry out the concurrent testing of IEEE 1500 wrapped cores. Reference [3] describes use of a dedicated test access bus or mechanism to deliver test vectors.

Regarding scan chain debug architecture, in scan design testing the scan cells must be tested and verified before the rest of the core can be structurally and functionally tested. Current scan design does not allow for the debug and diagnosis of scan cell errors. Reference [4] describes a process and implementation-specific technique for modifying the structure of a scan flip-flop cell to allow detection of shorts in the scan chain.

References: [1] IEEE, IEEE Standard Testability Method for Embedded Core-based Integrated Circuits, in IEEE Std 1500-2005, 2005, pp. 0_l-117. [2] P. Harrod, Testing reusable IP-a case study, presented at Test Conference, 1999. Proceedings. International, 1999. [3] M. Tuna, M. Benabdenbi, and A. Greiner, T-Proc: An Embedded IEEE1500Wrapped Cores Tester, presented at Research in Microelectronics and Electronics 2006, Ph. D., 2006. [4] M. Sachdev, Testing defects in scan chains, Design & Test of Computers, IEEE, vol. 12, pp. 45-51, 1995.

The invention is directed towards providing an improved mechanism for on-chip testing.

SUMMARY OF THE INVENTION According to the invention, there is provided a system-on-chip comprising a processor, a system bus, and embedded cores, and test means for delivering test vectors to the cores, wherein the test means comprises a dedicated test controller -3connected to the system bus by a system bus interface, and the test controller comprises means for reusing the system bus to route structural test vectors to the cores to implement Test Access Mechanisms (TAMs).

In one embodiment, the test controller comprises means for treating external automatic test equipment as a memory and for autonomously performing on-chip testing while retrieving data from the automatic test equipment.

In one embodiment, the test controller comprises means for interfacing with the cores via wrappers, each of which has an instruction register for controlling the test controller access.

In one embodiment, the system comprises a system bus master wrapped by a wrapper which allows the test controller to take over control of the system bus.

In one embodiment, the system bus master is the processor.

In one embodiment, the test controller and the core wrappers comprise means for allowing concurrent testing.

In one embodiment, the test controller comprises means for controlling a scan-chain testing technique using scan chains in the cores (4) to isolate semiconductor faults through a test wrapper.

In one embodiment, at least some of the wrappers comprise multiplexers to separate core internal scan chains into shorter segments, allowing for fault isolation and diagnosis.

In one embodiment, die scan-chain technique implements Yield Learning.

In one embodiment, the test controller performs concurrent testing of wrapped cores.

In one embodiment, the test controller is programmable. -4In one embodiment, the test controller has a parameterisable design that is scalable according to tests to be carried out.

In one embodiment, the test controller comprises a section of memory available for download of information required for test scheduling, said information including descriptions of each core.

In one embodiment, the information includes number of primary inputs, primary outputs, test inputs, test outputs, number of scan chains, length of scan chains and the number of test patterns.

In one embodiment, the test controller comprises means for decoding different classes of instructions, including a class of instructions which configures and controls the test wrappers and a class concerned with other on-chip test functions such as boundary scan chains.

In one embodiment, the test controller has associated with each instruction a decode state machine that carries out operations as specified by the instruction.

In one embodiment, the test controller comprises means for communicating with a plurality of cores simultaneously.

In one embodiment, the test controller and wrappers implement a technique to deliver test vectors to cores using combined serial/parallel access to the wrappers.

In one embodiment, the test means further comprises dedicated TAM lines linked to the cores.

In one embodiment, the system further comprises an interface state machine for communication with an off-chip test manager combined with a parallel port for test instructions and test vectors. |£0 80 0 Ο -5In one embodiment, the parallel port comprises multiplexers on primary input and primary output pins.

In one embodiment, the test controller routes test data from the test manager via dedicated test pins or through multiplexing the test pins with normal functional VO pins.

In one embodiment, the test controller comprises a pattern generation State Machine and a series of sequence detector state machines that allow the automated verification of SoC sequential logic.

In one embodiment, the test controller is a wrapped core and can be fully tested while the system-on-chip is in functional mode.

DETAILED DESCRIPTION OF THE INVENTION Brief Description of the Drawings The invention will be more clearly understood from the following description of some embodiments thereof, given by way of example only with reference to the accompanying drawings in which: Fig. 1 is a block diagram showing an SoC architecture of the invention; Fig 2 is a diagram showing the architecture and functionality of a test controller of the SOC; Figs. 3 and 4 are diagrams showing the SOC architecture in greater detail; Fig. 5 is a block diagram showing a wrapper architecture of a core of the SOC; Fig. 6 is a diagram showing a reversible scan chain configuration; Fig 7 is a diagram showing system bus re-use at the test controller; and JEO 80 Ο Ο -6Fig. 8 is a diagram showing system bus re-use at a core wrapper.

Description of the Embodiments Referring to Figs. 1 to 5 a system-on-chip 1 is shown. It comprises an interface state machine 2, a dedicated test controller 3, and cores 4 including a general processor core 10. The test controller 3 and the cores 4 have wrappers 6 and are interconnected by a system bus 11 .having a system bus interface 12 between the test controller 3 and the processor 10.

An external ATE is treated as a large chunk of memory that stores test vectors and the expected test responses. The on-chip test controller 3 takes charge of the sequencing and operation of the test procedures, without need for control inputs from either the ATE or the processor 10. The test controller 3 interfaces with the cores 4 via the wrappers 6, each of which has an instruction register for controlling the test controller 3 access. Also, even though each wrapper has eight pins and there are, say, ten wrappers, the chip 1 does not require 10 x 5 external pins because logic in the test controller 3 performs the necessary multiplexing and signal routing.

The invention uses the existing on-chip system bus 11 structures to implement some or all of the TAM routing and wiring resources needed to interface to the cores 4 to be tested. The ability to use the existing bus 11 of an embedded microprocessor-based design to form part of the test TAM overcomes the bus routing overheads that might stand in the way of widespread deployment of the IEEE 1500 standard techniques. The technique whereby the system bus 11 can be used for delivering test vectors is enabled by wrapping the system bus master itself with a test wrapper. The general purpose processor is the system bus master, but in other embodiments there may be more than one bus master. Not only does this allow the bus master to be tested, it also allows the test controller 3 to take over the system bus and use it to deliver test vectors. -7The invention reduces cost of test by reducing the extra chip resources required to achieve wide TAMs, which in turn allow multiple test vectors to be applied in parallel.

The term ‘test vectors’ in this specification means structural test vectors, as opposed to functional test vectors. Functional Test Vectors are sets of test patterns based on the normal usage of a device or core that attempt to check if a device or core works as it should. The technique suffers from two limitations: firstly, the level of fault coverage is impossible to quantify and tends to be unacceptably low, because not all possible input conditions on every logic gate in the core can be applied; and secondly, the time required to apply enough functional test vectors tends to be unacceptably high.

Structural test vectors are specific test patterns based on circuit structural information and a set of fault models. Structural testing saves time and improves test efficiency and allows the fault detection capabilities of the test vectors to be quantified in a measure called Fault Coverage. Specific types of faults can be targeted for testing using a smaller number of efficient test vectors. Almost all modem semiconductor testing uses structural testing for these reasons.

By allowing the use of wider TAMs at lower cost, this invention also allows for reduced test times. A wide TAM may allow test vectors to be applied to more than one core 4 at the same clock cycle, or alternatively may allow the test vectors for a single core 4 to be applied in a shorter overall time. The invention therefore allows concurrent testing of more than one core at a time at lower overall cost and this is an advantage for test engineers.

The test controller 3 allows some of the complex test control mechanisms to be relocated on-chip. A reversible and configurable scan-chain technique allows defects in the silicon during manufacturing to be isolated. Also, it allows for a much more flexible test solution and reduced ATE programming complexity. In addition, some of the functionality of the test controller 3 is similar to the functionality of other on-chip components, such as those used for on-chip software debugging support, Flash programming, or boundary-scan test support. The effects of combining these types of ΙΕΟ 80 Ο 6S -8functionality are to reduce the overall cost of each type of function since considerable amounts of logic could be reused.

The reversible and configurable scan-chain arrangement supports Yield Learning or Improvement techniques, which will be increasingly necessary as transistor sizes continue to shrink. This is because the reversible scan-chains allow the location of silicon defects to be pinpointed precisely. Process problems leading to localised defects can be more quickly resolved if the locations of the defects could be found.

The design technology combines the features of structured core test access and standardised bus architecture to facilitate optimal test scheduling and sequencing test vector delivery that minimises associated test cost and silicon overheads. The hardware architecture consists of a programmable on-chip test controller combined with optimised Test Access Mechanism (TAMs) that interfaces to the internally embedded IC cores. The test controller 3 carries out a test schedule based on a predefined resource-partitioning scheme that provides an optimal solution for performing integrated test and debug analysis.

Compliance with the IEEE1500 standard requires the addition of logic to the embedded cores within the SoC. A wrapper as shown in Fig. 5 is built around each designated core 4 to provide standardised Design For Test (DFT) access to support a core-based test strategy. The wrapper logic is optimised for each core according to the user-driven requirements. The wrapper supports the mandatory serial test access needs via the Wrapper Serial Port (WSP), however test access via the serial port severely increases the overall test application time and cost. The Wrapper Parallel Port (WPP) reuses the physical interconnections of the system bus as a TAM to facilitate a higher bandwidth test access and test vector delivery system. Access to the cores to deliver test vectors is via the WPP and the physical interconnections of the system bus 11 provides the bandwidth needed for a more efficient core test strategy, both in terms of a reduced test time and lower routing complexity required for a TAM. -9The test controller 3 manages and schedules test/debug access to the cores 4. This test controller 3 is a programmable core, which reacts to user commands from the external Automatic Test Equipment (ATE) interface but does not require instructions from the ATE to perform the testing. It has access to each embedded core 4 DFT features via the WSP and WPP interfaces for carrying out SoC core tests.

Also as shown in Figs. 5 and 6, the wrappers also contain a feature directed at scan chain diagnostics that is useful for silicon yield analysis. The wrapper architecture uses additional multiplexers (muxes) to separate the core internal scan chains into shorter segments allowing for faster fault isolation and diagnosis. The wrapper design overcomes the shortcomings of the IEEE 1500 standard to accommodate scan debug solutions by facilitating a flexible scan chain reordering scheme to enable in-field diagnostic capability and identification of structural errors in a more timely and efficient manner than current approaches. Additional scan chain muxes and control lines are shown in Fig. 6. The system further builds upon the ability to engineer a reversible scan chain order and to insert patterns that lead to quick detection of the scan chain blockages. The core internal scan chains can be configured independently for programmable length and adaptable to each clock domain. This architecture facilitates a timely arrangement for locating structural errors and developing targeted tests that assist in silicon yield analysis and Design for Manufacture (DfM) yieldlearning techniques.

The following describes the SOC 1 in more detail. a) TAP Interface State Machine 2 This is the point on the chip where the test features are accessed. This includes a userdefined parallel port for data transport. The parallel port for test data is realised through the use of multiplexers on the primary input and primary output pins 5. The additional multiplexers are used in such a way with the boundary scan cells that they do not impact on the normal functional operation of the SoC. If required, the parallel port of the TAP can be implemented using dedicated test pins rather than multiplexing -10with the normal functional inputs and outputs. The TAP is also compatible with the IEEE Pl687 standard which allows for communication between chips, boards, and systems. b) Embedded Intelligent Test Controller 3 The embedded intelligent test controller 3 treats the ATE as a large chunk of memory that stores the test vectors and the expected test responses. Intelligence is built into this test controller 3 to allow it to take control of the scheduling and the operation of tests in the SoC. The test controller is wrapped with a wrapper so that it can be tested by the ATE. On board the test controller 3 a section of memory is available to download core information required for test scheduling. This information is derived from the *.soc description of the SoC. The information contained in the *.soc file includes descriptions of each core such as the number of primary inputs, primary outputs, test inputs, test outputs, number of scan chains, length of scan chains and the number of test patterns. The test controller 3 decodes two different classes of instructions; one class of instructions configures and controls the test wrappers and the other class is concerned with other on-chip test functions such as boundary scan chains. Associated with each instruction decode is a state machine that carries out the operations as specified by the instruction. The test controller also provides a pattern generation FSM (finite state machine) and series of sequence detector FSMs which when used in conjunction with the reversible scan chains embedded in each digital core provide a powerful tool to aid debugging and diagnosing sequential logic.

As shown in Fig 2, the main section of the test controller 3 is based on a series of TAM section state machines to control and communicate with all the wrapped cores 4 within the SoC. The total TAM within the SoC is divided into TAM sections so that the total test time or total power consumed for all wrapped cores is kept to a minimum. The choice of wrapped cores that are attached to each TAM section is dependent on the results of the TAM allocation scheme carried out. The TAM section state machines are required so that the concurrent testing of wrapped cores can be carried out on different TAM sections. If a test controller were not used to control all -11wrapped cores within a SoC, then each wrapped core would have to be tested in series, increasing the total test time. Similarly, to allow for concurrent testing of wrapped cores without a test controller would require routing all the wrapper control signals to the primary I/O pins of the SoC, resulting in too many pins required for test purposes, i.e. if there are N wrapped cores within the SoC then there would be (N*6) + 2 pins required for the concurrent testing of IEEE 1500 wrapped cores without the test controller, the extra two pins are for the common WRCK and WRSTn signals.

The TAM section state machines within the test controller (cfr. Fig. 2) provide several functions such as: Providing each Wrapper Instruction Register (WIR) on that TAM section with the appropriate Wrapper Serial Control (WSC) signals to allow for wrapper instruction setup and test execution, The ability to individually select a wrapped core on a TAM section for test through core select lines, Route the test data from the off-chip test manager to the core(s) under test through parallel TAM (PTAM) lines.

The interface state machine 2 provides communication between the on-chip test controller 3 and the off-chip test manager. The state machine 2 includes a status and control register instead of the standard data register. The status and control register is used to query the status of the main section of the test controller 3. Depending on the instruction received by the state machine 2, it has the ability to activate the appropriate TAM section state machine(s) and wrapped core(s) required for testing purposes, select the test mode to be carried out, query when the TAM section state machine(s) have set up the appropriate wrapped core(s) for testing and also indicate when the test data is valid to be transmitted from the test manager to the TAM section state machine(s). The higher bandwidth test data ports (Parallel Test Data In (PTDI) and Parallel Test Data Out (PTDO)) bypass the state machine 2 and are routed directly to the main section of the test controller. The higher bandwidth test data ports are provided through either a series of dedicated I/O pins or by multiplexing with primary I/O pins. -12c) System Bus 11 Our approach re-uses the physical interconnections of the system bus 11 that is not normally used during test. In a best-case scenario each core 4 has access to the system bus, but this is not always possible. If a core 4 does not have direct access to the system bus 11 a system bus interface is provided for the core 4 to gain access to the system bus 11. The number of lines that are used to deliver test vectors to a core under test must equal the number of lines used to collect the test responses from the cores under test. If the number of physical interconnections reused from the system bus for test purposes do not equal the number of interconnections reused for the collection of test vectors, there are two routes that can be followed here: i) The appropriate number of lines can be removed from the input TAM, or ii) ii) More preferably, dedicated test lines can be added to the overall TAM structure to balance the number of input and output TAM lines. Using the parallel port of the TAP described in (a) above the parallel TAM can be loaded in parallel resulting in no de-serialisation of data.

Fig. 7 shows interfacing of the test controller with the system bus. Logic is added, both at the test controller and also in the 1500 wrapper of each core within the SoC, to enable the reuse of the system bus. The test controller requires a system bus interface to gain access to the system bus. To deal with any bus contention issues on the system bus, a series of multiplexers are placed within the system bus interface, therefore only the general purpose processor (GPP) 10, or the test controller 3, is exclusively driving the system bus lines. Placing the system bus interface close to both the test controller 3 and the GPP 10 reduces excessive interconnection between the GPP and test controller. An example of a system bus interface is shown in Fig. 7.

At the 1500 core wrapper level, additional logic is added to the wrapper logic to allow reuse of the system bus 11 as a TAM. An example of this logic is shown in Fig. 8.

Access to the system bus for test purposes is through multiplexers: Ml, M2, M5 and M6; which are controlled by the decode logic contained in the WIR. The WIR -13determines if the WPI and WPO ports are required for a test mode and the muxes are controlled accordingly.

Table 1 shows the instruction decoding for the wrapper mux logic-supporting Serial and Hybrid instruction formats for the wrapper architecture, as seen in Fig. 8.

Instruction Ml M2 M3 M4 M5 M6 M7 M8 WS_BYPASS X X X X 1 1 0 1 WS_SAFE X X X X 1 1 0 1 WS_INTEST_SCAN 0 0 1 0 1 1 1 1 WS_INTEST__RING X X X X 1 1 1 1 WS_EXTEST X X 0 0 1 1 1 1 WH_INTEST_SCAN 1 1 X 1 0 0 1 1 Table 1: Instruction Decoding for Wrapper Mux Logic The instruction of interest for system bus reuse in Table 1 is WH_INTEST_SCAN where both the WPP and WSP are used for applying test vectors. Examining Fig. 8, when the second inputs of Ml and M2 are enabled, the system bus lines PWDATA[0] and PWDATA[1] are used to shift scan values into scan chain 1 and 2; also WSI is used to shift scan values into scan chain 0. The scan outputs from scan chain 1 and 2 are also routed back onto the system bus lines, PRDATA[0] and PRDATAfl], by enabling the appropriate inputs of M5 and M6. The number of muxes used to gain access onto the system bus for test vectors must increase as the size of both WPI and WPO increase. This is a parameterisable feature of the wrapper design and can be changed at compile time. d) IEEE 1500 Compatible Test Core Wrappers (Fig. 6 and Fig 81 The invention provides not only the mandatory sections of the IEEE 1500 standard but also a majority of the listed optional applications focusing on the wrapper parallel port. In addition to the parallel operation other functionality is added to the wrapper that is not included in the IEEE 1500 specification such as the ability to facilitate reversible and reconfigurable scan chains. Ability to control reversible and reconfigurable scan chains adds advantages for yield and debug analysis. To add a -14reversible scan chain to a design, instead of replacing all the flip flops with a normal scan cell at the netlist level, a modified scan cell is inserted whereby an extra multiplexer is placed on the input so that the direction of the scan chain can be reversed to flush out an error in the chain. To test the functionality of the sequential logic in a core a 0011 pattern is traversed across all the elements of the scan chain showing that each sequential element can make the transition from 0-0, 0-1,1-1, and 1 - 0. If a stuck at fault occurs somewhere in the scan chain all outputs at the scan out pin of the chain are corrupted, therefore leaving the tester unable to diagnose where the fault occurred. Using the reversible scan structure shown in Fig. 6 the exact location of the stuck at fault in the chain can be found. To find the fault, the scan chain is loaded in the normal manner, then the direction of the scan chain is reversed giving the exact location in the scan chain where the error occurred by counting how many of the bits that are output are as expected. For example, if the scan chain contains 100 elements and the 55th cell is faulty, to detect this fault the scan chain is loaded as normal, and then the direction is changed. The first 54 bits out of the SO (scan out) pin will be as expected, but from the 55th bit onwards data will be corrupted due to the fault. Therefore the fault location can be pinpointed to the 55th cell in the scan chain. Using the conventional scan chain structure, i.e. unidirectional, it would not be possible to locate this fault as all of the bits shifted out of the scan chain at the SO pin would be corrupted. Using this scan chain structure would alleviate many problems that might only be found later in the testing phase through further sequential and combinational testing.

The diagram in Fig 8 illustrates the core wrapper design attached to an internal core 4. Three important points are noted below: The system bus connections are reused as physical wiring into the Core parallel TAM interface in to and out of the core. This parallel TAM is indicated by WPI, WPO and is the reused system bus connections 50.

This feature of sharing a common system bus facilitates lower SoC routing overhead, lowers complexity and also lower silicon area requirements. -15Another useful feature is utilising the serial TAM (WSI/WSO) and parallel TAM (WPI/WPO) interfaces in parallel for Hybrid SCAN test mode operation. This mode enables the full core bandwidth in terms of TAM access. A Hybrid Test command to the wrapper instruction register enables the core wrapper logic for combined serial/parallel TAM access. This minimises the need for a larger parallel TAM and efficiently uses the current wrapper TAM resources on-chip enabling further routing and area overhead savings.

In summary, the problems solved with this invention include: - Reduced cost of test by the combination of a system bus with the dedicated TAMs used for testing IEEE 1500 wrapped re-usable cores.

- Reduced test times arising from the ability to use wider TAMs at reduced cost.

- Reduced test complexity in the external test instrumentation as a result of the use of an on-chip test control module.

Enhanced ability to locate silicon defects quickly through use of the reversible and configurable scan-chain technique.

- Improved data bandwidth and reduced wiring and silicon overheads.

By combining a system bus with a dedicated TAM, a wider overall Test Access Mechanism can be realised at a reduced resource cost. Also, the invention involves using the system bus 11 as a means for applying structural test vectors. The system bus and dedicated TAM lines are combined into a single effective TAM, which can communicate with one or more cores at any time.

Use of the on-chip CPU for system testing is not excluded by the invention, but the preferred embodiment uses a dedicated intelligent controller that communicates with on-chip cores using the combined effective TAM. By carefully examining how -16functionality of the test controller overlaps with other non-mission mode functional blocks, such as on-chip software debug systems, Flash programming modules or boundary-scan TAP control modules, and combining these functions into a single module, the overall cost of testing, debugging and programming can be reduced.

The invention makes optimal on-chip test and debug of the embedded cores 4 possible. Such an approach has advantages over other solutions as it leverages the existing use of standardised system bus architectures as a mechanism for interfacing to the embedded cores as compared to an architecture using a separate and dedicated Test Bus. The optimized system bus with the Test Access Mechanism leads to a reduction of wiring overheads and minimises the silicon overheads associated with integrated DFT technology.

Yield improvement is vitally important in the semiconductor industry where margins are extremely tight. The reversible and configurable scan-chain technique of this invention allows yield improvement to be achieved with a small extra silicon cost, consisting of some extra multiplexers and counters. When used in conjunction with an on-chip test controller, the reversible and configurable scan-chain allows defects in silicon to be quickly localised for analysis by process engineers, thereby allowing process problems to be resolved early.

The invention is not limited to the embodiments described but may be varied in construction and detail.

Claims

1. A system-on-chip (SoC) comprising a processor (10), a system bus (11), and embedded cores (4), and test means for delivering test vectors to the cores, wherein the test means comprises a dedicated test controller (3) connected to the system bus (11) by a system bus interface (12), and the test controller (3) comprises means for reusing the system bus (11) to route structural test vectors to the cores to implement Test Access Mechanisms (TAMs).

2. A system-on-chip as claimed in claim 1, wherein the test controller (3) comprises means for treating external automatic test equipment as a memory and for autonomously performing on-chip testing while retrieving data from the automatic test equipment.

3. A system-on-chip as claimed in claim 2, wherein the test controller (3) comprises means for interfacing with the cores (4) via wrappers (6), each of which has an instruction register for controlling the test controller access.

4. A system-on-chip as claimed in any preceding claim, comprising a system bus master wrapped by a wrapper which allows the test controller (3) to take over control of the system bus.

5. A system-on-chip as claimed in claim 4, wherein the system bus master is the processor (10).

6. A system-on-chip as claimed in any preceding claim, wherein the test controller (3) and the core wrappers (4) comprise means for allowing concurrent testing.

7. A system-on-chip as claimed in any preceding claim, wherein the test controller (3) comprises means for controlling a scan-chain testing technique using scan chains in the cores (4) to isolate semiconductor faults through a test wrapper. -1830 *

8. A system-on-chip as claimed in claim 7, wherein at least some of the wrappers comprise multiplexers to separate core internal scan chains into shorter segments, allowing for fault isolation and diagnosis.

9. A system-on-chip as claimed in claims 7 or 8, wherein the scan-chain technique implements Yield Learning.

10. A system-on-chip as claimed in any of claims 3 to 9, wherein the test 10 controller (3) performs concurrent testing of wrapped cores (4).

11. A system-on-chip as claimed in any preceding claim, wherein the test controller (3) is programmable. 15

12. A system-on-chip as claimed in claim 11 which the test controller (3) has a parameterisable design that is scalable according to tests to be carried out.

13. A system-on-chip as claimed in claim 12, wherein the test controller (3) comprises a section of memory available for download of information required 20 for test scheduling, said information including descriptions of each core.

14. A system-on-chip as claimed in claim 13, wherein the information includes number of primary inputs, primary outputs, test inputs, test outputs, number of scan chains, length of scan chains and the number of test patterns.

15. A system-on-chip as claimed in either of claims 13 or 14, wherein the test controller (3) comprises means for decoding different classes of instructions, including a class of instructions which configures and controls the test wrappers and a class concerned with other on-chip test functions such as boundary scan chains. IE Ο 8 θ ρ § g -1916. A system-on-chip as claimed in claim 15, wherein the test controller (3) has associated with each instruction a decode state machine that carries out operations as specified by the instruction. 5 17. A system-on-chip as claimed in any preceding claim, wherein the test controller (3) comprises means for communicating with a plurality of cores (4) simultaneously.

16. 18. A system-on-chip as claimed in any of claims 3 to 17, wherein the test 10 controller (3)and wrappers (4) implement a technique to deliver test vectors to cores (4)using combined serial/parallel access to the wrappers (6).

17. 19. A system-on-chip as claimed in any preceding claim, wherein the test means further comprises dedicated TAM lines linked to the cores.

18. 20. A system-on-chip as claimed in any preceding claim, further comprising an interface state machine (2) for communication with an off-chip test manager combined with a parallel port (5) for test instructions and test vectors. 20

19. 21. A system-on-chip as claimed in claim 20, wherein the parallel port comprises multiplexers on primary input and primary output pins.

20. 22. A system-on-chip as claimed in claims 20 or 21, wherein the test controller (3) routes test data from the test manager via dedicated test pins or through 25 multiplexing the test pins with normal functional I/O pins.

21. 23. A system-on-chip as claimed in any preceding claim, wherein the test controller (3) comprises a pattern generation State Machine and a series of sequence detector state machines that allow the automated verification of SoC 30 sequential logic. 110 80 086 -2024. A system-on-chip as claimed in any preceding claim whereby the test controller (3) is a wrapped core and can be fully tested while the system-on chip is in functional mode.