HK1227222B - Single-layer circuit board, multilayer circuit board and methods for manufacturing the same - Google Patents

Description

Single-layer circuit board, multi-layer circuit board and manufacturing method thereof

Technical Field

The present invention relates to single-layer circuit boards, multilayer circuit boards, and methods for manufacturing the same. In particular, the present invention relates to single-layer circuit boards using an insulating material with holes as a substrate, a conductor layer formed in the hole walls, and a circuit pattern formed on the substrate surface; and multilayer circuit boards formed by laminating multiple single-layer circuit boards and interconnecting the single-layer circuit boards through metallized vias, as well as methods for manufacturing the same.

Background Art

In the circuit board industry, metallized vias are widely used to connect circuit patterns or electronic components on the surface and back of the circuit board, or to electrically connect the conductor layers between the layers of the double-layer or multi-layer circuit boards to facilitate the design of multi-layer circuit patterns.

In the prior art, the method for manufacturing a single-layer circuit board with metallized vias mainly includes the following steps: manufacturing copper foil by calendering or electrolysis; bonding the copper foil to a substrate by high-temperature lamination to form a copper-clad laminate; drilling holes in the copper-clad laminate and removing dirt; forming a conductive seed layer on the hole wall by electroless copper deposition (PTH) or black hole, black shadow and other processes; forming a metal conductor layer on the hole wall by electroplating to obtain a copper-clad laminate with metallized holes; covering the copper-clad laminate with a photoresist film, exposing and developing it with a photolithography machine, and then etching to remove the copper layer outside the circuit area on the copper-clad laminate, thereby producing a circuit board with a circuit pattern.

In addition, the manufacturing method of multi-layer circuit boards with metallized vias mainly includes the lamination method, which includes the following steps: manufacturing a single-layer circuit board; arranging and laminating the boards in the order of copper foil, PP (prepreg), single-layer circuit board, PP, single-layer circuit board, ..., PP, copper foil; drilling through holes in the laminated multi-layer board and blind holes in the surface copper foil, and metallizing the holes; applying pattern plating or full-board electroplating to the top and bottom copper foils to produce a circuit pattern. Among them, hole metallization is also usually achieved by forming a conductive seed layer on the hole wall through chemical copper deposition or black hole, black shadow and other processes, and then forming a conductor thickening layer through electroplating.

In the process of forming single-layer or multi-layer circuit boards with metallized holes using the above-mentioned method, if a hole with a diameter less than 100μm is to be drilled in the substrate, laser drilling technology is currently the only option. In this case, the copper foil in the area to be drilled must be thinned beforehand, followed by laser drilling. Copper deposition and electroplating are then performed after drilling. However, during the etching and thinning process, any deviation in the etching position will also cause deviation in the drilling position on the substrate. Moreover, when metallizing the microholes, the bonding between the electroplated copper layer and the hole wall is poor, and the copper layer easily detaches from the hole wall. Furthermore, the minimum hole diameter of microholes produced in copper-clad laminates using existing technology is 20-50μm. When the hole diameter is less than 20μm, the hole thickness-to-diameter ratio is too high, resulting in uneven copper layer formation on the hole wall during copper deposition and electroplating. Uneven current density distribution within the microhole area can cause the copper deposition rate on the microhole surface to be greater than that on the hole wall and bottom. Therefore, holes or cracks are easily formed during the deposition process, and the copper thickness on the hole surface is greater than the copper thickness on the hole wall.

Furthermore, the aforementioned circuit board production method requires the production of finished copper-clad laminates, followed by drilling and metallization of these finished copper-clad laminates. Finally, the circuit pattern is created through processes such as lamination, exposure and development, and etching. This results in a lengthy and costly process. Furthermore, the multiple metal etching steps involved in the entire process generate large amounts of wastewater containing metal ions, significantly harming the environment.

Summary of the Invention

The present invention is made in view of the above problems, and its purpose is to provide a single-layer circuit board and a multi-layer circuit board with metallized holes and their manufacturing methods to simplify the manufacturing process of the circuit board and improve the conductive performance of the metallized holes therein.

The first technical solution of the present invention is a method for manufacturing a single-layer circuit board, comprising the following steps: drilling holes in a substrate, including blind holes and/or through holes (S1); forming a photoresist layer with a circuit negative image on the surface of the substrate (S2); forming a conductive seed layer on the surface of the substrate and the hole walls (S3); and removing the photoresist layer to form a circuit pattern on the surface of the substrate (S4), wherein step S3 includes injecting a conductive material below the surface of the substrate and below the hole walls by ion implantation to form an ion implantation layer as at least a part of the conductive seed layer.

According to this method, metallized holes can be formed on a substrate and a circuit pattern can be formed on the surface of the substrate through a simple process flow. When forming the circuit pattern, a photoresist film is first coated on the substrate surface before forming the conductive seed layer, and a photoresist layer with a circuit negative image is further formed. A stripping solution is then used to dissolve the photoresist layer, causing the conductive seed layer and/or conductor thickening layer in the non-circuit area to fall off along with the photoresist layer. Therefore, it is not necessary to obtain the circuit pattern through etching as in the prior art, or at least the use of etching solution can be reduced, thereby reducing or eliminating the environmental damage caused by etching wastewater containing metal ions.

The second technical solution of the present invention is that, in the first solution, step S3 further includes depositing a conductive material onto the ion implantation layer by plasma deposition to form a plasma deposition layer, and the plasma deposition layer and the ion implantation layer constitute a conductive seed crystal layer.

The third technical solution of the present invention is that, in the first solution, after step S3 and before step S4, the method further comprises: forming a conductor thickening layer on the conductive seed crystal layer.

A fourth technical solution of the present invention is that, in the first solution, removing the photoresist layer includes using a stripping solution to dissolve the photoresist layer.

The fifth technical solution of the present invention is a method for manufacturing a single-layer circuit board, comprising the following steps: drilling holes in a substrate, which include blind holes and/or through holes (S1); forming a conductive seed layer (S2) on the surface of the substrate and the walls of the holes; and forming a circuit pattern (S3) on the surface of the substrate, wherein step S2 includes injecting a conductive material below the surface of the substrate and below the walls of the holes by ion implantation to form an ion implantation layer as at least a part of the conductive seed layer.

The sixth technical solution of the present invention is that, in the fifth solution, step S2 further includes depositing a conductive material onto the ion implantation layer by plasma deposition to form a plasma deposition layer, and the plasma deposition layer and the ion implantation layer constitute a conductive seed crystal layer.

The seventh technical solution of the present invention is that in the fifth solution, step S3 includes: first forming a conductor thickening layer on the conductive seed crystal layer, and then performing graphic electroplating or full-board electroplating on the conductor thickening layer located above the surface of the substrate to obtain a circuit pattern.

An eighth technical solution of the present invention is that, in the fifth solution, step S3 includes: performing pattern electroplating or full-board electroplating directly on the conductive seed crystal layer formed on the surface of the substrate, thereby obtaining a circuit pattern.

The ninth technical solution of the present invention is that in any one of the first to eighth solutions, the substrate is a rigid plate or a flexible plate, the rigid plate includes one or more of an organic polymer rigid plate, a ceramic plate, and a glass plate, wherein the organic polymer rigid plate includes one or more of LCP, PTFE, CTFE, FEP, PPE, synthetic rubber plate, and glass fiber cloth/ceramic filler reinforced plate, and the flexible plate is an organic polymer film, which includes one or more of PI, PTO, PC, PSU, PES, PPS, PS, PE, PP, PEI, PTFE, PEEK, PA, PET, PEN, LCP or PPA.

The tenth technical solution of the present invention is that in the first or fifth solution, during ion implantation, the ions of the conductive material obtain an energy of 1-1000 keV, are implanted to a depth of 1-500 nm below the surface of the substrate and below the pore wall of the pore, and form a stable doping structure with the substrate.

The eleventh technical solution of the present invention is that in the second or sixth solution, during plasma deposition, ions of the conductive material obtain energy of 1-1000 eV to form a plasma deposition layer with a thickness of 1-10000 nm.

The twelfth technical solution of the present invention is that in any one of the first to eighth solutions, the conductive material constituting the conductive seed crystal layer includes one or more of Ti, Cr, Ni, Cu, Ag, Au, V, Zr, Mo, Nb and alloys thereof.

The thirteenth technical solution of the present invention is that in the third or seventh solution, a conductor thickening layer with a thickness of 0.01-1000 μm is formed by one or more of Al, Mn, Fe, Ti, Cr, Co, Ni, Cu, Ag, Au, V, Zr, Mo, Nb and alloys thereof through electroplating, chemical plating, vacuum evaporation, and sputtering.

According to the method for manufacturing a single-layer circuit board of the present invention, the metallization of the substrate surface and the metallization of the holes can be carried out simultaneously. Therefore, a single-layer circuit board with metallized vias can be directly produced on the substrate through a one-step molding process, eliminating the need to pre-coat the substrate with a thicker metal foil and then etch and thin the metal foil before drilling holes in the substrate, as in the prior art. Furthermore, it is necessary to further form a conductive layer on the hole wall through chemical copper deposition or black hole, black shadow, and other processes to obtain the metallized vias. Compared with the prior art, the process flow of this method is significantly shortened, and the use of etching solution can be reduced, which is beneficial to environmental protection. In addition, by adjusting various process parameters, these methods can easily produce extremely thin circuit pattern layers. The resulting single-layer circuit board can be advantageously used in mid-to-high-end precision electronic products based on HDI (high-density interconnect substrate) and COF (chip on flexibility) technologies. In addition, during ion implantation, ions of the conductive material are forcibly injected into the interior of the substrate at a very high speed, forming a stable doping structure between the substrate and the substrate, which is equivalent to forming a large number of foundation piles on the substrate surface and below the hole wall. Due to the presence of the base pile, and the subsequent conductive layer (plasma deposition layer or conductor thickening layer) is connected to the base pile, the bonding force between the conductive layer of the substrate finally obtained and the substrate is high, much higher than the bonding force between the metal layer and the conductor obtained by magnetron sputtering in the prior art. Moreover, the size of the conductive material ions used for ion implantation is usually nanometer level, and the distribution is relatively uniform during ion implantation, and the difference in the angle of incidence to the substrate surface and the hole wall is not much. Therefore, it is possible to ensure that the conductor thickening layer or plasma deposition layer formed above the ion implantation layer has good uniformity and density, and is not prone to pinhole phenomenon. During microporous metallization, it is easy to form a conductive seed layer with a uniform and dense surface on the hole wall, and the ratio of the conductor layer thickness of the hole wall to the conductor layer thickness of the substrate surface can reach 1:1. Therefore, when electroplating, problems such as uneven hole wall conductor layer and holes or cracks will not occur, and the conductivity of the metallized hole can be effectively improved.

The fourteenth technical solution of the present invention is a single-layer circuit board, which includes a substrate and a circuit pattern layer formed on a partial surface of the substrate. The substrate is provided with holes, which include blind holes and/or through holes. The hole walls are formed with a conductive seed crystal layer. The circuit pattern layer includes a conductive seed crystal layer formed on a partial surface of the substrate, wherein the conductive seed crystal layer includes an ion implantation layer injected below the partial surface of the substrate and below the hole walls.

The presence of the ion-implanted layer in the hole wall creates a strong bond between the hole wall and the conductive seed layer, preventing the conductive layer on the hole wall from easily falling off or being scratched during subsequent processing or application. This improves the conductivity of the hole and facilitates the production of a single-layer circuit board with excellent conductivity.

The fifteenth technical solution of the present invention is that in the fourteenth solution, the ion implantation layer is located below a portion of the surface of the substrate and below the pore wall at a depth of 1-500 nm, and forms a stable doping structure with the substrate.

The sixteenth technical solution of the present invention is that in the fourteenth solution, the conductive seed crystal layer further includes a plasma deposition layer attached to the ion implantation layer, and the plasma deposition layer has a thickness of 1-10000 nm.

The seventeenth technical solution of the present invention is that in the fourteenth solution, the conductive seed crystal layer is composed of a conductive material, and the conductive material includes one or more of Ti, Cr, Ni, Cu, Ag, Au, V, Zr, Mo, Nb and alloys thereof.

The eighteenth technical solution of the present invention is that in the fourteenth solution, the circuit pattern layer also includes a conductor thickening layer located above the conductive seed crystal layer, the conductor thickening layer has a thickness of 0.01-1000μm, and is composed of one or more of Al, Mn, Fe, Ti, Cr, Co, Ni, Cu, Ag, Au, V, Zr, Mo, Nb and alloys thereof.

The nineteenth technical solution of the present invention is a method for manufacturing a multilayer circuit board, comprising: arranging and laminating the boards in the order of metal foil, intermediate laminating layer, single-layer circuit board, intermediate laminating layer, single-layer circuit board, ..., intermediate laminating layer, and metal foil (S1); drilling holes in the laminated multilayer board, which include through holes and/or blind holes (S2); forming a conductive seed layer on the hole wall of the hole (S3); and removing a portion of the metal foil to form a circuit pattern (S4), wherein step S3 comprises injecting a conductive material into the bottom of the hole wall of the hole by ion implantation to form an ion implantation layer as at least a part of the conductive seed layer.

During ion implantation, the ions of the conductive material are forcibly injected into the bottom of the hole wall at a very high speed, forming a stable doping structure between the conductive material and the substrate, which is equivalent to forming a large number of foundation piles under the hole wall. Due to the presence of the foundation piles, and the subsequent conductive layer (plasma deposition layer or conductor thickening layer) is connected to the foundation piles, the bonding force between the conductive layer of the substrate finally obtained and the substrate is high, much higher than the bonding force between the metal layer and the conductor obtained by magnetron sputtering in the prior art. Moreover, the size of the conductive material ions used for ion implantation is usually nanometer-level, and the distribution is relatively uniform during ion implantation, and the angle of incidence to the hole wall is not much different. Therefore, it can be ensured that the conductor thickening layer or plasma deposition layer formed above the ion implantation layer has good uniformity and density, and is not prone to pinhole phenomenon. During microporous metallization, it is easy to form a conductive seed layer with a uniform and dense surface on the hole wall, which can effectively improve the conductivity of the metallized hole.

The twentieth technical solution of the present invention is a method for manufacturing a multilayer circuit board, comprising: arranging and laminating boards in the order of surface laminating layer, single-layer circuit board, intermediate laminating layer, single-layer circuit board, intermediate laminating layer, single-layer circuit board, ..., surface laminating layer (S1); drilling holes in the laminated multilayer board, which include through holes and/or blind holes (S2); forming a conductive seed layer on the outer surface of the surface laminating layer and the hole walls of the holes (S3); and forming a circuit pattern on the outer surface of the surface laminating layer (S4), wherein step S3 comprises injecting a conductive material into below the outer surface of the surface laminating layer and below the hole walls of the holes by ion implantation to form an ion implantation layer as at least a part of the conductive seed layer.

According to this method, the metallization of the outer surface of the surface lamination layer and the metallization of the hole can be carried out simultaneously. Therefore, a multilayer circuit board with metallized vias and surface circuit patterns can be directly produced by one-time molding, without the need to cover the thicker metal foil in advance and then etch and thin the metal foil before drilling, as in the prior art, and it is necessary to form a conductive layer on the hole wall through chemical copper deposition or black holes, black shadows and other processes to obtain metallized vias. Compared with the prior art, the process flow of this method is significantly shortened, and the use of etching solution can be reduced, which is beneficial to environmental protection. In addition, by adjusting various process parameters, this method is easy to produce a surface circuit pattern layer with an extremely thin thickness, and the resulting multilayer circuit board can be advantageously used in high-end precision electronic products based on HDI (high-density interconnect substrate) and COF (flexible chip) technology.

The twenty-first technical solution of the present invention is that in the nineteenth or twentieth solution, during ion implantation, the ions of the conductive material obtain an energy of 1-1000 keV and are injected to a depth of 1-500 nm below the pore wall and/or below the outer surface of the surface bonding layer, and form a stable doping structure with the substrate.

The twenty-second technical solution of the present invention is that in the nineteenth or twentieth solution, step S3 also includes depositing a conductive material onto the ion implantation layer by plasma deposition to form a plasma deposition layer, and the plasma deposition layer and the ion implantation layer constitute a conductive seed layer.

The twenty-third technical solution of the present invention is that in the twenty-second solution, during plasma deposition, ions of the conductive material obtain energy of 1-1000 eV to form a plasma deposition layer with a thickness of 1-10000 nm.

The twenty-fourth technical solution of the present invention is that in the nineteenth or twentieth solution, the conductive material constituting the conductive seed crystal layer includes one or more of Ti, Cr, Ni, Cu, Ag, Au, V, Zr, Mo, Nb and alloys thereof.

The twenty-fifth technical solution of the present invention is that, in the nineteenth solution, step S3 further includes: forming a conductor thickening layer on the conductive seed crystal layer formed on the hole wall.

The twenty-sixth technical solution of the present invention is that in the nineteenth or twentieth solution, step S4 includes: first forming a conductor thickening layer on the conductive seed crystal layer, and then performing graphic electroplating or full-board electroplating on the conductor thickening layer located above the outer surface of the surface bonding layer to obtain a circuit pattern.

The twenty-seventh technical solution of the present invention is that in the twenty-fifth or twenty-sixth solution, a conductor thickening layer with a thickness of 0.01-1000 μm is formed by one or more of Al, Mn, Fe, Ti, Cr, Co, Ni, Cu, Ag, Au, V, Zr, Mo, Nb and alloys thereof through electroplating, chemical plating, vacuum evaporation, and sputtering.

The twenty-eighth technical solution of the present invention is that in the twentieth solution, step S4 includes: performing graphic electroplating or full-board electroplating directly on the conductive seed crystal layer formed on the outer surface of the surface bonding layer to obtain a circuit pattern.

The twenty-ninth technical solution of the present invention is that in the nineteenth or twentieth solution, at least one intermediate bonding layer is provided with a hole, and a conductive layer is formed on the hole wall of the hole.

The thirtieth technical solution of the present invention is that in the nineteenth or twentieth solution, at least one single-layer circuit board is provided with a hole, and a conductive layer is formed on the hole wall of the hole.

The thirty-first technical solution of the present invention is that in the nineteenth or twentieth solution, the intermediate bonding layer and/or the surface bonding layer include one or more of PP, PI, PTO, PC, PSU, PES, PPS, PS, PE, PEI, PTFE, PEEK, PA, PET, PEN, LCP, and PPA.

The thirty-second technical solution of the present invention is a multi-layer circuit board, which is composed of a metal foil, an intermediate bonding layer, a single-layer circuit board, an intermediate bonding layer, a single-layer circuit board,..., an intermediate bonding layer, and a metal foil in sequence. The multi-layer circuit board is provided with a hole, a conductive seed crystal layer is formed on the hole wall of the hole, and part of the metal foil is removed to form a circuit pattern layer, wherein the conductive seed crystal layer includes an ion implantation layer injected into the bottom wall of the hole.

The thirty-third technical solution of the present invention is a multi-layer circuit board, which is composed of a surface bonding layer, a single-layer circuit board, an intermediate bonding layer, a single-layer circuit board, ..., a surface bonding layer in sequence, the multi-layer circuit board is provided with a hole, a conductive seed crystal layer is formed on the hole wall of the hole, and a circuit pattern layer having a conductive seed crystal layer is formed on a portion of the outer surface of the surface bonding layer, wherein the conductive seed crystal layer includes an ion implantation layer injected under the hole wall of the hole and under a portion of the outer surface of the surface bonding layer.

The presence of the ion-implanted layer in the hole wall of such a multilayer circuit board creates a strong bond between the hole wall and the conductive seed layer, preventing the conductive layer in the hole wall from easily falling off or being scratched during subsequent processing or application. This improves the conductivity of the hole and facilitates the production of a multilayer circuit board with excellent conductivity.

The thirty-fourth technical solution of the present invention is that in the thirty-second or thirty-third solution, the ion implantation layer is located below the hole wall and/or below part of the outer surface of the surface bonding layer at a depth of 1-500 nm, and forms a stable doping structure with the substrate.

The thirty-fifth technical solution of the present invention is that in the thirty-second or thirty-third solution, the conductive seed crystal layer further includes a plasma deposition layer attached to the ion implantation layer, and the plasma deposition layer has a thickness of 1-10000 nm.

The thirty-sixth technical solution of the present invention is that in the thirty-second or thirty-third solution, the conductive seed crystal layer is composed of a conductive material, and the conductive material includes one or more of Ti, Cr, Ni, Cu, Ag, Au, V, Zr, Mo, Nb and alloys thereof.

The thirty-seventh technical solution of the present invention is that in the thirty-second or thirty-third solution, a conductor thickening layer with a thickness of 0.01-1000 μm is formed above the conductive seed crystal layer.

The thirty-eighth technical solution of the present invention is that in the thirty-second or thirty-third solution, the hole is a through hole passing through a multi-layer circuit board, a blind hole formed on the surface of a multi-layer circuit board, or a blind hole formed in a single-layer circuit board or an intermediate bonding layer.

The thirty-ninth technical solution of the present invention is that in the thirty-second or thirty-third solution, the intermediate bonding layer and/or the surface bonding layer includes one or more of PP, PI, PTO, PC, PSU, PES, PPS, PS, PE, PEI, PTFE, PEEK, PA, PET, PEN, LCP, and PPA.

BRIEF DESCRIPTION OF THE DRAWINGS

These and other features, aspects, and advantages of the present invention will be more readily understood by those skilled in the art after reading the following detailed description with reference to the accompanying drawings. For the sake of clarity, the drawings are not necessarily drawn to scale, and some parts may be exaggerated to show details. In all figures, the same reference numerals represent the same or similar parts, wherein:

1 is a flow chart showing a method for manufacturing a single-layer circuit board according to a first embodiment of the present invention;

FIG2 is a schematic cross-sectional view of a product corresponding to each step of the method shown in FIG1 ;

3 is a flow chart showing a method for manufacturing a single-layer circuit board according to a second embodiment of the present invention;

FIG4 is a schematic cross-sectional view showing a product corresponding to each step of the method shown in FIG3 ;

5 is a flowchart showing a method for manufacturing a single-layer circuit board according to a third embodiment of the present invention;

FIG6 is a schematic cross-sectional view of a product corresponding to each step of the method shown in FIG5 ;

7 is a flowchart showing a method of manufacturing a multilayer circuit board according to a fourth embodiment of the present invention;

FIG8 is a schematic cross-sectional view of a product corresponding to each step of the method shown in FIG7 ;

9 is a flowchart showing a method of manufacturing a multilayer circuit board according to a fifth embodiment of the present invention;

FIG10 is a schematic cross-sectional view of a product corresponding to each step of the method shown in FIG9 ;

11 is a flowchart showing a method for manufacturing a multilayer circuit board according to a sixth embodiment of the present invention;

FIG. 12 is a schematic cross-sectional view showing a product corresponding to each step of the method shown in FIG. 11 .

Reference Number:

10 Single-layer circuit board

11. Substrate

12 Surface of the substrate

13 Conductive seed layer

131 ion implantation layer

132 Plasma Deposition Layer

15 Conductor thickening layer

16 Circuit pattern layer

161 Circuit Area

162 Non-circuit area

17 through holes

18 blind holes

19 hole wall

20 multi-layer circuit boards

21 metal foil

22 Middle bonding layer

23 Surface bonding layer

24 Photoresist film.

DETAILED DESCRIPTION

The embodiments of the present invention are described in detail below with reference to the accompanying drawings. It should be understood by those skilled in the art that these descriptions merely list exemplary embodiments of the present invention and are not intended to limit the scope of protection of the present invention.

FIG1 is a flow chart illustrating a method for manufacturing a single-layer circuit board according to a first embodiment of the present invention, and FIG2 is a schematic cross-sectional view of a product corresponding to each step of the method shown in FIG1 . As shown in FIG1 , the method includes the following steps: drilling holes, including blind holes and/or through holes, into a substrate ( S1 ); forming a photoresist layer with a negative image of a circuit on the surface of the substrate ( S2 ); forming a conductive seed layer on the surface of the substrate and the walls of the holes ( S3 ); and removing the photoresist layer to form a circuit pattern on the surface of the substrate ( S4 ). Steps (a), (b), (c), and (d) in FIG2 correspond to steps S1, S2, S3, and S4, respectively. The steps of the method will be described in detail below with reference to both FIG1 and FIG2 .

In the manufacturing process of circuit boards, insulating materials are usually used as substrates, and metal materials are composited on one or both sides of the substrate and etched to produce circuit boards. As examples of insulating substrates, rigid substrates (also known as hard boards) can be used, such as one or more of organic polymer rigid boards, ceramic boards (such as silica boards), glass boards, etc., and organic polymer rigid boards can include one or more of LCP, PTFE, CTFE, FEP, PPE, synthetic rubber boards, and glass fiber cloth/ceramic filler reinforced boards, wherein the glass fiber cloth/ceramic filler reinforced boards are based on organic polymer materials such as epoxy resin, modified epoxy resin, PTFE, PPO, CE, BT, etc., and are reinforced with glass fiber cloth/ceramic fillers. In addition, the insulating substrate can also use flexible boards (also known as soft boards), such as organic polymer films, which include one or more of PI, PTO, PC, PSU, PES, PPS, PS, PE, PP, PEI, PTFE, PEEK, PA, PET, PEN, LCP or PPA.

First, it is necessary to drill holes on the substrate (step S1). Although only through holes 17 are shown in Figure 2 (a), blind holes can also be drilled on the surface 12 of the substrate 11. A through hole is a hole that penetrates the surface and back of the substrate, while a blind hole is a hole that penetrates deep into the substrate but does not penetrate the substrate. The shape of the hole can be a variety of shapes such as circular, rectangular, triangular, diamond, terraced, etc. Drilling can be carried out by mechanical drilling, punching, laser drilling, plasma etching and reactive ion etching, among which laser drilling can include infrared laser drilling, YAG laser drilling and ultraviolet laser drilling, which can form micropores with an aperture of 2-5μm on the substrate. In order to reduce the heat-affected zone and prevent the edges of the holes from being damaged by heat, ultraviolet laser drilling is preferably used. In the case of manufacturing flexible circuit boards in a roll-to-roll manner, a series of holes can be formed on the rolled flexible board substrate by a continuous drilling method. After the holes are formed on the substrate, the holes need to be cleaned to remove impurities such as drill cuttings.

Next, a photoresist layer with a negative image of the circuit is formed on the surface of the substrate (step S2). Specifically, as shown in Figure 2(b), a layer of photoresist film 24 is coated or adhered to the surface 12 of the drilled and cleaned substrate 11. The substrate coated with the photoresist film 24 is placed on a photolithography machine for exposure and development. The substrate surface is then cleaned and dried, resulting in a photoresist layer with a negative image of the circuit (i.e., an image that forms a complementary image to the circuit pattern to be ultimately formed on the substrate surface). At this point, the photoresist film 24 is present only in the non-circuit area 162 on the substrate surface and is absent from the complementary circuit area 161.

Then, a conductive seed layer is formed on the surface of the substrate and the wall of the hole (step S3). Since a photoresist film 24 is formed in the non-circuit area 162 on the surface of the substrate 12, a conductive seed layer 13 is also formed on the surface of the photoresist film 24 during this process. Importantly, step S3 includes injecting a conductive material below the surface 12 of the substrate 11 and below the hole wall 19 of the hole by ion implantation to form an ion implantation layer 131 as at least a portion of the conductive seed layer 13. It should be noted that the phrase "injected below the hole wall" herein actually refers to injecting below the surface of the substrate at the hole wall (i.e., the wall of the hole). For example, in FIG2(c), the ion implantation layer 131 is injected below the hole wall 19 of the hole 17, which actually means that the ion implantation layer 131 is located below the surface of the substrate at the hole wall 19 of the hole 17 (i.e., the wall of the hole).

The formation of the ion implantation layer can be achieved by the following method: using a conductive material as a target material, in an ion implantation device under a vacuum environment, the conductive material in the target material is ionized by an arc action to generate ions, and then the ions are accelerated under a high voltage electric field to obtain very high energy, for example, 1-1000keV. The high-energy conductive material ions then directly impact the surface of the substrate and the pore walls of the hole at a very high speed and are implanted to a certain depth below the substrate surface and the pore walls, for example, 1-500nm. A stable doping structure is formed between the implanted conductive material ions and the material constituting the substrate, just like the doping structure in a semiconductor. The outer surface of the doping structure (i.e., the ion implantation layer) is flush with the substrate surface or the pore walls, while its inner surface penetrates deep into the interior of the substrate. As specific examples, ions of the conductive material may obtain an energy of 50keV, 100keV, 200keV, 300keV, 400keV, 500keV, 600keV, 700keV, 800keV, 900keV during ion implantation and may be implanted within a depth range of 10nm, 20nm, 50nm, 100nm, 200nm, 300nm, 400nm below the substrate surface and the pore walls.

Various metals, alloys, conductive oxides, conductive carbides, conductive organics, etc. can be used as conductive materials for ion implantation, but are not limited thereto. Preferably, metals or alloys with strong molecular bonding to the substrate are used for ion implantation, including one or more of Ti, Cr, Ni, Cu, Ag, Au, V, Zr, Mo, Nb, and alloys thereof, such as NiCr, TiCr, VCr, CuCr, MoV, NiCrV, TiNiCrNb, etc. Moreover, the ion implantation layer can include one or more layers. Prior to ion implantation, the substrate with the holes can be subjected to pre-treatments such as decontamination, surface cleaning, sealing agent treatment, Hall source treatment under a vacuum environment, and surface deposition treatment.

During ion implantation, the ions of the conductive material are forcibly implanted into the interior of the substrate at a very high speed, forming a stable doping structure with the substrate, which is equivalent to forming a large number of foundation piles on the substrate surface and below the hole wall. Due to the existence of the foundation piles, and the subsequent metal layer (plasma deposition layer or conductor thickening layer) obtained is connected to the foundation piles, the peel strength between the substrate and the subsequent metal layer formed thereon can reach more than 0.5N/mm, for example, between 0.7-1.5N/mm, more specifically between 0.8-1.2N/mm. In comparison, in the case of conventional magnetron sputtering, the energy of the sputtered particles is only a few electron volts at most, so the particles will only be deposited on the substrate surface and the hole wall but will not enter the interior of the substrate. The bonding force between the resulting sputtered deposition layer and the substrate surface and the hole wall is not high, and is only about 0.5N/mm at most, which is significantly lower than the present invention. Moreover, the size of the conductive material ions used for ion implantation is usually nanometer-level, and is more evenly distributed during ion implantation, and the angle of incidence to the substrate surface and the hole wall is not much different. Therefore, it is possible to ensure that the subsequent conductor thickening layer or plasma deposited layer formed above the ion implantation layer has good uniformity and density, and is less likely to have pinholes. Moreover, during microporous metallization, it is easy to form a conductive seed layer with a uniform and dense surface on the hole wall, and the ratio of the conductor layer thickness on the hole wall to the conductor layer thickness on the substrate surface can reach 1:1. Therefore, during subsequent electroplating, problems such as uneven conductor layer on the hole wall, holes or cracks will not occur, and the conductivity of the metallized hole can be effectively improved.

In addition to ion implantation, step S3 may also include depositing a conductive material onto the ion implantation layer by plasma deposition to form a plasma deposited layer, which together with the ion implantation layer constitutes a conductive seed layer. As shown in FIG2(c), after step S3, an ion implantation layer 131 is formed below the hole wall 19 of the through hole 17, below the substrate surface 12 in the circuit area 161, and below the surface of the photoresist film 24 in the non-circuit area 162, and a plasma deposited layer 132 is formed on the ion implantation layer 131. Of course, step S3 may also not include plasma deposition. In this case, the plasma deposited layer 132 shown in FIG2(c) does not exist, and only the ion implantation layer 131 exists.

Plasma deposition can be performed in an ion implantation system using a similar method to the ion implantation described above, except that a lower voltage is applied, resulting in lower energy for the conductive material ions. Specifically, a conductive material is used as a target. In a vacuum environment, an arc is applied to ionize the conductive material in the target, generating ions. These ions are then accelerated in an electric field to a specific energy, for example, 1-1000 eV. The accelerated conductive material ions fly toward the substrate surface and pore walls and deposit onto the ion implantation layer formed below the substrate surface and pore walls, forming a plasma-deposited layer with a thickness of 1-10000 nm. As specific examples, the conductive material ions may obtain energies of 50 eV, 100 eV, 200 eV, 300 eV, 400 eV, 500 eV, 600 eV, 700 eV, 800 eV, or 900 eV during plasma deposition, and form a plasma-deposited layer having a thickness of 100 nm, 200 nm, 500 nm, 700 nm, 1 μm, 2 μm, 5 μm, 7 μm, or 10 μm. In the case of a thicker plasma-deposited layer, through-holes or blind vias drilled in the substrate may be completely filled. In other words, the entire hole is filled with the conductive material, and the macroscopic hole structure no longer exists.

In plasma deposition, the same or different conductive materials as those used for ion implantation can be used as targets. Furthermore, the conductive material can be selected based on the substrate, the composition, and thickness of the ion implantation layer, and other factors. Preferably, plasma deposition is performed using a metal or alloy that exhibits good bonding with the ion implantation layer. For example, one or more of Ti, Cr, Ni, Cu, Ag, Au, V, Zr, Mo, Nb, and alloys thereof, such as NiCr, TiCr, VCr, CuCr, MoV, NiCrV, and TiNiCrNb, can be used. Furthermore, the plasma-deposited layer can include one or more layers.

During plasma deposition, conductive material ions fly toward the substrate surface and pore walls at high speeds and deposit onto the ion-implanted layer formed below the substrate surface and pore walls. This creates a strong binding force with the conductive material in the ion-implanted layer, making it less likely to fall off the substrate surface and pore walls. Furthermore, the conductive material ions used for plasma deposition are typically nanometer-sized and relatively evenly distributed during plasma deposition. Furthermore, the angles of incidence on the substrate surface and pore walls vary slightly, ensuring that the resulting plasma-deposited layer, or the subsequent conductor thickening layer formed thereon, possesses good uniformity and density, making pinholes less likely to occur. Furthermore, whereas ion-implanted layers are typically thin and poorly conductive, plasma-deposited layers can enhance the conductivity of the conductive seed layer, thereby improving the performance of the resulting circuit board.

After the conductive seed layer is formed, the photoresist layer can be removed to form a circuit pattern on the surface of the substrate (step S4). As shown in Figure 2(d), the photoresist film 24 present in the non-circuit area 162 is removed, and the conductive seed layer 13 formed on the photoresist film 24 is also removed, leaving only the conductive seed layer 13 located in the circuit area 161 on the hole wall 19 and the substrate surface 12. In other words, on the surface 12 of the substrate, the conductive seed layer 13 is only present in the circuit area 161, thereby producing a double-sided single-layer circuit board 10 with a circuit pattern. In a preferred embodiment, a stripping liquid can be used to dissolve the photoresist layer. For example, the substrate with the photoresist layer and the conductive seed layer formed with the circuit negative image can be placed in an appropriate stripping liquid and stirred or shaken to accelerate the dissolution of the photoresist layer. After the photoresist layer is completely dissolved, it is thoroughly cleaned with a cleaning agent and then dried. The stripping liquid can be an organic solvent or alkaline solution that can dissolve the photoresist layer.

As shown in FIG2(d), the single-layer circuit board 10 produced by the above method includes a substrate 11 and a circuit pattern layer 16 formed on a portion of the substrate surface. A hole is formed in the substrate 11, and a conductive seed layer 13 is formed on the hole wall 19 of the hole. The circuit pattern layer 16 also includes a conductive seed layer 13 formed on a portion of the surface of the substrate 11. The conductive seed layer 13 includes an ion implantation layer 131 implanted below the surface 12 of the substrate and below the hole wall 19 of the hole, and a plasma deposited layer 132 attached to the ion implantation layer 131. Of course, when step S3 does not include plasma deposition, the conductive seed layer 13 consists solely of the ion implantation layer 131.

Alternatively, after step S3 and before step S4, the method shown in Figure 1 can also be included in forming a conductor thickening layer on the conductive seed layer to improve its electrical conductivity. Specifically, one or more of the methods such as electroplating, chemical plating, vacuum evaporation plating, sputtering, can be used, one or more of Al, Mn, Fe, Ti, Cr, Co, Ni, Cu, Ag, Au, V, Zr, Mo, Nb and the alloy therebetween, to form a conductor thickening layer with a thickness of 0.01-1000 μm (such as 0.5 μm, 1 μm, 5 μm, 10 μm, 50 μm, 100 μm, etc.). It is easy to understand that when base material is formed with a through hole or a blind hole, the through hole or the blind hole may be filled by the conductor thickening layer, that is, no longer have a pore structure macroscopically. Electroplating is the most common and most preferred, because electroplating speed is fast, cost is low, and the range of materials that can be electroplated is very wide, and can be used for various conductive materials such as Cu, Ni, Sn, Ag and their alloys. For some conductive materials, especially metals and alloys (such as Al, Cu, Ag and their alloys), the sputtering speed can reach 100nm/min, so sputtering can be used to quickly plate a conductor layer on the conductive seed layer. Since a uniform and dense conductive seed layer has been formed on the surface and pore walls of the substrate by ion implantation and/or plasma deposition, it is easy to form a uniform and dense conductor thickening layer on the conductive seed layer through the above methods.

When a conductor thickening layer is formed, it will accordingly cover the conductive seed layer and, after the photoresist layer is removed, ultimately exist on the conductive seed layer in the circuit area, serving as part of the circuit pattern on the circuit board's surface. In Figure 2, the conductive seed layer 13 is composed of an ion-implanted layer 131 and a plasma-deposited layer 132, so the conductor thickening layer is attached to the plasma-deposited layer. It is easy to understand that when the conductive seed layer only includes the ion-implanted layer, the conductor thickening layer is directly attached to the ion-implanted layer.

According to the above method, metallized holes can be formed in a substrate and a circuit pattern can be formed on the surface of the substrate through a simple process flow. When forming the circuit pattern, a photoresist film is first coated on the substrate surface before forming the conductive seed layer, and a photoresist layer with a circuit negative image is further formed. A stripping solution is then used to dissolve the photoresist layer, allowing the conductive seed layer and/or conductor thickening layer in the non-circuit area to be removed along with the photoresist layer. Therefore, the circuit pattern can be obtained without etching as in the prior art. At the same time, the use of etching solution can be reduced, thereby reducing or eliminating the environmental hazards of etching wastewater containing metal ions.

Figure 3 is a flow chart illustrating a method for manufacturing a single-layer circuit board according to a second embodiment of the present invention, and Figure 4 is a schematic cross-sectional view of a product corresponding to each step of the method shown in Figure 3 . As shown in Figure 3 , the method includes the following steps: drilling holes, including blind holes and/or through holes, into a substrate ( S1 ); forming a conductive seed layer on the surface of the substrate and the walls of the holes ( S2 ); forming a conductor thickening layer on the conductive seed layer ( S31 ); covering the surface of the substrate with a photoresist film and performing exposure and development ( S32 ); and etching and stripping the film to form a circuit pattern ( S33 ). Steps S31 to S33 are steps for forming the circuit pattern on the surface of the substrate. When electroplating is used to form the conductor thickening layer, these steps can be collectively referred to as "full-board electroplating." (a), (b), (c), (d), and (e) in Figure 4 correspond to steps S1, S2, S31, S32, and S33, respectively.

In the method of this embodiment, steps S1 and S2 correspond to steps S1 and S3 in the method shown in FIG1 , respectively, and can be performed using the various methods described above for FIG1 . In addition, step S31 can also be performed using the methods described above, that is, by electroplating, chemical plating, vacuum evaporation plating, sputtering, etc., using one or more of Al, Mn, Fe, Ti, Cr, Co, Ni, Cu, Ag, Au, V, Zr, Mo, Nb, and alloys thereof, to form a conductor thickening layer with a thickness of 0.01-1000 μm on the conductive seed crystal layer. Through steps S1, S2, and S31, a conductive seed crystal layer is formed on the surface of the substrate and the hole wall of the hole, and a conductor thickening layer is formed on the conductive seed crystal layer. In the example shown in FIG4( c ), the conductive seed layer 13 includes an ion implantation layer 131 formed below the surface 12 of the substrate 11 and below the pore walls 19, and a plasma deposited layer 132 attached to the ion implantation layer 131. The conductor thickening layer 15 is further attached to the plasma deposited layer 132, and the conductor thickening layer 15 fills the through hole 17 penetrating the substrate 11. It is easy to understand that when step S2 only includes ion implantation but does not include plasma deposition, the conductor thickening layer 15 is directly attached to the ion implantation layer 131.

After the conductor thickening layer is formed, a photoresist film is applied to the surface of the substrate and exposed and developed (step S32). Specifically, as shown in FIG4(d), a layer of photoresist film 24 is applied or adhered to the substrate surface 12 on which the conductor thickening layer 15 is formed. The substrate covered with the photoresist film 24 is placed on a photolithography machine for exposure and development. The substrate surface is then cleaned and dried to obtain a photoresist layer with a positive circuit image (i.e., an image identical to the circuit pattern to be ultimately formed on the substrate surface). At this point, the photoresist film 24 is present only in the circuit area 161 on the substrate surface and is absent from the complementary non-circuit area 162.

Then, a conventional etching method can be used to remove the conductive seed layer and the conductor thickening layer that are not covered by the photoresist film, and then the photoresist film is removed (step S33), so that the conductive seed layer and the conductor thickening layer are retained only in the circuit area on the surface of the substrate to form a surface circuit pattern. As shown in Figure 4 (e), the single-layer circuit board 10 obtained by the above method includes a substrate 11 and a circuit pattern layer 16 formed on a portion of the surface of the substrate. A hole is opened on the substrate 11, and a conductive seed layer 13 and a conductor thickening layer 15 are formed on the hole wall 19 of the hole. The circuit pattern layer 16 also includes a conductive seed layer 13 and a conductor thickening layer 15, wherein the conductive seed layer 13 includes an ion implantation layer 131 implanted below the surface 12 of the substrate and below the hole wall 19 of the hole, and a plasma deposition layer 132 attached to the ion implantation layer 131. Of course, if step S2 does not include plasma deposition, the conductive seed layer 13 is only composed of the ion implantation layer 131.

Figure 5 is a flow chart illustrating a method for manufacturing a single-layer circuit board according to a third embodiment of the present invention, while Figure 6 is a schematic cross-sectional view of a product corresponding to each step of the method shown in Figure 5 . As shown in Figure 5 , the method includes the following steps: drilling holes, including blind vias and/or through vias, into a substrate (S1); forming a conductive seed layer on the substrate surface and the walls of the holes (S2); covering the substrate surface with a photoresist film and exposing and developing the film (S31); performing electroplating (S32); and performing stripping and etching to form a circuit pattern (S33). Steps S31 to S33 are steps for forming a circuit pattern on the substrate surface and can be collectively referred to as "pattern plating." Compared to the method shown in Figure 3 , the method of this embodiment differs in that pattern plating is used rather than full-board plating to form the circuit pattern. Figures 6 (a), (b), (c), (d), and (e) correspond to steps S1, S2, S31, S32, and S33, respectively.

In the method of this embodiment, steps S1 and S2 correspond to steps S1 and S2 in the method shown in FIG3 , respectively, and can be performed using the various methods described above for FIG3 . After step S2, a conductive seed layer is formed on the surface of the substrate and the wall of the hole. As shown in FIG6( b), the conductive seed layer 13 includes an ion implantation layer 131 formed below the surface 12 of the substrate 11 and below the wall 19 of the hole, and a plasma deposition layer 132 attached to the ion implantation layer 131. It is easy to understand that when step S2 only includes ion implantation but does not include plasma deposition, the plasma deposition layer 132 does not exist. In addition, step S31 can also be performed in a manner similar to step S32 in the method shown in FIG3 , that is, a photoresist film is covered on the surface of the substrate on which the conductive seed layer is formed and exposed and developed. Specifically, as shown in FIG6(c), a photoresist film 24 is coated or adhered to the substrate surface 12 on which the conductive seed layer 13 is formed. The substrate coated with the photoresist film 24 is placed in a photolithography machine for exposure and development. The substrate surface is then cleaned and dried, resulting in a photoresist layer with a negative image of the circuit. At this point, the photoresist film 24 is present only in the non-circuit region 162 on the substrate surface, while the complementary circuit region 161 is not.

Next, electroplating is performed (step S32). Since the photoresist layer is insulating, during the electroplating process, the conductor thickening layer will not be formed above the photoresist layer, but will only be formed above the conductive seed layer that is not covered by the photoresist layer. At this time, there is a conductive seed layer composed of an ion implantation layer and a plasma deposition layer below the photoresist layer, but there is no conductor thickening layer above it. As shown in Figure 6 (d), through electroplating, a conductor thickening layer 15 is formed only on the conductive seed layer 13, and the conductor thickening layer 15 fills the through hole 17. Of course, if the aperture of the through hole 17 is large enough, the through hole 17 will not be filled by the conductor thickening layer 15.

Then, stripping and etching are performed to form a circuit pattern (step S33), thereby producing a single-layer circuit board. The single-layer circuit board 10 shown in FIG6(e) has the same structure as the single-layer circuit board 10 shown in FIG4(e).

Stripping, i.e., removing the photoresist layer with the negative image of the circuit, can be performed by the following steps: placing the insulating substrate formed with the conductive seed layer, the photoresist layer, and the conductor thickening layer in an appropriate stripping solution (e.g., an organic solvent or alkaline solution that can dissolve the photoresist layer), and stirring or shaking to accelerate the dissolution of the photoresist layer, followed by cleaning and drying. As a result, the conductive seed layer and the conductor thickening layer exist in the circuit area on the substrate surface, while only the conductive seed layer exists in the non-circuit area. Then, the entire surface of the metal substrate can be rapidly etched to remove the conductive seed layer in the non-circuit area, thereby obtaining the final circuit pattern on the substrate surface. At this time, the conductor thickening layer in the circuit area will also be etched away to a certain thickness equivalent to the conductive seed layer, but this will not affect its subsequent use. Alternatively, after the photoresist layer is completely dissolved, a protective layer (e.g., tin) can be applied over the conductor thickening layer in the circuit area, and then etching can be performed to remove the conductive seed layer in the non-circuit area, thereby obtaining the final circuit pattern. At this point, the thickened conductor layer in the circuit area will not be etched away, thereby maintaining the good surface properties of the thickened conductor layer. Alternatively, before placing the substrate in the stripping solution (i.e., before dissolving the photoresist layer), a protective layer (e.g., tin) can be applied over the thickened conductor layer in the circuit area. The photoresist layer can then be dissolved and the conductive seed layer in the non-circuit area can be etched away to obtain the final circuit pattern on the substrate surface. Of course, if a protective layer is used, it will also need to be removed before obtaining the final circuit pattern, for example, by removing the tin film.

According to the method for manufacturing a single-layer circuit board described above, the metallization of the substrate surface and the metallization of the holes can be carried out simultaneously. Therefore, a single-layer circuit board with metallized vias can be directly produced on the substrate by one-time molding, without the need to cover the substrate with a thicker metal foil in advance and then etch and thin the metal foil before drilling holes on the substrate as in the prior art, and it is necessary to further form a conductive layer on the hole wall by chemical copper deposition or black hole, black shadow and other processes to obtain metallized vias. Compared with the prior art, the process flow of the above method is significantly shortened, and the use of etching solution can be reduced, which is beneficial to environmental protection. In addition, by adjusting various process parameters, such a method can easily produce a circuit pattern layer with an extremely thin thickness (for example, less than 12 μm, such as 5 μm, 7 μm, 9 μm, etc.), and the resulting single-layer circuit board can be advantageously used in medium and high-end precision electronic products based on HDI (high-density interconnect substrate) and COF (flexible chip) technology.

Similarly, due to the presence of the ion-implanted layer in the hole wall, the single-layer circuit board produced by the aforementioned methods exhibits a very high bonding force between the hole wall and the conductive seed layer (e.g., reaching 0.5 N/mm or higher, such as between 0.7 and 1.5 N/mm, and more specifically between 0.8 and 1.2 N/mm). As a result, the conductive layer on the hole wall is not easily detached or scratched during subsequent processing or application. This helps improve the conductivity of the hole and facilitates the production of a single-layer circuit board with excellent conductivity.

It should be noted that although the method shown in Figure 3 adopts the full-board electroplating method to form the circuit pattern (i.e., successively forming a conductor thickening layer, covering a photoresist film and performing exposure and development, and etching and stripping the film), and the method shown in Figure 5 adopts the graphic electroplating method to form the circuit pattern (i.e., successively covering a photoresist film and performing exposure and development, electroplating, and stripping and etching), it is easy to understand that it is also possible to first form a conductor thickening layer on the conductive seed crystal layer and then perform full-board electroplating on this basis, or it is also possible to perform graphic electroplating directly on the conductive seed crystal layer (for example, when the conductive seed crystal layer is thicker).

Several methods for manufacturing a single-layer circuit board are described above. Hereinafter, several method embodiments for manufacturing a multi-layer circuit board according to the present invention will be described.

Figure 7 is a flow chart illustrating a method for manufacturing a multilayer circuit board according to a fourth embodiment of the present invention, and Figure 8 is a schematic cross-sectional view of a product corresponding to each step of the method shown in Figure 7 . As shown in Figure 7 , the method includes the following steps: arranging and laminating the boards in the order of metal foil, intermediate laminating layer, single-layer circuit board, intermediate laminating layer, single-layer circuit board, ..., intermediate laminating layer, and metal foil (step S1); drilling holes, including blind vias and/or through vias, in the laminated multilayer board (step S2); forming a conductive seed layer on the hole walls (step S3); and removing a portion of the metal foil to form a circuit pattern (step S4). (a), (b), (c), and (d) in Figure 8 correspond to steps S1, S2, S3, and S4, respectively. The steps of the method will be described in detail below with reference to both Figures 7 and 8 .

In step S1, the number of layers of the single-layer circuit board can be adjusted as needed, for example, it can be one or more layers. When the number of layers of the single-layer circuit board is one layer, a three-layer circuit board can be obtained in the end, and when the number of layers of the single-layer circuit board is two layers, a four-layer circuit board can be obtained in the end. Moreover, each single-layer circuit board can be the same or different circuit boards. As an example of metal foil, materials with good conductivity such as copper foil or aluminum foil are generally used. In addition, the intermediate bonding layer is used to press the single-layer circuit boards together, and between the single-layer circuit board and the metal foil. Generally, PP, PI, PTO, PC, PSU, PES, PPS, PS, PE, PEI, PTFE, PEEK, PA, PET, PEN, LCP, PPA, etc., or a pure resin film (such as epoxy resin film) that does not contain glass fiber cloth can be used. In addition, each bonding layer between the single-layer circuit boards and between the single-layer circuit board and the metal foil can be made of the same material or different materials. In the example shown in FIG8(a), two single-layer circuit boards 10 prepared by the method shown in FIG1 are used. The single-layer circuit board 10 is provided with holes and is formed with an ion implantation layer 131 implanted below the hole wall and below a portion of the surface, and a plasma deposited layer 132 attached to the ion implantation layer. Of course, the single-layer circuit board used here can also be a single-layer circuit board with only an ion implantation layer 131 as shown in FIG2 , and can have holes with a conductive layer or no holes, and can also be a circuit board made of metal foil commonly used in the art. Moreover, the intermediate bonding layer used here can also be a bonding layer with holes, especially through holes, in which a conductive layer is formed on the hole wall. The conductive layer can be a conductive seed layer including an ion implantation layer as described herein, or it can be a metal layer formed by conventional magnetron sputtering or other methods, as long as it can conduct electricity.

Next, holes are drilled in the laminated multilayer board (step S2). These holes may include blind holes and/or through holes. Step S2 corresponds to step S1 in the method shown in Figure 1 and can be performed in the same manner. As shown in Figure 8(b), through holes 17 and blind holes 18 are formed in the laminated multilayer board. Through holes 17 penetrate the entire multilayer board, while blind holes 18 only penetrate the metal foil 21 and the intermediate bonding layer 22 adjacent to the metal foil. Of course, only through holes 17 or blind holes 18 can be formed.

Then, a conductive seed layer is formed on the hole wall (S3). This step S3 is similar to step S3 in the method shown in Figure 1 and can be performed in the same manner. The difference is that since the metal foil is located on the outer surface of the multilayer board, the method of this embodiment does not necessarily form a conductive seed layer on the surface of the metal foil, but only needs to form the conductive seed layer on the hole wall. Of course, if ion implantation or plasma deposition is performed without taking protective measures on the metal foil, the conductive seed layer will also be formed on the outer surface of the metal foil. As shown in Figure 8(c), on the hole wall 19 of the through hole 17 and the blind hole 18, a conductive seed layer is formed, which is composed of an ion implantation layer 131 below the injection hole wall 19 and a plasma deposition layer 132 attached to the top of the ion implantation layer 131. Of course, if plasma deposition is not included in step S3, the conductive seed layer will only consist of the ion implantation layer 131 below the injection hole wall 19.

Finally, a portion of the metal foil is removed to form a circuit pattern (step S4). Since the metal foil is conductive, in this step, simply removing the metal foil in the non-circuit areas through conventional etching or other methods can yield a multilayer circuit board with a surface circuit pattern. For example, in step S4, a protective layer (e.g., tin) can be applied over the surface of the metal foil in the circuit area, followed by etching to remove the metal foil in the non-circuit areas, thereby yielding the final circuit pattern.

As shown in FIG8( d ), the metal foil 21 in the non-circuit area 162 is removed, and only the metal foil 21 in the circuit area 161 is retained, thereby forming a circuit pattern 16. The multilayer circuit board 20 produced by the above method is composed of the metal foil 21, the intermediate laminating layer 22, the single-layer circuit board 10, the intermediate laminating layer 22, the single-layer circuit board 10, the intermediate laminating layer 22, and the metal foil 21 in sequence. Holes 17 and 18 are opened in the multilayer circuit board 20, and a conductive seed layer is formed on the hole wall 19 of the hole. Part of the metal foil 21 is removed to form the circuit pattern layer 16, wherein the conductive seed layer includes an ion implantation layer 131 implanted below the hole wall 19 and a plasma deposited layer 132 attached to the ion implantation layer 131. Of course, the conductive seed layer can also be composed of only the ion implantation layer 131. In addition, the multilayer circuit board 20 also includes a through hole penetrating the multilayer circuit board, a blind hole formed on its surface, and blind holes formed in the single-layer circuit board and the intermediate laminating layer.

Alternatively, after step S3 and before step S4, the method of this embodiment may further include forming a conductor thickening layer on the conductive seed crystal layer to improve its conductivity. The conductor thickening layer may be formed by the method described above.

According to the method shown in FIG8 , a hole is formed in a multilayer circuit board, and an ion implantation layer is formed below the hole wall through ion implantation. As discussed above, ion implantation helps to form a strong bonding force between the substrate and the conductive seed layer, and can also make the surface of the conductive seed layer have good uniformity and density, and is less prone to pinholes. In addition, during microporous metallization, problems such as uneven hole wall conductor layer, holes or cracks will not occur, thereby effectively improving the conductivity of the metallized hole.

FIG9 is a flow chart showing a method for manufacturing a multilayer circuit board according to a fifth embodiment of the present invention, and FIG10 is a cross-sectional schematic diagram showing a product corresponding to each step of the method shown in FIG9 . As shown in FIG9 , the method includes the following steps: arranging and laminating the boards in the order of a surface laminating layer, a single-layer circuit board, an intermediate laminating layer, a single-layer circuit board, ..., and a surface laminating layer (step S1); drilling holes in the laminated multilayer board, including blind holes and/or through holes (S2); forming a conductive seed layer on the outer surface of the surface laminating layer and the hole walls of the holes (S3); forming a conductor thickening layer on the conductive seed layer (S41); covering the outer surface of the surface laminating layer with a photoresist film and performing exposure and development (S42); and etching and stripping the film to form a circuit pattern (S43). Steps S41 to S43 are all steps for forming the circuit pattern on the outer surface of the surface laminating layer. When the conductor thickening layer is formed by electroplating, these steps can be collectively referred to as "full board electroplating." (a), (b), (c), (d), (e) and (f) in FIG10 correspond to the above-mentioned steps S1, S2, S3, S41, S42 and S43, respectively.

In the method of this embodiment, step S1 is similar to step S1 in the method shown in Figure 7, except that no metal foil is used. Step S2 corresponds to step S2 in the method shown in Figure 7. Step S3 is similar to step S3 in the method shown in Figure 7, except that a conductive seed layer is formed not only on the hole walls but also on the outer surface of the surface bonding layer. In addition, steps S41 to S43 correspond to steps S31 to S33 in the method shown in Figure 3, respectively, and can be performed using a similar full-plate electroplating method.

As shown in FIG10( f ), the multilayer circuit board 20 obtained by the method of this embodiment is composed of a surface laminating layer 23, a single-layer circuit board 10, an intermediate laminating layer 22, a single-layer circuit board 10, and a surface laminating layer 23 in sequence. Holes 17 and 18 are provided in the multilayer circuit board 20, a conductive seed layer is formed on the hole wall 19 of the hole, and a circuit pattern layer 16 having a conductive seed layer is formed on a portion of the outer surface of the surface laminating layer 23, wherein the conductive seed layer includes an ion implantation layer 131 implanted below the hole wall 19 and below a portion of the outer surface of the surface laminating layer 23, and a plasma deposition layer 132 attached to the ion implantation layer 131. Of course, the conductive seed layer 13 can also be composed of only the ion implantation layer 131. The circuit pattern layer 16 also includes a conductor thickening layer 15, which is of course not required.

FIG11 is a flow chart showing a method for manufacturing a multilayer circuit board according to a sixth embodiment of the present invention, and FIG12 is a cross-sectional schematic diagram showing a product corresponding to each step of the method shown in FIG11 . The method includes the following steps: arranging and laminating the boards in the order of a surface lamination layer, a single-layer circuit board, an intermediate lamination layer, a single-layer circuit board, ..., a surface lamination layer (step S1); drilling holes in the laminated multilayer board, including blind holes and/or through holes (S2); forming a conductive seed layer on the outer surface of the surface lamination layer and the hole walls (S3); covering the outer surface of the surface lamination layer with a photoresist film and exposing and developing it (S41); performing electroplating (S42); and performing stripping and etching to form a circuit pattern (S43). Steps S41 to S43 are all steps for forming a circuit pattern on the outer surface of the surface lamination layer, which can be collectively referred to as "pattern plating." Compared with the method shown in FIG9 , the method of this embodiment differs in that pattern plating is used instead of full-board electroplating to form the circuit pattern. (a), (b), (c), (d), (e) and (f) in Figure 12 correspond to the above-mentioned steps S1, S2, S3, S41, S42 and S43 respectively.

In the method of this embodiment, steps S1, S2, and S3 correspond to steps S1, S2, and S3, respectively, in the method shown in FIG9 , and can be performed using the various methods described above with respect to FIG9 . Furthermore, steps S41 through S43 correspond to steps S31 through S33, respectively, in the method shown in FIG5 , and can be performed using a similar pattern plating method. As shown in FIG12( f ), the multilayer circuit board 20 produced by the method of this embodiment has the same structure as the multilayer circuit board 20 shown in FIG10( f ).

According to the method for manufacturing a multilayer circuit board shown in Figure 9 or Figure 11, the metallization of the outer surface of the surface lamination layer and the metallization of the hole can be carried out simultaneously. Therefore, a multilayer circuit board with metallized vias and surface circuit patterns can be directly obtained by one-time molding, without the need to cover the thicker metal foil in advance and then etch and thin the metal foil to drill holes as in the prior art, and it is necessary to form a conductive layer on the hole wall by processes such as chemical copper deposition or black holes and black shadows to obtain metallized vias. Compared with the prior art, the process flow of the method of the present invention is significantly shortened, and the use of etching solution can be reduced, which is beneficial to environmental protection. In addition, by adjusting various process parameters, such a method is easy to obtain a surface circuit pattern layer with an extremely thin thickness (less than 12 μm, such as 5 μm, 7 μm, 9 μm, etc.), and the resulting multilayer circuit board can be advantageously applied to high-end precision electronic products based on HDI (high-density interconnect substrate) and COF (flexible chip) technology.

Similarly, the multilayer circuit boards produced using the aforementioned methods exhibit a strong bond between the hole walls and the conductive seed layer due to the presence of the ion-implanted layer in the hole walls. This prevents the conductive layer in the hole walls from easily falling off or being scratched during subsequent processing or application. This improves the conductivity of the holes and facilitates the production of multilayer circuit boards with excellent conductivity.

The above describes in detail the methods for manufacturing single-layer circuit boards and multi-layer circuit boards according to the present invention, as well as the specific structures of the single-layer and multi-layer circuit boards produced by these methods. Below, several examples for implementing the present invention will be illustrated to enhance understanding of the present invention.

(Example 1)

This example uses an organic polymer film as a substrate to produce a flexible circuit board with metallized holes, specifically a liquid crystal polymer film (LCP film) as the substrate.

First, the surface of the LCP membrane is gently wiped with alcohol-soaked gauze to remove any dirt. Next, a series of 20μm-diameter through-holes are drilled through the membrane using laser drilling technology. The membrane surface and hole walls are then thoroughly cleaned using a hair dryer or other cleaning agent to remove any remaining drill cuttings and other dirt.

Next, a layer of photoresist is applied to the cleaned LCP film substrate surface, and the substrate is placed on a photolithography machine for exposure and development. The material in the area on the substrate surface where the circuit pattern will be formed (also known as the circuit area) is then washed away, resulting in a circuit negative image (also known as the photoresist layer) coated with a photoresist coating. At this point, the photoresist layer only exists in the non-circuit area on the substrate surface.

Next, the substrate, which has formed a negative circuit image on the photoresist layer after exposure and development, is placed in an oven for drying and then transferred to an ion implantation system for ion implantation. In this ion implantation system, the ion implantation chamber is evacuated to 8.5× ^10⁻³ Pa. Using Ni as the target, the appropriate injection voltage and current are selected so that the ionized Ni ions have an injection energy of approximately 60 keV. Ion implantation is performed on the surface and pore walls of the LCP film substrate, implanting the Ni ions beneath the surface and pore walls of the LCP film. Subsequently, Cu is selected as the target, and plasma deposition is performed on the surface and pore walls of the LCP film. At this point, the plasma deposition voltage can be adjusted to ensure that the energy of the deposited Cu ions is 1000 eV, resulting in a measured square resistance of the copper-clad laminate substrate after plasma deposition of less than 30 Ω/□.

The copper film on the LCP film substrate was then thickened to 5μm using magnetron sputtering. The specific process involved evacuating the coating chamber of the magnetron sputtering machine to ^10-2 Pa, filling it with argon gas, and adjusting the pressure to 10Pa to clean the film surface. The chamber was then evacuated to ^10-3 Pa, and the operating voltage and sputtering duty cycle were adjusted to 500V and 70%. Using copper as a target, the surface and pore walls of the LCP film substrate were sputtered, depositing a 5μm-thick copper layer.

Next, the LCP film substrate, bearing the negative circuit image of the photoresist layer, the conductive seed layer, and the conductor thickening layer, is placed in a stripping solution suitable for dissolving the photoresist layer. Stirring or shaking is performed to accelerate the dissolution of the photoresist layer. During the dissolution of the photoresist layer, the conductive seed layer and conductor thickening layer above the photoresist layer also detach from the substrate surface and enter the stripping solution. After the negative circuit image of the photoresist layer is completely dissolved, the substrate surface is thoroughly cleaned with an appropriate cleaning agent and then dried in an oven. This results in the desired circuit pattern on the substrate surface.

Finally, the resulting circuit board can be annealed by baking it in an oven at 80-100°C for 15 hours to eliminate stress in the copper layer and prevent cracking. Next, the board can be immersed in a passivation solution containing 1g/L of benzotriazole or its derivatives in water for approximately one minute before being air-dried to prevent oxidation and discoloration of the copper in the air.

(Example 2)

This example uses epoxy glass cloth as a substrate to manufacture a rigid single-layer circuit board with metallized holes, and then uses the single-layer circuit board to make a multi-layer circuit board, specifically using FR-4 or FR-5 substrate in the epoxy glass cloth substrate.

First, the upper surface of the FR-4 substrate is gently wiped with alcohol-soaked gauze to remove any contaminants. Next, laser drilling is used to drill several through-holes with a diameter of approximately 100 μm and several blind vias with a diameter of approximately 100 μm and a depth of approximately 200 μm. After drilling, the FR-4 substrate surface and hole walls are thoroughly cleaned using ultrasonic technology and then dried to remove any remaining drill cuttings and other contaminants.

Next, the dried substrate is placed into the ion implantation equipment via a discharge mechanism. The ion implantation chamber is evacuated to 2× ^10⁻³ Pa. Using Ni as the target, the appropriate injection voltage and current are selected to achieve an injection energy of 30 keV for the Ni ions. Ni ions are then implanted below the top surface of the FR-4 substrate and below the pore walls. Next, Cu is selected as the target, and plasma deposition is performed on the top surface of the FR-4 substrate and the pore walls. The plasma deposition voltage is adjusted to achieve an energy of 1000 eV for the deposited Cu ions, resulting in a measured sheet resistance of less than 50 Ω/□ for the FR-4 substrate with the conductive seed layer.

Next, a photoresist film is applied to the surface of the FR-4 substrate with the conductive seed layer. The substrate is then placed on a photolithography machine for exposure and development. The material in the circuit area on the substrate surface is then cleaned away, leaving a photoresist layer with a negative image of the circuit. At this point, the photoresist layer exists only in the non-circuit area on the substrate surface, but the conductive seed layer also exists beneath it.

The copper film in the circuit area on the substrate surface was then thickened to 5μm on a copper electroplating line. The electroplating solution consisted of 100g/L copper sulfate, 50g/L sulfuric acid, 30mg/L chloride ion concentration, and a small amount of additives. The electroplating current density was set at 1A/ ^dm² and the temperature was set at 10°C. During the electroplating process, the photoresist layer, due to its insulating properties, could not be plated onto the copper layer. This meant that the electroplated conductor thickening layer would only be present in areas of the substrate surface where the photoresist layer was not present, namely, the circuit area.

Afterwards, the FR-4 substrate formed with a conductive seed layer, a photoresist layer with a circuit negative image, and a conductor thickening layer is placed in a corresponding stripping solution that can dissolve the photoresist layer, and stirring is performed to accelerate the dissolution of the photoresist layer. After the photoresist layer is completely dissolved, the conductive seed layer underneath it will be exposed. Next, a layer of tin is applied as a protective layer on the conductor thickening layer on the surface of the substrate, and then the substrate is etched to remove the conductive seed layer outside the area of the conductor thickening layer (i.e., the circuit area). Finally, the tin-plated layer on the conductor thickening layer is torn off to obtain the desired circuit pattern. Alternatively, a layer of tin can be applied as a protective layer on the conductor thickening layer on the surface of the substrate first, and then the photoresist layer can be removed with a stripping solution, and then the conductive seed layer originally located below the photoresist layer can be removed by etching. In this way, a single-layer circuit board with metallized holes and surface circuit patterns is obtained.

Next, using epoxy resin film as a laminating layer, the boards are assembled in the following order from bottom to top: copper foil, epoxy resin film, single-layer circuit board, epoxy resin film, single-layer circuit board, epoxy resin film, copper foil. These boards are then placed in a press and laminated to form a multilayer board. Of course, single-layer boards with more or fewer layers can also be used as needed.

Next, a mechanical drill is used to drill several through-holes with a diameter of approximately 100 μm in the resulting multilayer board, and several blind vias with a diameter of approximately 100 μm are drilled in the surface copper foil and epoxy resin film. After drilling, the surface of the multilayer board and the walls of the holes are thoroughly cleaned using ultrasonic cleaning technology and then dried to remove residual drill chips and other contaminants.

Then, the formed through holes and blind holes are metallized. Specifically, the dried and cleaned multilayer board is placed into the ion implantation equipment through the discharge mechanism, and the ion implantation chamber is evacuated to 2× ^10-3 Pa. Using Ni as the target material, the appropriate injection voltage and injection current are selected so that the injection energy of the Ni ions is 30keV, and the Ni ions are implanted into the upper and lower surfaces of the multilayer board and the hole walls to form an ion implantation layer. Afterwards, Cu is selected as the target material, and plasma deposition is performed on the upper and lower surfaces and the hole walls of the multilayer board to form a plasma deposition layer. The voltage of the plasma deposition can be adjusted so that the energy of the deposited Cu ions is 1000eV, so that the measured square resistance of the FR-4 substrate with the conductive seed layer is less than 50Ω/□. Then, the copper film on the conductive seed layer is thickened to 5μm on the copper electroplating production line. The composition of the electroplating solution is 100 g/L copper sulfate, 50 g/L sulfuric acid, 30 mg/L chloride ion concentration and a small amount of additives; the electroplating current density is set to 1 A/dm ² ; the temperature is set to 10°C.

Next, the desired circuit pattern is formed on the surface copper foil of the multilayer board, which already has metallized holes, through pattern plating. Specifically, a photoresist film (e.g., a YQ-30SD film or AQ-2058 film negative) is applied to the surface of the surface copper foil, exposed and developed, and then the material in the non-circuit areas is cleaned. At this point, the photoresist layer is only present in the circuit areas of the copper foil surface, while the copper foil in the non-circuit areas is exposed. Next, an acidic etching solution (HCl + _CuCl₂ ) is used to etch the copper foil in the non-circuit areas. Finally, a NaOH solution is used to strip the remaining photoresist film from the copper foil, exposing the copper foil underneath and ultimately achieving the desired surface circuit pattern.

Optionally, the resulting multilayer circuit board can be annealed to eliminate stress and prevent copper foil cracking. Specifically, the multilayer circuit board can be baked in an oven at 100-120°C for 12 hours. The annealed circuit board can then be immersed in a passivation solution for approximately one minute and then air-dried to prevent copper oxidation and discoloration in the air. The passivation solution is a 2g/L aqueous solution of benzotriazole and its derivatives.

(Example 3)

In this example, a double-sided flexible copper-clad laminate with an organic polymer film (eg, PI film) as a substrate is used to manufacture a single-layer circuit board, and then the single-layer circuit board is used to manufacture a multi-layer circuit board.

First, a single-layer circuit board was prepared. Specifically, using a polyvinyl chloride (PI) film as the substrate, both surfaces of the PI film were gently wiped with alcohol-soaked gauze to remove any contaminants. Next, a series of 10μm-diameter through-holes were drilled into the PI film using UV laser drilling. Ultrasonic cleaning was then used to thoroughly clean the surface and walls of the PI film to remove any remaining drill cuttings and other contaminants. The drilled PI film was then placed into an ion implantation system. The ion implantation chamber was evacuated to 1× ^10⁻⁴ Pa. Using Ni as the target, the injection voltage and current were adjusted to achieve an energy of 40 keV for the Ni ions. Ni ions were then implanted into both the upper and lower surfaces of the PI film substrate and into the pore walls. Next, Cu was used as the target, and plasma deposition was performed on both surfaces and the pore walls. The plasma deposition voltage was adjusted to achieve an energy of 500 eV for the deposited Cu ions, resulting in a measured sheet resistance of less than 40 Ω/□ for the PI film substrate with the conductive seed layer formed.

Next, the copper film on the PI film substrate was thickened to 5μm on a copper electroplating line. The electroplating solution consisted of 160g/L copper sulfate, 70g/L sulfuric acid, 60mg/L chloride ion concentration, and a small amount of additives. The electroplating current density was set at 2.5A/ ^dm² , and the temperature was set at 25°C. A photoresist film was then coated on the thickened copper layer of the PI film substrate and placed in a photolithography machine for exposure and development. The material in the non-circuit areas of the substrate surface was then washed away, resulting in a positive image of the circuit covered with the photoresist film. At this point, the photoresist layer was present only in the circuit areas on the surface of the conductive seed crystal layer.

Next, etching is performed to remove the conductive seed layer from the non-circuit areas. The circuit areas remain unetched due to the protective effect of the photoresist film. A stripping solution is then used to remove the photoresist film. The stripped substrate is then placed in an oven to dry, resulting in the desired circuit pattern on the substrate surface. This results in a single-layer circuit board with a circuit pattern and plated holes, which can then be used in the manufacture of multi-layer circuit boards.

Next, using PP film as a laminating layer, the boards are assembled in the order of PP, single-layer circuit board, PP, single-layer circuit board, and PP from bottom to top. These boards are then laminated in a press to form a multilayer board. Next, laser drilling is used to drill several through holes with a diameter of approximately 10 μm in the resulting multilayer board, and several blind holes with a diameter of approximately 10 μm are drilled in the surface PP layer. After drilling, the board's surface and hole walls are thoroughly cleaned using ultrasonic cleaning and other techniques, and then dried to remove any remaining drill cuttings and other contaminants.

Next, the drilled multilayer board is placed sequentially into an ion implantation system and a plasma deposition system. A conductive seed layer is formed on the surface of the surface PP film and along the walls of the holes, as described above. To form the circuit, a photoresist layer (e.g., YQ-40PN or ASG-302) is applied to both the upper and lower surfaces of the surface PP film with the thickened copper film. The film is then placed in a photolithography machine for exposure and development. Unnecessary photoresist material in the circuit area is then removed, leaving only the conductive seed layer exposed. The copper film in the conductive seed layer in the circuit area and the hole walls of the PP film is then thickened to 5 μm by electroplating. Following this, an 8 μm thick layer of tin is electroplated to protect the copper layer during subsequent etching. Next, the film is stripped using a NaOH (or KaOH) solution to expose the conductive seed layer outside the circuit area. Next, the conductive seed layer outside the circuit area is etched away using an alkaline etching solution _{( NH₄Cl} / _NH₃ • _H₂O ). Furthermore, the tin on the surface of the copper plating layer is removed using a _HNO₃ or _H₂O₂ solution in a dedicated device. This results in a multilayer circuit board with a circuit pattern. The cross-sectional structure of the multilayer circuit board at this point is shown in Figure 10(f).

The foregoing description merely mentions preferred embodiments of the present invention. However, the present invention is not limited to the specific embodiments described herein. It will be readily apparent to those skilled in the art that various obvious modifications, adjustments, and substitutions may be made to these embodiments to adapt them to specific circumstances without departing from the gist of the present invention. In fact, the scope of protection of the present invention is defined by the claims and may include other examples that may be envisioned by those skilled in the art. Such other examples will fall within the scope of protection of the claims if they have structural elements that are indistinguishable from the literal language of the claims, or if they include equivalent structural elements that are insignificantly different from the literal language of the claims.

Claims (25)

1. A method for manufacturing a multilayer circuit board, comprising: S1: Arrange and laminate the boards in the following order: metal foil, intermediate bonding layer, single-layer circuit board, intermediate bonding layer, single-layer circuit board, ..., intermediate bonding layer, metal foil; S2: Drilling holes in the laminated multilayer board, including through holes and/or blind holes; S3: A conductive seed layer is formed on the wall of the hole; and S4: Remove a portion of the metal foil to form a circuit pattern. Step S3 includes injecting a conductive material into the hole wall below the hole by ion implantation to form an ion implantation layer as at least a part of the conductive seed layer. 2. A method for manufacturing a multilayer circuit board, comprising: S1: Arrange and laminate the boards in the following order: surface lamination layer, single-layer circuit board, intermediate lamination layer, single-layer circuit board, intermediate lamination layer, single-layer circuit board, ..., surface lamination layer; S2: Drilling holes in the laminated multilayer board, including through holes and/or blind holes; S3: A conductive seed layer is formed on the outer surface of the surface bonding layer and on the hole wall; and S4: A circuit pattern is formed on the outer surface of the surface bonding layer. Step S3 includes ion implantation to inject conductive material below the outer surface of the surface bonding layer and below the hole wall to form an ion implantation layer as at least a part of the conductive seed layer. 3. The method according to claim 1, characterized in that, during the ion implantation, the ions of the conductive material acquire an energy of 1-1000 keV and are implanted to a depth of 1-500 nm below the pore wall. 4. The method according to claim 2, wherein during the ion implantation, the ions of the conductive material acquire an energy of 1-1000 keV and are implanted to a depth of 1-500 nm below the hole wall and/or below the outer surface of the surface bonding layer. 5. The method according to claim 1 or 2, wherein step S3 further includes depositing a conductive material onto the ion implantation layer by plasma deposition to form a plasma deposition layer, wherein the plasma deposition layer and the ion implantation layer constitute the conductive seed layer. 6. The method according to claim 5, wherein during the plasma deposition, the ions of the conductive material acquire an energy of 1-1000 eV to form the plasma deposition layer with a thickness of 1-10000 nm. 7. The method according to claim 1 or 2, wherein the conductive material constituting the conductive seed layer comprises one or more of Ti, Cr, Ni, Cu, Ag, Au, V, Zr, Mo, Nb and alloys thereof. 8. The method according to claim 1, wherein step S3 further comprises: forming a conductor thickening layer on the conductive seed layer formed on the hole wall. 9. The method according to claim 2, wherein step S4 comprises: first forming a conductor thickening layer on the conductive seed layer, and then performing pattern electroplating or full-board electroplating on the conductor thickening layer located above the outer surface of the surface bonding layer to obtain the circuit pattern. 10. The method according to claim 8 or 9, characterized in that the conductor thickening layer with a thickness of 0.01-1000 μm is formed by one or more of Al, Mn, Fe, Ti, Cr, Co, Ni, Cu, Ag, Au, V, Zr, Mo, Nb and alloys thereof, through electroplating, electroless plating, vacuum evaporation plating, sputtering. 11. The method according to claim 2, wherein step S4 comprises: performing patterned electroplating or full-board electroplating directly on the conductive seed layer formed on the outer surface of the surface bonding layer to obtain the circuit pattern. 12. The method according to claim 1 or 2, wherein at least one of the intermediate bonding layers has a hole, and a conductive layer is formed on the wall of the hole. 13. The method according to claim 1 or 2, wherein at least one of the single-layer circuit boards has a hole, and a conductive layer is formed on the wall of the hole. 14. The method according to claim 1, wherein the intermediate bonding layer comprises one or more of PP, PI, PTO, PC, PSU, PES, PPS, PS, PE, PEI, PTFE, PEEK, PA, PET, PEN, LCP, and PPA. 15. The method according to claim 2, wherein the intermediate bonding layer and/or the surface bonding layer comprises one or more of PP, PI, PTO, PC, PSU, PES, PPS, PS, PE, PEI, PTFE, PEEK, PA, PET, PEN, LCP, and PPA. 16. A multilayer circuit board, comprising, in sequence, a metal foil, an intermediate bonding layer, a single-layer circuit board, an intermediate bonding layer, a single-layer circuit board, ..., an intermediate bonding layer and a metal foil, wherein the multilayer circuit board has holes, a conductive seed layer is formed on the hole wall, and a portion of the metal foil is removed to form a circuit pattern layer, wherein the conductive seed layer includes an ion implantation layer implanted below the hole wall. 17. A multilayer circuit board, comprising, in sequence, a surface-mount layer, a single-layer circuit board, an intermediate bonding layer, another single-layer circuit board, ..., a surface-mount layer, wherein the multilayer circuit board has holes, a conductive seed layer is formed on the wall of the holes, and a circuit pattern layer having the conductive seed layer is formed on a portion of the outer surface of the surface-mount layer, wherein the conductive seed layer includes an ion implantation layer implanted below the wall of the holes and below a portion of the outer surface of the surface-mount layer. 18. The multilayer circuit board according to claim 16, wherein the ion implantation layer is located at a depth of 1-500 nm below the hole wall. 19. The multilayer circuit board according to claim 17, wherein the ion implantation layer is located at a depth of 1-500 nm below the hole wall and/or below a portion of the outer surface of the surface bonding layer. 20. The multilayer circuit board according to claim 16 or 17, wherein the conductive seed layer further comprises a plasma deposition layer attached above the ion implantation layer, the plasma deposition layer having a thickness of 1-10000 nm. 21. The multilayer circuit board according to claim 16 or 17, wherein the conductive seed layer is composed of a conductive material, the conductive material including one or more of Ti, Cr, Ni, Cu, Ag, Au, V, Zr, Mo, Nb and alloys thereof. 22. The multilayer circuit board according to claim 16 or 17, characterized in that a conductor thickening layer with a thickness of 0.01-1000 μm is formed above the conductive seed layer. 23. The multilayer circuit board according to claim 16 or 17, wherein the hole is a through hole penetrating the multilayer circuit board, a blind hole formed on the surface of the multilayer circuit board, or a blind hole formed in the single-layer circuit board or the intermediate bonding layer. 24. The multilayer circuit board according to claim 16, wherein the intermediate bonding layer comprises one or more of PP, PI, PTO, PC, PSU, PES, PPS, PS, PE, PEI, PTFE, PEEK, PA, PET, PEN, LCP, and PPA. 25. The multilayer circuit board according to claim 17, wherein the intermediate bonding layer and/or the surface bonding layer comprises one or more of PP, PI, PTO, PC, PSU, PES, PPS, PS, PE, PEI, PTFE, PEEK, PA, PET, PEN, LCP, and PPA.