HK1218023A1

HK1218023A1 - Image sensor pixel cell with non-destructive readout

Info

Publication number: HK1218023A1
Application number: HK16105892.0A
Authority: HK
Inventors: 約翰內斯．索爾胡斯維克; 约翰内斯．索尔胡斯维克; 多米尼克．馬塞提; 多米尼克．马塞提
Original assignee: 豪威科技股份有限公司
Priority date: 2014-09-29
Filing date: 2016-05-24
Publication date: 2017-01-27
Also published as: EP3001458B1; US20160093664A1; US9406718B2; TWI578788B; TW201615004A; CN105470273B; CN105470273A; EP3001458A1

Abstract

A pixel cell includes a photodiode coupled to photogenerate image charge in response to incident light. A deep trench isolation structure is disposed proximate to the photodiode to provide a capacitive coupling to the photodiode through the deep trench isolation structure. An amplifier transistor is coupled to the deep trench isolation structure to generate amplified image data in response to the image charge read out from the photodiode through the capacitive coupling provided by the deep trench isolation structure. A row select transistor is coupled to an output of the amplifier transistor to selectively output the amplified image data to a column bitline coupled to the row select transistor.

Description

Image sensor pixel cell with non-destructive readout

Technical Field

The present invention relates generally to image sensors. More specifically, examples of the invention relate to circuits that read out image data from image sensor pixel cells.

Background

Image sensors have become ubiquitous. It is widely used in digital cameras, cellular phones, security cameras, as well as in medical, automotive and other applications. The technology used to fabricate image sensors, and in particular Complementary Metal Oxide Semiconductor (CMOS) image sensors, has been constantly and rapidly advancing. Furthermore, the increased demand for higher resolution and lower power consumption has facilitated further miniaturization and integration of these image sensors.

As pixel cells become smaller, the need for image sensors to operate over a large range of lighting conditions, ranging from low-light conditions to bright-light conditions, becomes increasingly difficult to achieve. Such performance capabilities are often referred to as having High Dynamic Range (HDR). In conventional image capture devices with small photosensitive devices, the pixel cell typically requires multiple successive samples or exposures of the photodiode with long and short integration times to achieve HDR.

In a conventional CMOS pixel cell, image charge is transferred from a photosensitive device (e.g., a photodiode) and converted to a voltage signal on a floating diffusion node inside the pixel cell. The challenge with this approach is that each readout of a conventional pixel cell is destructive. In particular, the charge in the photodiode disappears after each readout, which reduces the light sensitivity compared to a pixel cell that can accumulate light during the entire frame time.

Disclosure of Invention

One embodiment of the invention relates to a pixel cell, comprising: a photodiode coupled to produce image charge in response to incident light; a deep trench isolation structure disposed proximate to the photodiode to provide capacitive coupling to the photodiode through the deep trench isolation structure; an amplifier transistor coupled to the deep trench isolation structure to generate amplified image data in response to the image charge read out of the photodiode through the capacitive coupling provided by the deep trench isolation structure; and a row select transistor coupled to an output of the amplifier transistor to selectively output the amplified image data to a column bit line coupled to the row select transistor.

Another embodiment of the invention is directed to an imaging system, comprising: a pixel array comprising a plurality of pixel cells, wherein each of the pixel cells comprises: a photodiode coupled to produce image charge in response to incident light; a deep trench isolation structure disposed proximate to the photodiode to provide capacitive coupling to the photodiode through the deep trench isolation structure; an amplifier transistor coupled to the deep trench isolation structure to generate amplified image data in response to the image charge read out of the photodiode through the capacitive coupling provided by the deep trench isolation structure; and a row select transistor coupled to an output of the amplifier transistor to selectively output the amplified image data to a column bit line coupled to the row select transistor; control circuitry coupled to the pixel array to control operation of the pixel array; and readout circuitry coupled to the pixel array to readout the amplified image data from each of the plurality of pixel cells of the pixel array.

Drawings

Non-limiting and non-exhaustive embodiments of the present invention are described with reference to the following figures, wherein like reference numerals refer to like parts throughout the various views unless otherwise specified.

Figure 1 is a schematic diagram illustrating one example of an image sensor pixel cell including non-destructive readout according to the teachings of this disclosure.

Figure 2 is a diagram illustrating the layout of an exemplary image sensor pixel cell including non-destructive readout according to the teachings of this disclosure.

Figure 3 is a schematic illustrating another example of an image sensor pixel cell including non-destructive readout according to the teachings of this disclosure.

Figure 4 is a diagram illustrating a layout of another exemplary image sensor pixel cell including non-destructive readout according to the teachings of this disclosure.

Figure 5 is a block diagram illustrating an example imaging system including a pixel array with non-destructive readout of pixel cells according to the teachings of this disclosure.

Corresponding reference characters indicate corresponding parts throughout the several views of the drawings. Skilled artisans will appreciate that elements in the figures are illustrated for simplicity and clarity and have not necessarily been drawn to scale. For example, the dimensions of some of the elements in the figures may be exaggerated relative to other elements to help improve understanding of various embodiments of the present invention. Additionally, common but well-understood elements that are useful or necessary in a commercially feasible embodiment are often not depicted in order to facilitate a less obstructed view of these various embodiments of the present invention.

Detailed Description

In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present invention. However, it will be apparent to one skilled in the art that the specific details need not be employed to practice the present invention. In other instances, well-known materials or methods have not been described in detail in order to avoid obscuring the present invention.

Reference throughout this specification to "one embodiment," "an embodiment," "one example," or "an example" means that a particular feature, structure, or characteristic described in connection with the embodiment or example is included in at least one embodiment of the present invention. Thus, the appearances of the phrases "in one embodiment," "in an embodiment," "one example" or "an example" in various places throughout this specification are not necessarily all referring to the same embodiment or example. Furthermore, the particular features, structures, or characteristics may be combined in any suitable combination and/or sub-combination in one or more embodiments or examples. The particular features, structures, or characteristics may be included in integrated circuits, electronic circuits, combinational logic circuits, or other suitable components that provide the described functionality. Additionally, it should be appreciated that the figures provided herewith are for purposes of explanation to persons skilled in the art and that the drawings are not necessarily drawn to scale.

Examples in accordance with the teachings of this disclosure describe examples of image sensor pixel cells having non-destructive readout in accordance with the teachings of this disclosure. As will be shown, in various examples, a capacitive coupling is provided to the photodiode in each pixel cell by which a non-destructive readout of the pixel cell can be performed. For example, in various examples, a deep trench isolation structure is disposed proximate to a photodiode of each pixel cell in a pixel array to sense a voltage in the photodiode without affecting accumulated charge in the photodiode. Thus, according to the teachings of this disclosure, a non-destructive readout of a pixel cell may be provided for techniques such as Automatic Exposure Control (AEC), which thus improves the overall light sensitivity of the pixel cell as compared to conventional pixel cells, since light may be accumulated during the entire frame time of the pixel cell.

To illustrate, FIG. 1 is a schematic diagram illustrating one example of an image sensor pixel cell 102 including a non-destructive readout, according to the teachings of this disclosure. In the depicted example, the pixel cell 102 includes a photodiode PD104 coupled to generate image charge in response to incident light 136. Deep trench isolation structure C_DTI116 is close to lightThe photodiode PD104 is disposed to isolate the structure C by a deep trench_DTI116 provide capacitive coupling to the photodiode PD 104. In the exemplary schematic depicted in FIG. 1, a deep trench isolation structure C_DTI116 are illustrated as capacitors coupled to provide capacitive coupling to the photodiode PD 104.

Amplifier transistor 112 is coupled to deep trench isolation structure C_DTI116 in response to isolation of the structure C by the deep trench_DTI116 to couple out image charge from the photodiode PD104 to produce amplified image data. In the exemplary schematic depicted in fig. 1, the switching transistor 120 is coupled to a deep trench isolation structure C_DTI116 and the floating diffusion FD110, as shown, the FD110 is coupled to an amplifier transistor 112. In the depicted example, the amplifier transistor 112 is a source follower coupled transistor, the gate terminal of which is selectively coupled to the deep trench isolation structure C by the switching transistor 120_DTI116. The row select transistor 114 is coupled to the output of the amplifier transistor 114 to selectively output amplified image data to a column bit line 118 coupled to the row select transistor 114.

As shown in the depicted example, a floating diffusion FD110 is coupled to the amplifier transistor 112, and a transfer transistor 106 is coupled between the photodiode PD104 and the floating diffusion FD110 to selectively couple the floating diffusion FD110 to the photodiode PD 104. A reset transistor 108 is coupled to the floating diffusion FD110 to selectively reset the charge in the floating diffusion FD110 and the photodiode PD 104. For example, in one example, the charge in the floating diffusion FD110 may be reset to a reset voltage by the reset transistor 108, and the charge in the photodiode PD104 may be reset to a reset voltage by the reset transistor 108 and the transfer transistor 106. In the exemplary schematic illustrated in FIG. 1, the structure C is isolated by a deep trench_DTIThe charge in the capacitive coupling provided by 116 may be reset to a reset voltage through reset transistor 108 and switching transistor 120. In one example, it is appreciated that coupling to a deep trenchIsolation structure C_DTI116 to isolate structure C from deep trench_DTIThe reset voltage to reset the charge in 116 may be a different reset voltage than the reset voltage coupled to reset the charge in the photodiode PD104 and/or the floating diffusion PD 110. In one example, the different reset voltages may be switched on the reset supply side before the reset transistor 108 is activated.

Thus, in one example, the deep trench isolation structure C can be first isolated by first beginning the deep trench during reset of the photodiode PD104 just before integration begins_DTI116 are reset to a known potential to perform sensing of the pixel cell 102. Next, integration may begin with the photodiode PD104 generating charge in response to incident light 136. In one example, Correlated Double Sampling (CDS) may be performed by first resetting the floating diffusion FD110 to a reset voltage by the reset transistor 108. The charge on the floating diffusion FD110 after reset may then be sampled (e.g., SHR) from the column bit line 118 by the amplifier transistor 112 and the row select transistor 118. Next, the floating diffusion FD110 may then be shorted to the deep trench isolation structure C by closing (i.e., turning on) the switching transistor 120, according to the teachings of this disclosure_DTI116 to sample the non-destructive reading of the charge photo-generated in the photodiode PD104, which will be through the isolation of the structure C by the deep trench_DTIThe capacitive coupling provided by 116 non-destructively samples image charge (e.g., SHS) photo-generated in the photodiode PD104 in response to the incident light 136.

Assume the sample value of the floating diffusion FD110 after reset is SHR and assume the floating diffusion FD110 is shorted to the deep trench isolation structure C at the switching transistor 120_DTIThe sample of the floating diffusion FD110 after 116 is SHS, then the Correlated Double Sampling (CDS) signal value is SHS-SHR. In one example, it should be appreciated that according to the teachings of this disclosure, the photodiode PD104 may then be read out through the transfer transistor 106, floating diffusion FD110, amplifier transistor 112, row select transistor 114, and column bit line 118 by monitoring the CDS signal value until a threshold charge is generated in the photodiode PD104 (at which time the photodiode may then be read out through the transfer transistor 106, floating diffusion FD110, amplifier transistor 112, row select transistor 114, and column bit line 118The generated image charge in the tube PD 104) to implement Automatic Exposure Control (AEC).

Figure 2 is a diagram illustrating the layout of an example image sensor pixel cell 202 with non-destructive readout included in a semiconductor chip according to the teachings of this disclosure. It should be understood that the image sensor pixel cell 202 illustrated in fig. 2 may be one example of the pixel cell 102 shown in fig. 1, and that similarly named and numbered elements below are coupled and function as described above. As shown in the example, the pixel cell 202 includes a photodiode 204 coupled to produce image charge in response to incident light 236. The deep trench isolation structure 216 is disposed proximate to the photodiode 204 to provide capacitive coupling to the photodiode 204 through the deep trench isolation structure 216.

The amplifier transistor 212 is coupled to the deep trench isolation structure 216 to generate amplified image data in response to image charge read out of the photodiode 204 through capacitive coupling provided by the deep trench isolation structure 216. In the example schematic depicted in fig. 2, a switching transistor 220 is coupled between the deep trench isolation structure 216 and the floating diffusion FD210, as shown, the FD210 is coupled to an amplifier transistor 212. In the depicted example, the amplifier transistor 212 is a source follower coupled transistor, the gate terminal of which is selectively coupled to the deep trench isolation structure 216 by a switching transistor 220. A row select transistor 214 is coupled to the output of the amplifier transistor 214 to selectively output amplified image data to a column bit line 218 coupled to the row select transistor 214.

As shown in the depicted example, the floating diffusion FD210 is coupled to an amplifier transistor 212, and a transfer transistor 206 is coupled between the photodiode 204 and the floating diffusion FD210 to selectively couple the floating diffusion FD210 to the photodiode 204. A reset transistor 208 is coupled to the floating diffusion FD210 to selectively reset the charge in the floating diffusion FD210 and the photodiode 204. For example, in one example, the charge in the floating diffusion FD210 may be reset to a reset voltage by the reset transistor 208, and the charge in the photodiode 204 may be reset to a reset voltage by the reset transistor 208 and the transfer transistor 206. In the exemplary schematic illustrated in fig. 2, the charge in the capacitive coupling provided by the deep trench isolation structures 216 may be reset to a reset voltage by the reset transistor 208 and the switching transistor 220.

In the example depicted in fig. 2, a conductive material 238 (e.g., polysilicon, etc.) is disposed within the deep trench isolation structure 216. In the example, the oxide material 228 lines the interior of the deep trench isolation structure 216. In one example, the oxide material 228 lining the interior of the deep trench isolation structure 216 is a charged oxide trench liner. For example, in one example, the oxide material 228 may be a negatively charged oxide trench liner, and in another example, the oxide material 228 may be a positively charged oxide liner. As such, it should be appreciated that in the illustrated example, the capacitance of the capacitive coupling to the photodiode 204 provided with the deep trench isolation structure 216 is suitably matched to sense the image charge accumulated in the photodiode 204 in accordance with the teachings of the present invention.

Figure 3 is a schematic diagram illustrating another example of an image sensor pixel cell 302 including a non-destructive readout, according to the teachings of this disclosure. It should be appreciated that the image sensor pixel cell 302 illustrated in fig. 3 shares similarities with the pixel cell 102 shown in fig. 1 and/or the pixel cell 202 shown in fig. 2, and similarly-named and numbered elements below are coupled and function as described above. In the depicted example, pixel cell 302 includes a photodiode PD304 coupled to generate image charge in response to incident light 336. Deep trench isolation structure C_DTI316 are disposed proximate to the photodiode PD304 to isolate the structure C by a deep trench_DTI316 provide capacitive coupling to the photodiode PD 304. In the exemplary schematic depicted in FIG. 3, a deep trench isolation structure C_DTI316 are illustrated as capacitors coupled to provide capacitive coupling to the photodiode PD 304.

As shown in the illustrated example, the first amplifier transistor 312A is coupled to a deep trench isolation structure C_DTI316 in response to passing through the isolation structure C by the deep trench_DTI316 to couple out image charge from the photodiode PD304 to produce first amplified image data. The first row select transistor 314A is coupled to the output of the first amplifier transistor 314A to selectively output first amplified image data to a column bit line 318 coupled to the first row select transistor 314A.

In the depicted example, the first amplifier transistor 312A is a source follower coupled transistor having its gate terminal coupled to the deep trench isolation structure C_DTI316 to provide a non-destructive readout of the image charge in the photodiode PD 304. In this example, the first row select transistor 314A is coupled to selectively output a non-destructive readout from the first amplifier transistor 312A to the column bit line 318 according to the teachings of this disclosure. It should therefore be appreciated that the first amplifier transistor 312A and the first row select transistor 314A are used for non-destructive readout of the pixel cell 302.

In one example, the pixel cell 302 further includes a second amplifier transistor 312B and a floating diffusion FD310 coupled to generate second amplified image data in response to image charge read out of the photodiode PD304 through the floating diffusion FD 310. In this example, a second row select transistor 314B is coupled to the output of the second amplifier transistor 312B to selectively output second amplified image data to a column bit line 318 coupled to the second row select transistor 314B in accordance with the teachings of this disclosure.

As shown in the example depicted in fig. 3, a floating diffusion FD310 is coupled to the second amplifier transistor 312B, and a transfer transistor 306 is coupled between the photodiode PD304 and the floating diffusion FD310 to selectively couple the floating diffusion FD310 to the photodiode PD 304. A reset transistor 308 is coupled to the floating diffusion FD310 to selectively couple the floating diffusion FD310 and electricity in the photodiode PD304The load is reset. For example, in one example, the charge in the floating diffusion FD310 may be reset to a reset voltage by the reset transistor 308, and the charge in the photodiode PD304 may be reset to a reset voltage by the reset transistor 308 and the transfer transistor 306. In one example, the pixel cell 302 further includes an optional reset connection 309, the structure C can also be isolated by the deep trench via the reset transistor 308 by the optional reset connection 309_DTI316 to a reset voltage. In one example, it is appreciated that coupling to the deep trench isolation structure C through an optional reset connection 309_DTI316 to isolate structure C from deep trench_DTIThe reset voltage at which the charge in 316 is reset may be a different reset voltage than the reset voltage coupled to reset the charge in the photodiode PD304 and/or the floating diffusion PD 310. In one example, the different reset voltage may be switched on the reset supply side before the reset transistor 308 is activated.

Similar to the examples detailed above, the structure C can be isolated by means of a deep trench_DTIThe capacitive coupling provided by 316, the first amplifier transistor 312A, the first row select transistor 314A, and the column bit line 318, to monitor the image charge accumulated in the photodiode PD304 with a non-destructive readout. In one example, it should be appreciated that Automatic Exposure Control (AEC) may be achieved by monitoring signal values sampled from the photodiode PD304 by non-destructive readout until threshold charge is generated in the photodiode PD304, at which time the generated image charge may then be read out by the transfer transistor 306, floating diffusion FD310, second amplifier transistor 312B, second row select transistor 314B, and column bit line 318.

Figure 4 is a diagram illustrating a layout of another exemplary image sensor pixel cell 402 with non-destructive readout included in a semiconductor chip according to the teachings of this disclosure. It should be appreciated that the image sensor pixel cell 402 illustrated in fig. 4 shares similarities with the pixel cell 102 shown in fig. 1, the pixel cell 202 shown in fig. 2, and/or the pixel cell 302 shown in fig. 3, and similarly named and numbered elements below are coupled and function as described above. As shown in the example, pixel cell 402 includes a photodiode 404 coupled to produce image charge in response to incident light 436. A deep trench isolation structure 416 is disposed proximate to the photodiode 404 to provide capacitive coupling to the photodiode 404 through the deep trench isolation structure 416.

The first amplifier transistor 412A is coupled to the deep trench isolation structure 416 to generate first amplified image data in response to image charge read out of the photodiode 404 through capacitive coupling provided by the deep trench isolation structure 416. In the depicted example, the first amplifier transistor 412A is a source follower coupled transistor, the gate terminal of which is coupled to the deep trench isolation structure 416. A first row select transistor 414A is coupled to the output of the first amplifier transistor 414A to selectively output first amplified image data to a column bit line 418 coupled to the first row select transistor 414A.

As shown in the depicted example, a floating diffusion FD410 is coupled to the second amplifier transistor 412B, and a transfer transistor 406 is coupled between the photodiode 404 and the floating diffusion FD410 to selectively couple the floating diffusion FD410 to the photodiode 404. A reset transistor 408 is coupled to the floating diffusion FD410 to selectively reset the charge in the floating diffusion FD410 and the photodiode 404. For example, in one example, the charge in the floating diffusion FD410 may be reset to a reset voltage by the reset transistor 408, and the charge in the photodiode 404 may be reset to a reset voltage by the reset transistor 408 and the transfer transistor 406. In one example, the pixel cell 402 further includes an optional reset connection 409, and the charge in the capacitive coupling provided by the deep trench isolation structure 416 can also be reset to a reset voltage by the reset transistor 408 through the optional reset connection 409.

In the example depicted in fig. 4, a conductive material 438 (e.g., polysilicon, etc.) is disposed within the deep trench isolation structure 416. In the example, the oxide material 428 lines the interior of the deep trench isolation structure 416. In one example, the oxide material 428 lining the interior of the deep trench isolation structure 416 is a charged oxide trench liner. For example, in one example, the oxide material 228 may be a negatively charged oxide trench liner, and in another example, the oxide material 228 may be a positively charged oxide liner. As such, it should be appreciated that in the illustrated example, the capacitance of the capacitive coupling to the photodiode 404 provided by the deep trench isolation structure 416 is suitably matched to sense the image charge accumulated in the photodiode 404 in accordance with the teachings of the present invention.

Figure 5 is a block diagram illustrating an example imaging system 500 including a pixel array with non-destructive readout of pixel cells according to the teachings of this disclosure. As shown in the depicted example, imaging system 500 includes a pixel array 502 coupled to control circuitry 532 and readout circuitry 530 (which is coupled to functional logic 534).

In one example, pixel array 502 is a two-dimensional (2D) array of image sensors or pixel cells (e.g., pixel cells P1, P2 …, Pn). In one example, each pixel cell is a CMOS imaging pixel. Note that pixel cells P1, P2, … Pn in pixel array 502 may be examples of pixel cell 102 of fig. 1, pixel cell 202 of fig. 2, pixel cell 302 of fig. 3, or pixel cell 402 of fig. 4, and similarly named and numbered elements mentioned below are coupled and function similarly as described above. As illustrated, each pixel cell is arranged into one row (e.g., row R1-Ry) and one column (e.g., column C1-Cx) to acquire image data of a person, place, object, etc., which can then be used to render a 2D image of the person, place, object, etc.

In one example, after each pixel cell has accumulated its image data or image charge, the image data is readout by readout circuitry 530 via column bit lines 518 and then transferred to function logic 534. In various examples, readout circuitry 530 may also include additional amplification circuitry, additional analog-to-digital (ADC) conversion circuitry, or others. The function logic 534 may simply store the image data or even manipulate the image data by applying post-image effects (e.g., crop, rotate, remove red eye, adjust brightness, adjust contrast, or otherwise). In one example, readout circuitry 530 may readout a row of image data at a time along readout column bit lines 518 (illustrated) or may readout the image data using a variety of other techniques (not illustrated), such as serial readout or readout of all pixels in full parallel at the same time.

In one example, control circuitry 532 is coupled to pixel array 502 to control operating characteristics of pixel array 502. For example, the control circuit 532 may generate a shutter signal for controlling image acquisition. In one example, the shutter signal is a global shutter signal for simultaneously enabling all pixels within the pixel array 502 to simultaneously capture their respective image data during a single acquisition window. In another example, the shutter signal is a rolling shutter signal such that each row of pixels, each column of pixels, or each group of pixels is sequentially enabled during successive acquisition windows.

The above description of illustrated examples of the invention, including what is described in the summary, is not intended to be exhaustive or to be limited to the precise forms disclosed. While specific embodiments of, and examples for, the invention are described herein for illustrative purposes, various equivalent modifications can be made without departing from the broader spirit and scope of the invention.

These modifications can be made to the examples of the invention in light of the above detailed description. The terms used in the following claims should not be construed to limit the invention to the specific embodiments disclosed in the specification and the claims. Rather, the scope is to be determined entirely by the following claims, which are to be construed in accordance with established doctrines of claim interpretation. The specification and drawings are, accordingly, to be regarded in an illustrative rather than a restrictive sense.

Claims

1. A pixel cell, comprising:

a photodiode coupled to produce image charge in response to incident light;

a deep trench isolation structure disposed proximate to the photodiode to provide capacitive coupling to the photodiode through the deep trench isolation structure;

an amplifier transistor coupled to the deep trench isolation structure to generate amplified image data in response to the image charge read out of the photodiode through the capacitive coupling provided by the deep trench isolation structure; and

a row select transistor coupled to an output of the amplifier transistor to selectively output the amplified image data to a column bit line coupled to the row select transistor.

2. The pixel cell of claim 1, further comprising:

a floating diffusion coupled to the amplifier transistor;

a transfer transistor coupled between the photodiode and the floating diffusion to selectively couple the floating diffusion to the photodiode; and

a reset transistor coupled to the floating diffusion to selectively reset charge in the floating diffusion and the photodiode.

3. The pixel cell of claim 2, further comprising a switching transistor coupled between the deep trench isolation structure and the floating diffusion, wherein the amplifier transistor and the reset transistor are selectively coupled to the deep trench isolation structure by the switching transistor.

4. The pixel cell of claim 2, wherein the amplifier transistor is a first amplifier transistor, wherein the row select transistor is a first row select transistor, and wherein the amplified image data selectively output by the first row select transistor is first amplified image data, the pixel cell further comprising:

a second amplifier transistor coupled to the floating diffusion to generate second amplified image data in response to the image charge read out of the photodiode through the floating diffusion; and

a second row select transistor coupled to an output of the second amplifier transistor to selectively output the second amplified image data to the column bit line coupled to the second row select transistor.

5. The pixel cell of claim 4, wherein the reset transistor is further coupled to the deep trench isolation structure to selectively reset charge in the deep trench isolation structure.

6. The pixel cell of claim 1, further comprising:

a conductive material disposed within the deep trench isolation structure; and

an oxide material lining an interior of the deep trench isolation structure.

7. The pixel cell of claim 6, wherein said conductive material comprises polysilicon.

8. The pixel cell of claim 7, wherein the oxide material is a charged oxide trench liner.

9. An imaging system, comprising:

a pixel array comprising a plurality of pixel cells, wherein each of the pixel cells comprises:

a photodiode coupled to produce image charge in response to incident light;

a row select transistor coupled to an output of the amplifier transistor to selectively output the amplified image data to a column bit line coupled to the row select transistor;

control circuitry coupled to the pixel array to control operation of the pixel array; and

readout circuitry coupled to the pixel array to readout the amplified image data from each of the plurality of pixel cells of the pixel array.

10. The imaging system of claim 9, further comprising functional logic coupled to the readout circuitry to store the amplified image data read out of the pixel array.

11. The imaging system of claim 9, wherein each of the pixel cells further comprises:

a floating diffusion coupled to the amplifier transistor;

12. The imaging system of claim 11, wherein each of the pixel cells further comprises a switching transistor coupled between the deep trench isolation structure and the floating diffusion, wherein the amplifier transistor and the reset transistor are selectively coupled to the deep trench isolation structure by the switching transistor.

13. The imaging system of claim 11, wherein the amplifier transistor is a first amplifier transistor, wherein the row select transistor is a first row select transistor, and wherein the amplified image data selectively output by the first row select transistor is first amplified image data, wherein each of the pixel cells further comprises:

14. The imaging system of claim 13, wherein the reset transistor is further coupled to the deep trench isolation structure to selectively reset charge in the deep trench isolation structure.

15. The imaging system of claim 9, wherein each of the pixel cells further comprises:

a conductive material disposed within the deep trench isolation structure; and

an oxide material lining an interior of the deep trench isolation structure.

16. The imaging system of claim 15, wherein the conductive material comprises polysilicon.

17. The imaging system of claim 16, wherein the oxide material is a charged oxide trench liner.