HK1180111A - One-time programmable device having an ldmos structure and related method - Google Patents

Abstract

The invention discloses a one-time programmable device having an LDMOS structure and related method. According to one embodiment, a one-time programmable (OTP) device having a lateral diffused metal-oxide-semiconductor (LDMOS) structure comprises a pass gate including a pass gate electrode and a pass gate dielectric, and a programming gate including a programming gate electrode and a programming gate dielectric. The programming gate is spaced from the pass gate by a drain extension region of the LDMOS structure. The LDMOS structure provides protection for the pass gate when a programming voltage for rupturing the programming gate dielectric is applied to the programming gate electrode. A method for producing such an OTP device comprises forming a drain extension region, fabricating a pass gate over a first portion of the drain extension region, and fabricating a programming gate over a second portion of the drain extension region.

Description

One-time programmable device having LDMOS structure and related method

Technical Field

The present invention is generally in the field of semiconductors. More specifically, the present invention is in the field of one-time programmable semiconductor devices.

Background

One-time programmable (OTP) devices are used throughout the semiconductor industry to enable post-fabrication design changes in Integrated Circuits (ICs). For example, after post-manufacturing functionality testing but before sale to a consumer, a semiconductor device manufacturer may program a set (a network) of OTP devices embedded in a particular semiconductor die to provide a permanent serial number encoding such particular die. In other cases, a single OTP device may be programmed to make a portion of the integrated circuit permanently usable or unusable at any time after manufacture, including after sale to a consumer (user). Although this functionality is very demanding, for example, conventional OTP elements (programmable components of OTP devices) may be larger than desired or may require multiple additional fabrication steps in addition to those required for conventional transistor fabrication, making conventional OTP devices expensive to fabricate and embed.

One such conventional embedded OTP device can be fabricated using a so-called split-channel (split-channel) method, in which an atypical Metal Oxide Semiconductor Field Effect Transistor (MOSFET) fabrication method is used to form a gate structure that includes a single channel interface having two different gate dielectric thicknesses. A thin portion of the gate dielectric (OTP element) can be destructively damaged and a conductive path is formed from the gate to the channel, thereby switching the conventional OTP device to a "programmed" state. However, this approach has a relatively high tendency to obtain devices with a programmed state, where the remaining thick gate structure exhibits a relatively high leakage current due to collateral damage during programming. In addition, this approach tends to cause devices with a relatively poorly differentiated combination of programmed and unprogrammed states (as seen by the sensing circuit) and high leakage current statistics to require relatively high voltage sensing circuits to reliably read the programmed and unprogrammed states. Mitigation of these drawbacks may require additional die (chip) space for high voltage sensing circuits and/or for redundant technologies that may involve, for example, an undesirable increase in manufacturing costs.

Accordingly, there is a need to address the shortcomings and drawbacks in the art by providing reliable OTP devices that are both robust to damage during programming and can be fabricated using existing MOSFET fabrication method steps.

Disclosure of Invention

A One Time Programmable (OTP) device having a Laterally Diffused Metal Oxide Semiconductor (LDMOS) structure and related methods are substantially shown in and/or described with reference to at least one of the figures and are explained more fully in the following description.

In one aspect, the present invention provides a one-time programmable (OTP) device having a Laterally Diffused Metal Oxide Semiconductor (LDMOS) structure, the OTP device comprising:

a transfer gate comprising a transfer gate electrode and a transfer gate dielectric;

a program gate comprising a program gate electrode and a program gate dielectric, the program gate being isolated from the pass gate by a drain extension region of the LDMOS structure;

the LDMOS structure provides protection to the pass gate when a programming voltage for rupturing the programming gate dielectric is applied to the programming gate.

Preferably, the OTP device according to the present invention wherein said transfer gate and said programming gate are fabricated simultaneously.

Preferably, the OTP device according to the present invention wherein said transfer gate dielectric and said programming gate dielectric comprise the same dielectric material.

Preferably, the OTP device according to the present invention wherein said program gate and said transfer gate comprise the same conductive material.

Preferably, the OTP device according to the present invention wherein said program gate forms a schottky contact with said drain extension region after said program voltage is applied.

Preferably, the OTP device according to the present invention is an n-channel metal oxide semiconductor (NMOS) device.

Preferably, the OTP device according to the present invention is a p-channel metal oxide semiconductor (PMOS) device.

Preferably, the OTP device according to the present invention wherein said program gate is formed of a gate metal and said program gate dielectric comprises a high- κ dielectric.

Preferably, the OTP device according to the present invention further includes an isolation body between the transfer gate and the program gate.

Preferably, the OTP device according to the present invention, wherein the isolation body comprises Shallow Trench Isolation (STI).

In another aspect, the present invention also provides a method for fabricating a metal oxide semiconductor (LDMOS) structure having lateral diffusion, the method comprising:

forming a drain extension region of the LDMOS structure;

fabricating a transfer gate comprising a transfer gate electrode and a transfer gate dielectric over a first portion of the drain extension region;

fabricating a program gate comprising a program gate and a program gate dielectric over a second portion of the drain extension region;

the LDMOS device structure provides protection to the pass gate when a programming voltage for rupturing the programming gate dielectric is applied to the programming gate.

Preferably, the method according to the present invention, wherein said transfer gate and said programming gate are fabricated simultaneously.

Preferably, the method according to the present invention, wherein said transfer gate dielectric and said programming gate dielectric are formed of the same dielectric material.

Preferably, the method according to the present invention, wherein the program gate and the transfer gate are formed of the same conductive material.

Preferably, the method according to the present invention, wherein after applying said programming voltage, said program gate is configured to form a schottky contact with said drain extension region.

Preferably, the method according to the present invention, wherein said program gate is formed of a gate metal and said program gate dielectric comprises a high- κ dielectric.

Preferably, the method according to the present invention, wherein said OTP device is an n-channel metal oxide semiconductor (NMOS) device.

Preferably, the method according to the present invention, wherein said OTP device is a p-channel metal oxide semiconductor (PMOS) device.

Preferably, the method according to the present invention further comprises forming an isolation body between the transfer gate and the program gate.

Preferably, a method according to the present invention, wherein forming the isolation body between the transfer gate and the program gate comprises forming a Shallow Trench Isolation (STI) between the transfer gate and the program gate.

Drawings

Fig. 1 illustrates a one-time programmable (OTP) device having a Laterally Diffused Metal Oxide Semiconductor (LDMOS) structure prior to programming according to one embodiment of the invention.

Fig. 2 is a flowchart illustrating a method of fabricating an OTP device having an LDMOS structure according to one embodiment of the present invention.

FIG. 3 illustrates the OTP device of FIG. 1 after application of a programming voltage in accordance with one embodiment of the invention.

Fig. 4 shows an OTP device having an LDMOS structure according to another embodiment of the present invention.

Detailed Description

The present invention relates to one-time programmable (OTP) devices having Laterally Diffused Metal Oxide Semiconductor (LDMOS) structures and related methods. The following description contains specific information pertaining to the implementation of the present invention. It will be appreciated by those skilled in the art that the present invention may be practiced otherwise than as specifically disclosed herein. Furthermore, some of the specific details of the invention are not discussed in order to avoid obscuring the invention.

The drawings in the present application and their accompanying detailed description are directed to merely exemplary embodiments of the invention. In the interest of brevity, other embodiments of the present invention are not specifically described in the present application and are not specifically illustrated by the present drawings. It should be understood that, unless otherwise specified, identical or corresponding elements in the figures may be indicated by identical or corresponding reference numerals. Moreover, the drawings and illustrations in this application are generally not to scale and are not intended to correspond to actual relative dimensions.

Fig. 1 illustrates a cross-sectional view of an OTP device 100 having an LDMOS structure 101 according to an embodiment of the invention, which OTP device 100 is capable of addressing the drawbacks and deficiencies associated with the prior art. The OTP device 100, represented in fig. 1 as an n-channel metal oxide semiconductor (NMOS) device, may be fabricated in a P-type semiconductor body 102, which P-type semiconductor body 102 may include, for example, a group IV semiconductor wafer (wafer) or die (chip), such as a portion of a wafer or die including silicon or germanium. The semiconductor body 102 may include an N-type drain extension region 104, a heavily doped N + drain region 106, and a heavily doped N + source region 108. As shown in fig. 1, OTP device 100 may include a transfer gate 120 including a transfer gate 122 and a transfer gate dielectric 124, and a program gate 130 including a program gate 132 and a program gate dielectric 134. As further shown in fig. 1, a transfer gate 120 is formed over the channel region 110 of the semiconductor body, and a program gate 130 is spaced from the transfer gate 120 by a portion of the drain extension 104. Also shown in fig. 1 are a bit line contact 116 formed over heavily doped source region 108 and a word line contact 126 formed over transfer gate 120.

Due at least in part to the employment of LDMOS structure 101, OTP device 100 is constructed to have enhanced programming reliability while providing protection to pass gate 120 when a programming voltage is applied to program gate 132 for rupturing program gate dielectric 134. In addition, the program gate 130 may be fabricated using a high- κ metal gate method such that after programming, a Schottky contact (Schottky contact) is formed between the program gate 132 and the drain extension region 104, thereby enabling better conduction in a forward biased state. Moreover, because the fabrication of OTP device 100 may be performed using processing steps currently included in many Complementary Metal Oxide Semiconductor (CMOS) casting process flows, such as high- κ metal gate CMOS process flows, OTP device 100 may be fabricated with conventional CMOS devices, for example, and may be integrated in CMOS logic cells, for example, in an Integrated Circuit (IC) fabricated on a semiconductor wafer or die (chip).

It should be noted that the specific features shown in fig. 1 are provided as part of an exemplary implementation of the principles of the present invention and are shown with such features to help clarify the concept. Because of the emphasis on conceptual clarity, it is reiterated that the structures and features depicted in FIG. 1, as well as in FIGS. 2 and 4, are not drawn to scale. Furthermore, it should be noted that specific details attributed to its features, such as the kind of semiconductor device represented by OTP device 100, its overall layout, its channel conductivity type, and specific dimensions, are provided as examples only and should not be construed as limiting. For example, although the embodiment shown in FIG. 1 characterizes OTP device 100 as an NMOS device, more generally an OTP device in accordance with the principles of the invention may include an n-channel or p-channel MOSFET and thus may be implemented as a PMOS device, and in FIG. 1 an example NMOS device is specifically shown as OTP device 100.

Some features and advantages of OTP device 100 with LDMOS structure 101 will be further described in conjunction with fig. 2 and 3. Fig. 2 shows a flow chart 200 representing one embodiment of a method for fabricating an OTP device having an LDMOS structure, and fig. 3 shows an OTP device 300 corresponding to OTP device 100 of fig. 1 after programming according to one embodiment of the invention. With respect to the flowchart 200 in fig. 2, it should be noted that certain details and features of the flowchart 200 that are apparent to a person skilled in the art have been omitted. For example, a step may comprise one or more substeps or may involve specialized equipment or materials, as known in the art. While steps 210 through 240 shown in flowchart 200 are sufficient to describe one embodiment of the present invention, other embodiments of the invention may utilize different steps than those shown in flowchart 200, or may include more or fewer steps.

Referring to step 210 in fig. 2 and OTP device 100 in fig. 1, step 210 of flowchart 200 includes forming drain extension region 104 of LDMOS structure 101. In one embodiment, step 210 may correspond to implanting the drain extension region 104 by performing a retrograde implant (retrogradation implant) of dopants into the semiconductor body 102. As previously described, in some embodiments, the fabrication method of flowchart 200 may be implemented using existing CMOS fabrication process flows. For example, in one embodiment, the OTP device 100 with the LDMOS structure 101 can be fabricated on a wafer while undergoing CMOS logic fabrication. Thus, in such an embodiment, step 210 may correspond to implanting the drain extension region by performing one of a Core Well implant or IO Well implant procedure, as is known in the art.

Turning to step 220 in fig. 2 and with continued reference to OTP device 100 in fig. 1, step 220 of flowchart 200 includes fabricating a transfer gate 120 that includes a transfer gate dielectric 124 and a transfer gate 122 over a first portion of a drain extension 104. As shown in fig. 1, a transfer gate 120, including a transfer gate 122 and a transfer gate dielectric 124, is located over the channel region 110 and a first portion of the drain extension region 104 disposed between the channel region 110 and the heavily doped drain region 106. The transfer gate dielectric 124 can be, for example, a high dielectric constant (high- κ) gate dielectric layer (e.g., a high- κ dielectric layer that can be used to form an NMOS or PMOS gate dielectric). In such an embodiment, the high- κ transfer gate dielectric 124 may comprise, for example, a metal oxide such as hafnium oxide (HfO)₂) Zirconium oxide (ZrO)₂) And the like. When implemented as a high- κ dielectric, the transfer gate dielectric 124 may be formed, for example, by: high- κ dielectric material, such as HfO, is deposited on semiconductor body 102 by using, for example, a Physical Vapor Deposition (PVD) process, a Chemical Vapor Deposition (CVD) process, or other suitable process, such as Atomic Layer Deposition (ALD) or Molecular Beam Epitaxy (MBE)₂Or ZrO₂。

The transfer gate 122 may include a gate metal. For example, in embodiments where OTP device 100 is implemented as an NMOS device as shown in fig. 1, transfer gate 122 may be formed of any gate metal suitable for use in an NMOS device, such as, for example, tantalum (Ta), tantalum nitride (TaN), or titanium nitride (TiN). Also, in embodiments where OTP device 100 is implemented as a PMOS device, transfer gate 122 may be formed of any gate metal suitable for use in a PMOS device, such as, for example, molybdenum (Mo), ruthenium (Ru), or tantalum carbon nitride (TaCN). The gate metal disposed over the transfer gate dielectric 124 to fabricate the transfer gate 122 may be fabricated using any of PVD, CVD, ALD, or MBE, for example.

Continuing to step 230 in fig. 2, step 230 of flowchart 200 includes fabricating a programming gate 130, the programming gate 130 including a programming gate 132 and a programming gate dielectric 134 over a second portion of the drain extension region 104. As shown in fig. 1, the program gate 130, including the program gate 132 and the program gate dielectric 134, does not abut the transfer gate 120, but is adjacent to the transfer gate 120 over a second portion of the drain extension region 104 spaced apart from the first portion of the drain extension region 104 over which the transfer gate 120 is disposed.

According to one embodiment, transfer gate 120 and program gate 130 may be fabricated substantially simultaneously. That is, steps 220 and 230 of flowchart 200 may be performed simultaneously. Also, the transfer gate 120 and the program gate 130 may be formed using substantially the same material. In other words, the transfer gate dielectric 124 and the program gate dielectric 134 can comprise the same dielectric material, such as the same high- κ dielectric material, while the transfer gate 122 and the program gate 132 can comprise the same conductive material, such as the same gate metal. Thus, as in the case of the transfer gate 120 fabricated in step 220, the fabrication of the programming gate 130 may use a high- κ dielectric as the programming gate dielectric 134, such as HfO₂Or ZrO₂And a metal gate comprising, for example, Ta, TaN, TiN, Mo, Ru, or TaCN may be used to implement program gate 132. Moreover, as with transfer gate 120, any suitable method may be used for programming gate 130Methods such as, for example, PVD, CVD, ALD, or MBE formation.

Turning to step 240 in fig. 2, step 240 of flowchart 200 includes applying a program voltage to program gate 132 to rupture program gate dielectric 134. The result of performing step 240 of flowchart 200 on OTP device 100 in fig. 1 is shown in fig. 3, which fig. 3 illustrates a cross-sectional view of OTP device 300 having LDMOS structure 301.

OTP device 300 is shown to include an N-type drain extension region 304, a heavily doped N + drain region 306, a heavily doped N + source region 308, and a channel region 310 in a P-type semiconductor body 302. As shown in fig. 3, OTP device 300 further includes a transfer gate 320 and a program gate 350, the transfer gate 320 including a transfer gate 322 and a transfer gate dielectric 324, and the program gate 330 including a program gate 332 and a program gate dielectric 334. OTP device 300 formed in semiconductor body 302 and including transfer gate 320 and program gate 330 corresponds to OTP device 100 formed in semiconductor body 102 and including transfer gate 120 and program gate 130 in fig. 1 after application of a program voltage to program gate 132, as shown by rupture 336 in fig. 3 through program gate dielectric 334. Also shown in fig. 3 are a bit line contact 316 and a word line contact 326, which correspond to the bit line contact 116 and the word line contact 126, respectively, of fig. 1.

Step 240 of flowchart 200 may be performed by, for example, applying a relatively high voltage, such as about a 5V programming voltage, to programming gate 332 to create one or more pinhole-type breaks 336 in programming gate dielectric 334. In embodiments in which program gate 332 is formed of a gate metal, such as those discussed above, step 240 results in program gate 332 forming a schottky contact with drain extension region 304. However, due to the relative voltage separation of the pass gate 320 from the program gate 330 caused by the LDMOS structure 301, the pass gate dielectric 324 will remain substantially unaffected by the application of the programming voltage that causes a pinhole-type rupture 336 through the program gate dielectric 334.

Referring now to fig. 4, fig. 4 illustrates a cross-sectional view of an OTP device 400 having an LDMOS structure 401 in accordance with another embodiment of the invention. OTP device 400 includes an N-type drain extension region 404, a heavily doped N + source region 408 and a channel region 410 in a P-type semiconductor body 402. As shown in fig. 4, OTP device 400 further includes a transfer gate 420 and a program gate 430, the transfer gate 420 including a transfer gate 422 and a transfer gate dielectric 424, and the program gate 430 including a program gate 432 and a program gate dielectric 434, a pinhole-type rupture 436 being formed through the program gate dielectric 434. OTP device 400 formed in semiconductor body 402 and including transfer gate 420 and programming gate 430 including break 436 corresponds to OTP device 300 formed in semiconductor body 302 and including transfer gate 320 and programming gate 330 including break 336 in fig. 3. As can be further seen in fig. 4, when the program gate 430 is fabricated using the high- κ metal gate method, the rupture 436 through the program gate dielectric 434 causes the N-type drain extension 404 to be in schottky contact with the program gate 432. In addition, fig. 4 shows a bit line contact 416 and a word line contact 426, which correspond to the bit line contact 316 and the word line contact 326, respectively, in fig. 3.

Also shown in fig. 4 is the isolation body 418 between the transfer gate 420 and the program gate 430, without the analogs in the previous figures. The isolation body 418 may include a Shallow Trench Isolation (STI) structure such as, for example, formed of silicon dioxide (SiO)₂) STI structures are formed and may be formed according to known CMOS fabrication process steps. According to the embodiment shown in fig. 4, the isolation body 418 may be implemented as part of the LDMOS structure 401 to provide additional protection to the pass gate 420 when a programming voltage for fabricating the rupture 436 is applied to the program gate 432.

The structure and method according to the invention thus allow several advantages with respect to the conventional art. For example, by employing an LDMOS structure, embodiments of the OTP devices disclosed herein are configured to withstand higher programming voltages than would otherwise be the case, thereby making programming more reliable while advantageously providing enhanced protection for the pass gate portion of the OTP device. In addition, the program gate of the disclosed embodiments of the OTP device can be fabricated using a high- κ metal gate method, such that after programming, a schottky contact is formed between the program gate and the drain region of the OTP device, thereby enabling better conduction in a forward-biased state. Moreover, the advantages associated with this approach can be achieved using existing high- κ metal gate CMOS process flows, thereby making the integration of high voltage devices with CMOS cores (CMOS core) and IO devices on common ICs efficient and economical. As a result, the present invention increases design flexibility without adding cost or complexity to the established semiconductor device fabrication process.

It will be apparent from the above description of the invention that various techniques can be used to implement the concepts of the invention without departing from its scope. Moreover, although the present invention has been described with reference to particular embodiments, workers skilled in the art will recognize that changes may be made in form and detail without departing from the spirit and scope of the invention. The described embodiments are, therefore, to be considered in all respects as illustrative and not restrictive. It should also be understood that the invention is not limited to the particular embodiments described herein, but is capable of many rearrangements, modifications, and substitutions without departing from the scope of the invention.

Claims (10)

1. A one-time programmable (OTP) device having a Laterally Diffused Metal Oxide Semiconductor (LDMOS) structure, the OTP device comprising:

a transfer gate comprising a transfer gate electrode and a transfer gate dielectric;

a program gate comprising a program gate electrode and a program gate dielectric, the program gate being isolated from the pass gate by a drain extension region of the LDMOS structure;

the LDMOS structure provides protection to the pass gate when a programming voltage for rupturing the programming gate dielectric is applied to the programming gate.

2. The OTP device of claim 1 wherein said program gate forms a schottky contact with said drain extension region after application of said program voltage.

3. The OTP device of claim 1, wherein the OTP device is an n-channel metal oxide semiconductor (NMOS) device.

4. The OTP device of claim 1, wherein the OTP device is a p-channel metal oxide semiconductor (PMOS) device.

5. The OTP device of claim 1 wherein said program gate is formed of a gate metal and said program gate dielectric comprises a high- κ dielectric.

6. The OTP device of claim 1 further comprising an isolation body between said transfer gate and said program gate.

7. The OTP device of claim 9 wherein said isolation body comprises Shallow Trench Isolation (STI).

8. A method for fabricating a metal oxide semiconductor (LDMOS) structure having lateral diffusion, the method comprising:

forming a drain extension region of the LDMOS structure;

fabricating a transfer gate comprising a transfer gate electrode and a transfer gate dielectric over a first portion of the drain extension region;

fabricating a program gate comprising a program gate and a program gate dielectric over a second portion of the drain extension region;

the LDMOS device structure provides protection to the pass gate when a programming voltage for rupturing the programming gate dielectric is applied to the programming gate.

9. The method of claim 11, wherein after applying the programming voltage, the program gate is configured to form a schottky contact with the drain extension region.

10. The method of claim 11 wherein the program gate is formed of a gate metal and the program gate dielectric comprises a high- κ dielectric.