HK1175888B - Wrap-around contacts for finfet and tri-gate devices - Google Patents

Description

Wrap-around contacts for fin FETs and tri-gate devices

Background

In conventional fin FET and tri-gate transistor devices, the contact area of the source and drain regions, i.e., the top of the source and drain regions, is constant as the fin height increases, thus as the fin height increases, the drive current increase or decrease is not optimal due to the small contact interface area. Thus, the area on top of the source and drain regions of conventional fin FET and tri-gate transistor devices remains substantially constant as the fin height increases.

Drawings

The embodiments disclosed herein are illustrated by way of example, and not by way of limitation, in the figures of the accompanying drawings and in which like reference numerals refer to similar elements and in which:

fig. 1 illustrates an exemplary fin FET or tri-gate transistor 100 in accordance with the subject matter disclosed herein;

FIGS. 2A-2I illustrate a sequence of process steps for forming a contact structure according to the subject matter disclosed herein; and

figure 3 shows a process flow corresponding to the sequence of process steps shown in figures 2A-2I.

It will be appreciated that for simplicity and/or illustrative clarity, elements shown in the figures have not necessarily been drawn to scale. For example, the dimensions of some of the elements may be exaggerated relative to other elements for clarity. Further, where considered appropriate, reference numerals have been repeated among the figures to indicate corresponding and/or analogous elements.

Detailed Description

Embodiments of contact structures for fin FETs and tri-gate devices are described herein. In the following description, numerous specific details are set forth in order to provide a thorough understanding of the embodiments disclosed herein. One skilled in the relevant art will recognize, however, that the embodiments disclosed herein can be practiced without one or more of the specific details, or with other methods, components, materials, and so forth. In other instances, well-known structures, materials, or operations are not shown or described in detail to avoid obscuring aspects of the description.

Reference throughout this specification to "one embodiment" or "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment. Thus, the appearances of the phrases "in one embodiment" or "in an embodiment" in various places throughout this specification are not necessarily all referring to the same embodiment. Furthermore, the particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. The word "exemplary" is used herein to mean "serving as an example, instance, or illustration. Any embodiment described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other embodiments.

The subject matter disclosed herein relates to contact structures for fin FET or tri-gate transistor devices that utilize a wrap-around structure such that the contact area advantageously increases and decreases as the fin height increases. That is, according to the subject matter disclosed herein, the contact area increases proportionally with increasing fin height.

Fig. 1 illustrates an exemplary fin FET or tri-gate transistor 100 in accordance with the subject matter disclosed herein. A tri-gate transistor 100 is formed on a substrate 101. In an exemplary embodiment, the substrate 101 is an insulating substrate comprising an underlying monocrystalline silicon substrate 102, an insulating layer 103, such as a silicon dioxide film, being formed on the monocrystalline silicon substrate 102. However, tri-gate transistor 100 may be formed on any insulating substrate, such as a substrate formed of silicon dioxide, nitride, oxide, or sapphire. In an exemplary embodiment, the substrate 101 may be a semiconductor substrate, such as, but not limited to, a monocrystalline silicon substrate or a gallium arsenide substrate. In yet another exemplary embodiment, the substrate 101 may be a bulk structure formed entirely of, for example, silicon.

The tri-gate transistor 100 includes a semiconductor body 104 formed on an insulator 103 of an insulating substrate 101. The semiconductor body 104 may be formed of any semiconductor material, such as, but not limited to, silicon, germanium, a silicon-germanium alloy, gallium arsenide, indium antimonide, gallium phosphide, gallium antimonide, or carbon nanotubes. The semiconductor body 104 may be formed of any material that can be reversibly changed from an insulating state to a conductive state by applying external electrical control. In one exemplary embodiment, semiconductor body 104 is desirably a single crystal film when optimal electrical performance of transistor 100 is desired. For example, when the transistor 100 is used in high performance applications, such as in high density circuits (e.g., microprocessors), the semiconductor body 104 is a single crystalline film. However, semiconductor body 104 may be a polycrystalline film when transistor 100 is used in less performance demanding applications, such as in a liquid crystal display. The insulator 103 insulates the semiconductor body 104 from the monocrystalline silicon substrate 101. In an exemplary embodiment, the semiconductor body 104 comprises a single crystalline silicon film. The semiconductor body 104 includes a pair of laterally opposite sidewalls 105 and 106, the sidewalls being separated by a distance that defines the width of the semiconductor body 104. Furthermore, the semiconductor body 104 includes a top surface 107, the top surface 107 being opposite a bottom surface (not shown) formed on the substrate 101. The distance between the top surface 107 and the bottom surface (not shown) defines the body height. In one exemplary embodiment, the body height is substantially equal to the body width. In another exemplary embodiment, the width and height of the semiconductor body 104 is less than about 30 nanometers, and desirably less than about 20 nanometers. In yet another exemplary embodiment, the body height is between about half the body width to twice the body width.

Tri-gate transistor 100 also includes a gate dielectric layer (not shown) formed on and around three sides of semiconductor body 104. A gate dielectric layer is formed on or adjacent to the sidewalls 105, on the top surface 107, on or adjacent to the sidewalls 106 of the body 104. The gate dielectric layer may be formed of any gate dielectric material. In one exemplary embodiment, the gate dielectric layer comprises a silicon dioxide, silicon oxynitride or silicon nitride dielectric layer. In another exemplary embodiment, a gateThe gate dielectric layer comprises a dielectric material formed to a thickness of between aboutAnd aboutWith a silicon oxynitride film in between. In yet another exemplary embodiment, the gate dielectric layer is a Hi-K gate dielectric layer, such as a metal oxide dielectric, such as, but not limited to, tantalum pentoxide, tantalum oxide, hafnium silicon dioxide, lanthanum oxide, lanthanum aluminum oxide, zirconium silicon oxide, tantalum oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, lead zinc niobate, and lead zirconate titanate (PZT).

The tri-gate device 100 further comprises a gate electrode 109. A gate electrode 109 is formed on and around the gate dielectric layer. That is, the gate electrode 109 is formed on or adjacent to the gate dielectric on three sides of the semiconductor body 104 on which the gate dielectric is formed. The gate electrode 109 has a pair of laterally opposite sidewalls 110 and 111 separated by a distance that defines a gate length Lg of the transistor 100. In an exemplary embodiment, laterally opposite sidewalls 110 and 111 of the gate electrode 109 extend in a direction substantially perpendicular to the laterally opposite sidewalls 105 and 106 of the semiconductor body 104.

Gate electrode 109 can be formed from any suitable gate electrode material in one exemplary embodiment, gate electrode 109 comprises a material doped to about 1 × 10¹⁹Atom/cm³And about 1 × 10²⁰Atom/cm³Polysilicon of intermediate concentration density. In another exemplary embodiment, the gate electrode 109 may be a metal gate electrode such as, but not limited to, tungsten, tantalum, titanium, hafnium, zirconium, aluminum, ruthenium, palladium, platinum, cobalt, nickel, and carbides and nitrides thereof. In an exemplary embodiment, the gate electrode 109 is formed of a material having a medium gap work function between about 4.6eV and about 4.8 eV. It should also be appreciated that the gate electrode 109 need not necessarily be a single material, but may comprise a composite stack of thin filmsSuch as, but not limited to, a polysilicon/metal electrode or a metal/polysilicon electrode.

Tri-gate transistor 100 also includes a source region 120 and a drain region 130. As shown in FIG. 1, a source region 112 and a drain region 113 are formed in semiconductor body 104 on opposite sides of gate electrode 109. Source region 112 and drain region 113 are formed of the same conductivity type, e.g., N-type or P-type¹⁹Atom/cm³And about 1 × 10²¹Atom/cm³With the doping concentration in between. The source region 112 and the drain region 113 may be formed of uniform concentration or may include sub-regions of different concentrations or doping profiles, such as tip regions (e.g., source/drain extension regions). In one exemplary embodiment, when the transistor 100 is a symmetric transistor, the source region 112 and the drain region 113 will include the same doping concentration and profile. In another exemplary embodiment, when the tri-gate transistor 100 is formed as an asymmetric transistor, then the doping concentration and profile of the source region 112 and the drain region 113 may be varied to obtain specific electrical characteristics. In another exemplary embodiment, the source and drain regions 112 and 113 include a semiconductor film 115 formed on exposed surfaces of the semiconductor body 104 to form source and drain contact regions. In another exemplary embodiment, the film 115 is grown after recess etching the fin in the source-drain regions, and the film 115 will be used to strain the channel. One example is strained silicon germanium SiGe. Another example is strained silicon carbide SiC.

The portion of the semiconductor body 104 located between the source region 112 and the drain region 113 defines a channel region (not shown) of the transistor 100. The channel region may also be defined as the region of the semiconductor body 104 which is surrounded by the gate electrode 109. Sometimes, however, the source/drain regions may extend slightly below the gate electrode, such as by diffusion, to define a channel region that is slightly less than the gate electrode length Lg. In an exemplary embodiment, the channel region comprises intrinsic or undoped monocrystalline silicon. In one exemplary embodiment, the channel region comprises doped monocrystalline silicon. When the channel region is doped, it is typically doped to between about1×10¹⁶Atom/cm³To about 1 × 10¹⁹Atom/cm³The conductivity level between. In an exemplary embodiment, when the channel region is doped, the channel region is typically doped to an opposite conductivity type as the source region 112 and the drain region 113. For example, where the source and drain regions are N-type conductivity, the channel region will be doped to P-type conductivity. Similarly, where the source and drain regions are of P-type conductivity, the channel region will be doped to N-type conductivity. In this way, the tri-gate transistor 100 may be formed as an NMOS transistor or a PMOS transistor, respectively. The channel region may be uniformly doped or may be non-uniformly doped or doped at different concentrations to provide specific electrical and performance characteristics. For example, the channel region may include a "halo" region, if desired.

One exemplary embodiment of the transistor 100 includes sidewall spacers 114 formed on sidewalls of the gate electrode 109. In another exemplary embodiment, the source and drain regions 112 and 113 include a semiconductor film 115 formed on exposed surfaces of the semiconductor body 104 to form source and drain contact regions. In another exemplary embodiment, the film 115 is grown after recess etching the fin in the source-drain regions, and the film 115 will be used to strain the channel. One example is strained SiGe. Further, if necessary, a semiconductor film 116 may be formed on top of the gate electrode 109. Semiconductor film 116 can be a single crystalline film or a polycrystalline film. In one exemplary embodiment, semiconductor film 116 is an epitaxial (single crystal) silicon film. In another exemplary embodiment, the silicon film 115 is formed by a selective deposition process wherein silicon is formed only on exposed regions comprising silicon, such as on exposed top surfaces and sidewalls of the semiconductor body 104. Metal 117 is formed on the source and drain regions and on top of gate electrode 109. Metal 117 may be formed of, for example, titanium, tungsten, nickel, copper, or cobalt, or any other metal or silicide contact having a contact resistance equal to or better than NiSi. Metal 117 is formed on the source and drain regions to form source and drain contact regions such that the contact regions advantageously scale as the fin height increases. In an exemplary alternative embodiment, the silicide may be formed by reacting metal 117 with silicon or silicon germanium.

A method of fabricating a tri-gate transistor in accordance with an embodiment of the subject matter disclosed herein is illustrated in fig. 2A-2I. Fig. 3 is a flow chart summarizing the process shown in fig. 2A-2I for fabricating a tri-gate transistor. Fabrication of the tri-gate transistor begins with a substrate 201. In one exemplary embodiment, as shown in fig. 2A, a silicon or semiconductor film 202 is formed on a substrate 201. In another exemplary embodiment, the substrate 201 comprises an insulating substrate, such as an oxide-based substrate. In yet another exemplary embodiment, the insulating substrate 201 includes a bottom monocrystalline silicon substrate 203 and a top insulating layer 204, such as a silicon-dioxide film or a silicon-nitride film. The insulating layer 204 isolates the semiconductor film 202 from the substrate 203. In one exemplary embodiment, the insulating layer 204 is formed to have a thickness of aboutAnd aboutTo the thickness of (d) in between. Insulating layer 204 is sometimes referred to as a "buried oxide" layer. When a silicon or semiconductor film 202 is formed on an insulating substrate 201, a silicon or semiconductor-on-insulator (SOI) substrate 200 is produced. In other exemplary embodiments, the substrate 201 may be a semiconductor substrate, such as, but not limited to, a silicon single crystal substrate or a gallium arsenide substrate.

Although semiconductor film 202 is a silicon film in one exemplary embodiment, in other exemplary embodiments, semiconductor film 202 may be other types of semiconductor films such as, but not limited to, germanium, a silicon-germanium alloy, gallium arsenide, indium antimonide, gallium phosphide, gallium antimonide, or carbon nanotubes¹⁶Atom/cm³And about 1 × 10¹⁹Atom/cm³P-type or N-type conductivity. The semiconductor film 202 may be doped by, for example, ion implantation (i.e., doping while depositing the semiconductor film 202) or after forming the semiconductor film 202 on the substrate 201.Doping after formation enables easy fabrication of PMOS and NMOS tri-gate devices on the same insulating substrate. The doping level of the semiconductor body at this point in the fabrication process determines the doping level of the channel region of the device.

Semiconductor film 202 is formed to a thickness approximately equal to the desired height of the subsequently formed semiconductor body of the fabricated tri-gate transistor. In one exemplary embodiment, the thickness or height 205 of semiconductor film 202 is less than about 30 nanometers, and desirably less than about 20 nanometers. In another exemplary embodiment, semiconductor film 202 is formed to a thickness approximately equal to the gate "length" desired for the fabricated tri-gate transistor. In yet another exemplary embodiment, semiconductor film 202 is formed to be thicker than the desired gate length of the device. In yet another exemplary embodiment, semiconductor film 202 is formed to a thickness such that the fabricated tri-gate transistor can operate in a fully depleted manner for its designed gate length (Lg).

A semiconductor film 202 may be formed on the substrate 201. Step 301 in fig. 3 corresponds to this portion of fabricating a tri-gate transistor in accordance with an embodiment of the subject matter disclosed herein. In one exemplary technique for forming a silicon-on-insulator (SOI) substrate, commonly referred to as the SIMOX technique, oxygen atoms are implanted at a high dose into a single crystal silicon substrate and then annealed to form a buried oxide 204 within the substrate. The portion of the single crystal silicon substrate above the buried oxide 204 becomes the silicon film 202. Another exemplary technique for forming SOI substrates is the epitaxial silicon film transfer technique commonly referred to as bonded SOI. In the bonded SOI technology, a first silicon wafer is grown with a thin oxide on its surface, which will later serve as the buried oxide 204 in the SOI structure. Next, a high dose hydrogen implant is performed into the first silicon wafer to form a high stress region below the silicon surface of the first wafer. The first wafer is then flipped over and bonded to the surface of the second silicon wafer. The first wafer is then cleaved along a high stress plane created by the hydrogen implant to obtain an SOI structure comprising a thin silicon layer on top and a buried oxide all below on top of the single crystal silicon substrate. Smoothing techniques, such as HC smoothing or Chemical Mechanical Polishing (CMP), may be used to smooth the top surface of semiconductor film 202 to its desired thickness. In another exemplary alternative embodiment, the substrate 201 may be formed of a bulk material, such as silicon.

At this point in the fabrication process, isolation regions (not shown) may be formed in the SOI substrate 200, if desired, to isolate the various transistors to be formed therein from one another. Portions of the substrate film 202 surrounding the tri-gate transistor can be etched away, for example, by photolithography and etching techniques, and then using an insulating film, such as SiO₂And backfilling the etched region to form an isolation region.

To form a tri-gate transistor on substrate 200, a photoresist mask 206 is formed over semiconductor film 202, as shown in fig. 2B. Photoresist mask 206 includes a pattern or patterns that define the locations where one or more semiconductor bodies or fins are next formed in semiconductor film 202. The photoresist mask 206 may be formed by photolithographic techniques including masking, exposing, and developing a blanket deposited photoresist film. The photoresist pattern defines the desired width of the subsequently formed semiconductor body or fin in the tri-gate transistor. In one exemplary embodiment, the pattern defines fins or bodies having a width equal to or greater than the desired width of the gate length Lg of the transistor being fabricated. Thus, the most stringent lithographic constraints for fabricating transistors are related to gate electrode patterning, not semiconductor body or fin definition. In one exemplary embodiment, the semiconductor body or fin will have a width less than or equal to about 30 nanometers, desirably less than or equal to about 20 nanometers. In one exemplary embodiment, the pattern width of the semiconductor body or fin is approximately equal to the silicon body height 205.

In addition, the photoresist mask 206 may further include a pattern for defining a location where a source landing (landing) pad (not shown) and a drain landing pad (not shown) are to be formed. Landing pads (not shown) may be used to connect the source regions together and the drain regions together of the fabricated transistor.

In forming photoresistAfter the mask 206, the semiconductor film 202 is etched, if necessary, in alignment with the photoresist mask 206 to form one or more silicon bodies 207 or fins 207 (fig. 2C) and source and drain landing pads. Step 302 in fig. 3 corresponds to this portion of fabricating a tri-gate transistor in accordance with an embodiment of the subject matter disclosed herein. Semiconductor film 202 is etched until the underlying buried oxide layer 204 is exposed. Semiconductor etching techniques, such as anisotropic plasma etching or reactive ion etching, can be used to etch semiconductor film 202 in alignment with mask 206. After semiconductor film 202 has been etched to form one or more semiconductor bodies or fins 207 (and source/drain landing pads, if desired), for example, chemical stripping and O are utilized₂Ashing removes the photoresist mask to produce the substrate and semiconductor body, as shown in figure 2C. In an exemplary alternative embodiment, the well and the Vt implant may be formed.

Next, as shown in fig. 2D, a gate dielectric layer 208 is formed on and around each semiconductor body 207. That is, a gate dielectric layer 208 is formed on a top surface 209 of each semiconductor body 207 and on laterally opposite sidewalls 210 and 211 of each semiconductor body 207. The gate dielectric may be a deposited dielectric or a grown dielectric. In one exemplary embodiment, the gate dielectric layer 208 is a silicon-dioxide dielectric film grown using a dry/wet oxidation process. In an exemplary embodiment, the silicon-dioxide film is grown to between aboutAnd aboutTo the thickness of (d) in between. In another exemplary embodiment, the gate dielectric film 207 is a deposited dielectric such as, but not limited to, a high dielectric constant film, such as a metal oxide dielectric, such as tantalum pentoxide and titanium oxide, or other high-K dielectrics, such as zirconate, titanate (PZT), or Barium Strontium (BST). For example, the high dielectric constant film may be formed by Chemical Vapor Deposition (CVD). In the exemplary embodimentIn an alternative embodiment, dummy gates may be formed for the Hi-K/metal gate fabrication process.

After forming the gate dielectric layer 208, a gate electrode 212 is formed. Step 303 in fig. 3 corresponds to this portion of fabricating a tri-gate transistor in accordance with an embodiment of the subject matter disclosed herein. As shown in fig. 2D and 2E, a gate electrode 212 is formed on all sides of the gate dielectric layer 208. Fig. 2E shows two transistors coupled together by a single gate electrode 212, while fig. 2D shows only one transistor. Gate electrode 212 has a top surface 213 (fig. 2D) opposite a bottom surface (not shown, formed on insulating layer 204) and having a pair of laterally opposite sidewalls 214 and 215. The distance between the laterally opposite sidewalls 214 and 215 defines the gate length Lg of the tri-gate transistor. In one exemplary embodiment, the gate length Lg is less than or equal to about 30 nanometers, and desirably less than or equal to about 20 nanometers.

For example, gate electrode 212 may be formed by blanket depositing an appropriate gate electrode material over the substrate shown in fig. 2D. In one exemplary embodiment, the gate electrode 212 is formed to have a thickness of aboutAnd aboutTo the thickness of (d) in between. In another exemplary embodiment, the thickness or height of the gate electrode 212 is at least three times the height of the semiconductor body 208. The gate electrode material is then patterned using photolithography and etching techniques to form gate electrode 212 from the gate electrode material. In one exemplary embodiment, the gate electrode material comprises polysilicon. In another exemplary embodiment, the gate electrode material comprises a polysilicon-germanium alloy. In yet another exemplary embodiment, the gate electrode material may include a metal film, such as tungsten, tantalum, and nitrides thereof.

Next, source 216 and drain 217 regions for the transistors are formed in the semiconductor body 208 on opposite sides of the gate electrode 212. On-line displayIn one exemplary embodiment, the source and drain regions 216 and 217 include tip or source/drain extension regions (not shown). such source and drain extension regions may be formed by placing dopants into the semiconductor body 207 on both sides of the gate electrode 212 to form tip regions²⁰Atom/cm³And about 1 × 10²¹Atom/cm³For an NMOS tri-gate transistor, the semiconductor fin or body 208 is doped to a concentration of between about 1 × 10²⁰Atom/cm³And about 1 × 10²¹Atom/cm³Is conductive. In one exemplary embodiment, the silicon film is doped by ion implantation. In another exemplary embodiment, the ion implantation is performed in a vertical direction (i.e., a direction perpendicular to the substrate 200). When the gate electrode 212 is a polysilicon gate electrode, the gate electrode 212 may be doped during an ion implantation process. The gate electrode 212 acts as a mask to prevent the ion implantation step from doping the channel region (not shown) of the tri-gate transistor. The channel region is the portion of the semiconductor body 208 that is under or surrounded by the gate electrode 212. If the gate electrode 212 is a metal electrode, a dielectric hard mask may be used to block doping during the ion implantation process. In other exemplary embodiments, the semiconductor body may be doped to form source and drain extension regions using other exemplary methods, such as solid source diffusion. In another exemplary embodiment, the source and drain regions 216 and 217 include a semiconductor film (not shown) formed on exposed surfaces of the semiconductor body 207 to form source and drain contact regions. In another exemplary embodiment, a semiconductor film (not shown) is grown after recess etching the fins in the source-drain regions, which will be used to strain the channel. One example is strained silicon germanium SiGe. Another example isStrained silicon carbide SiC.

In an exemplary embodiment, a "halo" region (not shown) may be formed in the semiconductor body 207 prior to forming the source/drain regions or the source/drain extension regions. A halo region is a doped region formed in the channel region of the device that is of the same conductivity type as, but of a slightly higher doping concentration than, the channel region of the device. The halo region may be formed by ion implanting dopants under the gate electrode using a high angle ion implantation technique.

Next, if desired, the substrate may be further processed to form additional features such as heavily doped source/drain contact regions, deposited silicon on the source and drain regions, and a gate electrode on which source/drain contacts may also be formed. The source/drain contacts may be formed by depositing metal around the fins and reacting or not reacting. If the deposited metal is left unreacted, the metal in the undesired areas is removed.

In one exemplary embodiment, dielectric sidewall spacers 218 may be formed on sidewalls of the gate electrode 212 (fig. 2F). The heavy source/drain contact implant may be offset with sidewall spacers 218, which may be used to isolate the source/drain regions from the gate electrode during a selective silicon deposition process. The spacers 218 may be formed over the substrate 200 by blanket depositing a conformal dielectric film, such as, but not limited to, silicon nitride, silicon oxide, silicon oxynitride, or combinations thereof. The dielectric film forming spacers 218 is deposited in a conformal manner such that the dielectric film forms a substantially equal height on vertical surfaces, such as sidewalls of gate electrode 212, and on horizontal surfaces, such as the top of semiconductor body 207 and the top of gate electrode 212. In one exemplary embodiment, the dielectric film is a silicon nitride film formed by a hot wall Low Pressure Chemical Vapor Deposition (LPCVD) process. The deposited thickness of the dielectric film determines the width or thickness of the spacers formed. In an exemplary embodiment, the dielectric film is formed to have a thickness of aboutAnd aboutTo the thickness of (d) in between.

Next, the dielectric film is anisotropically etched, e.g., plasma etched or reactive ion etched, to form sidewall spacers 218, as shown in fig. 2F. The anisotropic etching of the dielectric film removes the dielectric film from horizontal surfaces, such as the tops of gate electrodes 212 (and the tops of landing pads (not shown), if used), leaving dielectric sidewall spacers adjacent to vertical surfaces, such as the sidewalls of gate electrodes 212. The etching is continued for a sufficient time to remove the dielectric film from all horizontal surfaces. In an exemplary embodiment, an over etch is utilized such that the spacer material on the sidewalls of the semiconductor body 207 is removed, as shown in fig. 2F. As shown in fig. 2F, sidewall spacers 218 are formed extending along and adjacent to the sidewalls of gate electrode 212. The height of sidewall spacers 218 is shown to be less than the height of gate electrode 212.

Next, if desired, a semiconductor film 219 can be formed on the exposed surface of the semiconductor body 207 (and on landing pads (not shown)), as shown in fig. 2G. In addition, a semiconductor film 220 may be formed on top of the gate electrode 212, if necessary. Semiconductor film 220 may be a single crystal film or a polycrystalline film. In an exemplary embodiment, semiconductor film 219 is an epitaxial (single crystal) silicon film. In one exemplary embodiment, the silicon film 219 is formed by a selective deposition process wherein silicon is formed only on exposed regions comprising silicon, such as on exposed top surfaces and sidewalls of the semiconductor body 207. In a selective deposition process, a silicon film is not formed on dielectric regions, such as sidewall spacers 218. When the gate electrode 212 includes a polysilicon film, a semiconductor film is also selectively formed on the top surface of the gate electrode 212 to form a silicon film 220. In one exemplary embodiment, the silicon film 220 is formed to have a thickness of aboutAnd aboutTo the thickness of (d) in between. The silicon film may be doped in situ (i.e., doped during deposition) or subsequently doped by, for example, ion implantation or solid source diffusion. The silicon film is doped to the desired conductivity type of the device source and drain regions. In an exemplary embodiment, the deposited silicon films 219 and 220 are intrinsic silicon films (i.e., undoped silicon films). Depositing semiconductor film 219 forms raised source and drain regions improves the parasitic characteristics of the device.

In one exemplary embodiment, as shown in FIG. 2H, the deposited silicon films 219 and 220 are doped by ion implantation utilizing a vertical ion implantation angle the ion implantation process dopes the deposited silicon film 219 and the underlying semiconductor body 207 to between about 1 × 10²⁰Atom/cm³And about 1 × 10²¹Atom/cm³To form source contact regions 216 and drain contact regions (not shown in fig. 2H). The sidewall spacers 218 offset the source/drain contact implantation step and define a tip region (not shown) as a doped silicon body region under the sidewall spacers 218. Thus, the fabrication process source region 216 and drain region 217 (not shown in fig. 2H) each include a tip region and a contact region. A tip region (not shown) is the region of the semiconductor body 207 that is located below the sidewall spacers 218. The contact region is the region of the semiconductor body 207 and the deposited silicon film 219 adjacent the outer edge of the sidewall spacers 218. Further, when utilized, the source/drain contact regions include source and drain landing pads (not shown).

Next, metal 221 is formed in a surrounding configuration on the source and drain regions and on top of gate electrode 212. In one exemplary embodiment, in the ILD layer, for example, deposited SiO₂Trenches for forming contact vias are formed (not shown) such that the tops and sidewalls of the source and drain regions are exposed. Metal 221 is then deposited on the exposed portions of the source and drain regions using CVD techniques. In another exemplary embodiment, then, use is made ofThe ALD technique forms metal 221 on the exposed portions of the source and drain regions. The remaining portion of the via is filled with a metal like tungsten. Chemical mechanical polishing is used to remove the tungsten and contact metal from the area outside the via. In another exemplary embodiment, metal is deposited inside the via and reacts to form a metal silicide that does not deplete the entire fin, then the via is filled with via metal, and the metal is removed from outside the via using chemical mechanical polishing. In another exemplary embodiment, silicide may be formed on the surface of the source and drain regions in contact with the metal by heat treating the device. In one exemplary embodiment, the silicide is formed such that it does not deplete the entire source region or the entire drain region, such that the interface area between the metal 221 and the source and drain regions is proportional to the fin height. The excess metal 221 is then removed, for example by chemical etching. In one exemplary embodiment using a Hi-K metal gate, no silicide is formed on the gate. Step 305 in fig. 3 corresponds to this portion of fabricating a tri-gate transistor in accordance with an embodiment of the subject matter disclosed herein. Metal 221 may be formed of a material that provides good contact to the source and drain regions, such as, but not limited to, titanium, tungsten, nickel, copper, or cobalt, or any other metal having a contact resistance equal to or less than that of NiSi. Metal 221 is formed on the source and drain regions to form source and drain contact regions such that the contact regions advantageously scale as the fin height increases.

The above description of illustrated embodiments, including what is described in the abstract, is not intended to be exhaustive or to be limited to the precise forms disclosed. While specific embodiments of, and examples for, the invention are described herein for illustrative purposes, various equivalent modifications are possible within the scope of the specification, as those skilled in the relevant art will recognize.

These modifications may be made in light of the above detailed description. The terms used in the following claims should not be construed to limit the scope to the specific embodiments disclosed in the specification and the claims. Rather, the scope of the embodiments disclosed herein is to be determined by the following claims, which are to be construed in accordance with established doctrines of claim interpretation.

Claims (8)

1. A semiconductor device, comprising:

a substrate; and

a semiconductor body formed on the substrate, the semiconductor body comprising a source region and a drain region, at least one of the source region and the drain region comprising a first side surface, a second side surface, and a top surface, the first side surface opposite the second side surface,

a semiconductor film grown on exposed surfaces of the source and drain regions to form raised source and drain regions, wherein the semiconductor film is grown after recess etching fins in the source and drain regions and is used to strain the channel,

a high-permittivity gate dielectric layer formed on the first side surface, the second side surface, and the top surface of the semiconductor body between the source region and the drain region,

a metal gate electrode formed on the high-k gate dielectric layer, and

a metal layer formed on the first side surface, the second side surface and the top surface of the source region and the drain region and on top of the metal gate electrode,

wherein a dummy gate is formed for a high dielectric constant/metal gate fabrication process.

2. The semiconductor device of claim 1, wherein the metal layer provides a contact surface with the first and second side surfaces of the source and drain regions, the contact surface scaled in proportion to a height of the semiconductor body.

3. The semiconductor device of claim 2, wherein the substrate comprises an insulating substrate or a bulk substrate.

4. The semiconductor device of claim 3, wherein the metal layer comprises: titanium, tungsten, nickel, copper or cobalt or any other metal with a contact resistance equal to or less than that of NiSi, or a combination thereof.

5. A method of forming a semiconductor device, the method comprising:

providing a substrate; and

forming a semiconductor body on the substrate, the semiconductor body comprising a source region and a drain region, at least one of the source region and the drain region comprising a first side surface, a second side surface, and a top surface, the first side surface being opposite the second side surface,

growing a semiconductor film on exposed surfaces of the source and drain regions to form raised source and drain regions, wherein the semiconductor film is grown after recess etching fins in the source and drain regions and is used to strain the channel,

forming a high-k gate dielectric layer on the first side surface, the second side surface, and the top surface of the semiconductor body between the source region and the drain region,

forming a metal gate electrode on the high-k gate dielectric layer, and

forming a metal layer on the first side surface, the second side surface and the top surface of the source region and the drain region and on top of the metal gate electrode,

wherein a dummy gate is formed for a high dielectric constant/metal gate fabrication process.

6. The method of claim 5, wherein the metal layer provides a contact surface with the first and second side surfaces of the source and drain regions, the contact surface scaled in proportion to a height of the semiconductor body.

7. The method of claim 6, wherein the substrate comprises an insulating substrate or a bulk substrate.

8. The method of claim 7, wherein the metal layer comprises: titanium, tungsten, nickel, copper or cobalt or any other metal with a contact resistance equal to or less than that of NiSi, or a combination thereof.