HK1172443A - Flash memory device comprising host interface for processing a multi-command descriptor block in order to exploit concurrency - Google Patents
Flash memory device comprising host interface for processing a multi-command descriptor block in order to exploit concurrency Download PDFInfo
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- HK1172443A HK1172443A HK12113166.7A HK12113166A HK1172443A HK 1172443 A HK1172443 A HK 1172443A HK 12113166 A HK12113166 A HK 12113166A HK 1172443 A HK1172443 A HK 1172443A
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Description
Technical Field
Background
Flash memory devices may be used as mass storage for computer systems (e.g., desktop, notebook, portable, etc.) or consumer devices (e.g., music players, cell phones, cameras, etc.) or other suitable applications. A flash memory device may include one or more flash memories (e.g., NAND, NOR, etc.) and a flash memory controller that accesses each flash memory. Each flash memory is coupled to an I/O (input/output) bus and a number of interface control lines. When issuing a program command or an erase command to the memory device, the flash controller transfers address and command data (as well as write data for a program operation) over the I/O bus. When a read command is issued, the flash memory controller transmits address and command data via the I/O bus and receives read data via the I/O bus.
Fig. 1A shows a prior art flash memory device 2 communicating with a host 4 according to a suitable communication protocol. The flash memory controller 6 includes a buffer 8 for buffering data for read/write commands, and a microprocessor 10 for executing control programs for various algorithms, such as mapping of Logical Block Addresses (LBAs) to Physical Block Addresses (PBAs), wear leveling (wear leveling), Error Correction Codes (ECCs), and the like. The flash memory controller 6 also includes an interface circuit 12 that interfaces with one or more flash memories 14. The interface circuit 12, in conjunction with executing read/write commands initiated by the microprocessor 10, generates appropriate control signals 16 and receives status information 18 from the flash memory 14. The interface circuit 12 also transmits and receives data via the I/O bus 20, including read/write data stored in the buffer 8 or command data generated by the microprocessor 10 and transmitted to a controller 22 integrated with the flash memory 14.
The flash memory 14 includes an array of memory cells 24 that are accessible in memory segments called pages. During a write operation, write data received from the buffer 8 via the I/O bus 20 is first stored in the data register 26. The controller 22 then transfers the write data from the data register 26 to the target page in the memory array 24. In a read operation, a page in the memory array 24 is read into the data register 26 and then transferred over the I/O bus 20 to where it is stored in the buffer 8.
There is an access time associated with programming the write data stored in the data register 26 to a target page in the memory array 24 during a write operation and reading the data from the target page in the memory array 24 into the data register 26 during a read operation. The busy status is typically returned to flash controller 6 until flash memory 14 completes accessing memory array 24. As described in more detail below, flash memory device 2 may include multiple flash memories that are concurrently programmed (e.g., concurrent write or read operations), thus overlapping the access times of the flash memories and increasing the throughput of the flash memory device.
Fig. 1B shows a prior art flash memory device 28 including a host interface 30 for implementing standard communication protocols (e.g., multi-media card (MMC), Universal Serial Bus (USB), universal flash memory (UFS), etc.) for communication with the host 4. The flash memory device 28 also includes a plurality of flash memories 141-143Wherein each flash memory 14iTwo devices, D1 and D2, are included and each includes a memory array 24 and a corresponding data register 26. Flash controller 6 includes independent channels 321-323(Each channel includes control 16, status 18, and I/O bus 20, as shown in FIG. 1A) for use with a corresponding flash memory 141-143And (4) communication. This configuration increases throughput by employing multiple devices and multiple channels to enable flash controller 6 to perform concurrent operations. For example, the flash memory controller 6 may write data to the first flash memory 14 by writing the data to the first flash memory1Performs a write operation and then commands the first flash memory 14 to write to the data registers in the devices D1 and D21The data register is programmed to the target page of each device. In the first flash memory 141During the access time of the flash memory controller 6 may write more data to the second flash memory 142And the data registers in the devices D1 and D2, and then commands the second flash memory 142The data register is programmed to the target page of each device. By writing data to the third flash memory 143Still more data may be processed so that the access times of all three flash memories overlap as they process their respective data concurrently. Similar performance enhancements may be achieved for read operations by commanding multiple flash memories to concurrently read data from their respective devices.
Brief description of the invention
FIG. 1A illustrates a prior art flash memory device including a flash memory controller for accessing a flash memory.
Fig. 1B illustrates a prior art flash memory device including a host interface for implementing a conventional communication protocol (e.g., multi-media card (MMC), Universal Serial Bus (USB), universal flash memory (UFS), etc.).
FIG. 2A illustrates a flash memory device including a host interface operable to receive a multi-command descriptor block including identifiers identifying a plurality of access commands that a host is preparing to request, according to an embodiment of the invention.
FIG. 2B is a flow diagram according to an embodiment of the present invention in which access commands are grouped and then executed concurrently by concurrently accessing at least first and second flash memories.
FIG. 2C illustrates an example of a multi-command descriptor block according to an embodiment of the present invention.
Fig. 2D illustrates an embodiment of concurrently accessing the first and second flash memories, wherein at least a portion of the access times overlap.
FIG. 3 is a flow diagram according to an embodiment of the present invention in which a multiple command descriptor block identifies multiple write commands.
FIG. 4 is a flow diagram according to an embodiment of the present invention wherein a multiple command descriptor block identifies multiple read commands.
Detailed Description
FIG. 2A illustrates a flash memory device including a plurality of flash memories 361-363The plurality of flash memories 36, the flash memory device 34 of1-363Including a first flash memory 361And a second flash memory 362. Flash controller 38 is coupled to first channel 401Access the first flash memory 361And through the firstTwo channels 402Accessing the second flash memory 362. The host interface 42 performs the operations shown in the flow diagram of FIG. 2B, where the multi-command descriptor block is received from the host 4 (step 46). The multi-command descriptor block contains identifiers that identify a plurality of access commands that the host is preparing for a request (FIG. 2C). A first set of access commands is selected for concurrent execution and a second set of access commands is selected for concurrent execution (step 48). A first set of access commands is received from the host and executed concurrently by accessing at least the first and second flash memories concurrently (step 50). The second set of access commands are received from the host by concurrently accessing at least the first and second flash memories and are executed concurrently (step 52).
Any suitable flash memory 36 may be employed in embodiments of the present invention, such as any suitable non-volatile electrically erasable and programmable semiconductor memory. Typical flash memories found on the market include NAND-type and NOR-type memories; however, aspects of the present invention are applicable to any type of memory available now and in the future.
The multi-command descriptor block is shown generally in fig. 2C, but in practice it may comprise any suitable format including additional fields supporting any suitable communication protocol. In one embodiment, the multi-command descriptor block may be implemented as a new command of the communication protocol or incorporated in an existing command of the communication protocol (i.e., become the payload of an existing command). In one embodiment, the access command may include a write command, a read command, or an erase command. A user of the flash memory device may issue an erase command to physically erase data stored in one or more of the flash memories. In one embodiment, the multi-command descriptor block may include a mix of different commands, including write and read commands. However, in embodiments that allow write and read commands to be within the same descriptor block, the access commands must be executed in the correct order to ensure data coherency (i.e., to ensure that the write command is executed before the read command when accessing the same address). In another embodiment, the multi-command descriptor block may include write and erase commands, or read and erase commands, but not both, to simplify implementation by avoiding data coherency issues.
In one embodiment, and flash memory 361-363Channel 40 for communication1-403May be implemented separately with the ability to be programmed concurrently by the flash controller 38. This embodiment is illustrated in FIG. 2D, where the flash controller 38 may issue access commands to two or more channels concurrently (or simultaneously) so that the command times overlap. In an alternative embodiment, the channel 401-403May be multiplexed such that the flash controller 38 issues access commands serially to each target flash. In this embodiment, the command times do not overlap, as illustrated in fig. 2D. However, in both embodiments, the access times of the flash memories (the time required to write data to or read data from or erase the memory array) at least partially overlap, so that the flash memories are concurrently accessed for at least part of the access times.
The multi-command descriptor block of the embodiment of FIG. 2C helps to improve performance by delaying the execution of access commands received from the host. That is, the host interface 42 evaluates the access commands in the multi-command descriptor block to determine how to execute the commands in an order that utilizes concurrent access of the flash memory. For example, when multiple read commands are identified by the multi-command descriptor block, the read commands may be grouped and then executed so that they may be read from the flash memory 361-363Two or more of the data are read concurrently. For a write command, the write data is buffered for several write commands until enough data is received to allow concurrent writes to the flash memory 361-363Two or more of them. The erase command may also be interleaved with the read or write command to erase data stored in the first flash memory and read/write data from/to the second flash memory.
FIG. 3 is a flow diagram according to an embodiment of the present invention wherein a multi-command descriptor block containing a plurality of write commands is received from a host (step 54). The write commands are evaluated and grouped to improve throughput by executing the write commands in an order that enables concurrent writing to the at least two flash memories (step 56). After the above-described write command is packetized, the host is notified to send the next command (the first write command (step 58)), which may be implemented as an acknowledgement transmitted to the host that the flash memory device completed processing the multi-command descriptor block. Write data for the write command is received and buffered in memory (step 60). The process is then repeated by informing the host to send the next command (step 58) and the write data is buffered in memory (step 60) until enough data is buffered to enable concurrent write data (step 62). In the embodiment of FIG. 3, the write operation is delayed until enough write commands are received corresponding to the group identified in step 56. In other embodiments, a write operation may begin executing before all write commands of a group are received.
Once enough write data is buffered, at least two of the flash memories are programmed to write the data to the corresponding memory arrays (step 64), as illustrated in FIG. 2D. In the embodiment of fig. 3, concurrent with accessing (writing to) the memory array in the flash memory, write data for a subsequent write command is transferred from the host. That is, steps 58 and 60 are performed concurrently with step 64 (until the write buffer is full at step 66). If the write buffer is full in step 66, the process of receiving write data from the host is suspended until the buffered write data is written to the flash memory (thus freeing space in the write buffer) in step 64. This embodiment improves performance (increases throughput) by overlapping the receipt of write data from the host and the concurrent writing of data to the flash memory. When the current write operation to the flash memory is completed (step 68), the process repeats from step 64 until the write buffer is empty (step 70), and repeats from step 58 until all write commands are processed (step 71). After completing the write operation for the last write command, the flash device notifies the host of the status of all write commands received in the multi-command descriptor block (and the status of any erase commands that may have been included in the multi-command descriptor block) (step 72).
FIG. 4 is a flow diagram according to an embodiment of the present invention wherein a multi-command descriptor block containing a plurality of read commands is received from a host (step 74). These read commands are evaluated and grouped to improve throughput by executing the read commands in an order that enables concurrent reads from at least two flash memories (step 76). At least two flash memories are then programmed to concurrently read data from their memory arrays (step 78), wherein the read data is buffered in a read buffer. When the current read operation is completed (step 80), the process repeats from step 78 until all read commands have been executed (step 82). If the read buffer becomes full at step 88, the process of reading data from the flash memory may be suspended.
Once sufficient read data has been buffered in the read buffer, the host is notified to transmit the next access command (the first read command (step 84)), which can serve as an acknowledgement that the flash memory device transmitted to the host has completed processing the multi-command descriptor block. When a read command is received from the host, the corresponding read data is transferred from the read buffer to the host (step 86). In the embodiment of FIG. 4, the steps of reading data from the flash memory and transmitting the read data to the host are performed concurrently. That is, steps 84 and 86 are performed concurrently with step 78 (until the read buffer is full at step 88). If the read buffer is full at step 88, the process of reading data from the flash memory is suspended until the buffered read data is transferred to the host at step 86 (thereby freeing up space in the read buffer). This embodiment improves performance (increases throughput) by overlapping transfers of read data to the host and concurrent reads of data from the flash memory. Steps 84 and 86 are repeated until the read buffer is empty at step 90, wherein the flowchart repeats from step 80 until the last read command has been processed at step 92.
The control circuitry (e.g., host interface 42 and/or flash controller 38 of fig. 2A) in the flash memory device may include any suitable circuitry for implementing the flow diagrams herein, such as one or more integrated circuits. In one embodiment, the control circuitry may include one or more microprocessors to execute code segments of the control program. In other embodiments, the control circuitry may comprise state machine circuitry in an Application Specific Integrated Circuit (ASIC).
Claims (24)
1. A flash memory device, comprising:
a plurality of flash memories including a first flash memory and a second flash memory;
a flash memory controller for accessing the first flash memory through a first channel and the second flash memory through a second channel; and
a host interface operable to:
receiving a multi-command descriptor block from a host, wherein the multi-command descriptor block includes identifiers that identify a plurality of access commands that the host is preparing to request;
selecting a first set of access commands for concurrent execution and selecting a second set of access commands for concurrent execution;
receiving the first set of access commands from the host;
concurrently executing the first set of access commands by concurrently accessing at least the first and second flash memories;
receiving the second set of access commands from the host; and
concurrently executing the second set of access commands by concurrently accessing at least the first and second flash memories.
2. The flash memory device of claim 1, wherein:
the first set of access commands comprises a first set of write commands; and
the second set of access commands comprises a second set of write commands.
3. The flash memory device of claim 2, wherein the host interface is further operable to:
receiving the first set of write commands from the host including first write data; and
after receiving the first set of write commands and the first write data, concurrently writing the first write data to at least the first and second flash memories.
4. The flash memory device of claim 3, wherein the host interface is further operable to receive the second set of write commands comprising second write data from the host and concurrently write the first write data to at least the first and second flash memories.
5. The flash memory device of claim 4, wherein after writing the first write data concurrently to at least the first and second flash memories, the host interface is further operable to write the second write data concurrently to at least the first and second flash memories.
6. The flash memory device of claim 5, wherein the host interface is further operable to notify the host of an execution status of an access command identified by the multi-command descriptor block after the second write data is concurrently written to at least the first and second flash memories.
7. The flash memory device of claim 1, wherein:
the first set of access commands comprises a first set of read commands; and
the second set of access commands includes a second set of read commands.
8. The flash memory device of claim 7, wherein the host interface is further operable to:
concurrently reading first data from at least the first and second flash memories, wherein the first data corresponds to the first set of read commands;
receiving the first set of read commands from the host; and
transmitting the first data to the host.
9. The flash memory device of claim 8, wherein the host interface is further operable to receive the first set of read commands from the host and to concurrently read the first data from at least the first and second flash memories.
10. The flash memory device of claim 9, wherein:
after concurrently reading the first data from at least the first and second flash memories, the host interface is further operable to concurrently read second data from at least the first and second flash memories; and
the second data corresponds to the second set of read commands.
11. The flash memory device of claim 1, wherein:
the first set of access commands comprises at least one write command; and
the second set of access commands includes at least one erase command.
12. The flash memory device of claim 1, wherein:
the first set of access commands comprises at least one read command; and
the second set of access commands includes at least one erase command.
13. A method of operating a flash memory device, the flash memory device comprising a plurality of flash memories including first and second flash memories, and a flash memory controller for accessing the first flash memory through a first channel and the second flash memory through a second channel, the method comprising:
receiving a multi-command descriptor block from a host, wherein the multi-command descriptor block includes identifiers that identify a plurality of access commands that the host is preparing to request;
selecting a first set of access commands for concurrent execution and selecting a second set of access commands for concurrent execution;
receiving the first set of access commands from the host;
concurrently executing the first set of access commands by concurrently accessing at least the first and second flash memories;
receiving the second set of access commands from the host; and
concurrently executing the second set of access commands by concurrently accessing at least the first and second flash memories.
14. The method of claim 13, wherein:
the first set of access commands comprises a first set of write commands; and
the second set of access commands comprises a second set of write commands.
15. The method of claim 14, further comprising:
receiving the first set of write commands including first write data from the host; and
after receiving the first set of write commands and first write data, concurrently writing the first write data to at least the first and second flash memories.
16. The method of claim 15, further comprising receiving the second set of write commands including second write data from the host and concurrently writing the first write data to at least the first and second flash memories.
17. The method of claim 16, wherein after concurrently writing the first write data to at least the first and second flash memories, further comprising concurrently writing the second write data to at least the first and second flash memories.
18. The method of claim 17, further comprising notifying the host of the status of execution of the access command identified by the multi-command descriptor block after concurrently writing the second write data to at least the first and second flash memories.
19. The method of claim 13, wherein:
the first set of access commands comprises a first set of read commands; and
the second set of access commands includes a second set of read commands.
20. The method of claim 19, further comprising:
concurrently reading first data from the at least first and second flash memories, wherein the first data corresponds to the first set of read commands;
receiving the first set of read commands from the host; and
transmitting the first data to a host.
21. The method of claim 20, further comprising receiving the first set of read commands from the host and concurrently reading the first data from the at least first and second flash memories.
22. The method of claim 21, wherein:
after concurrently reading the first data from at least the first and second flash memories, further comprising concurrently reading the second data from at least the first and second flash memories; and
the second data corresponds to the second set of read commands.
23. The method of claim 13, wherein:
the first set of access commands comprises at least one write command; and
the second set of access commands includes at least one erase command.
24. The method of claim 13, wherein:
the first set of access commands comprises at least one read command; and
the second set of access commands includes at least one erase command.
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US13/073,638 | 2011-03-28 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| HK1172443A true HK1172443A (en) | 2013-04-19 |
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