HK1167525A - Improvements in dc-dc converters - Google Patents

Description

Improvements in DC-DC converters

The present invention relates to voltage converters, in particular to DC-DC or switching voltage regulators, and to methods and apparatus for controlling such regulators, in particular to provide current limiting control, for example for protection against current overload or short circuit ground conditions and/or during start-up.

Voltage converters, such as DC-DC converters, are used in a range of different applications. Fig. 1 shows a typical application, in which a DC-DC converter 100 supplies a voltage V to a processor circuit 101 (which may be, for example, a processor of a portable electronic device)_OUT(102). The DC-DC converter 100 receives an input voltage V_IN(103) And an external clock signal CLK (104) and outputs a desired voltage output V_OUT(102). Typically, the required processor supply voltage varies with the processor frequency, which may vary with the processing load. When the processing load is light, the processor reduces the operating frequency, thereby reducing the required voltage to conserve power. Thus, the processor circuit 101 provides the voltage selection signal V to the DC-DC converter 100_SEL(105) To select a suitable voltage output V_OUT. The voltage selection signal may be a digital signal for controlling a programmable element (e.g., a level shifter) of the DC-DC converter, as will be described below. The DC-DC converter 100 may also operate in a variety of MODEs, as will be described below, and the processor circuit may select a particular operating MODE by an appropriate MODE control signal MODE (106). It should be understood that the DC-DC converter may be used to provide power to device subsystems other than the processor, and the embodiments described herein are generally applicable to many DC-DC converters or switching voltage regulators for many applications.

A conventional current mode buck (i.e., step down) DC-DC converter 200 is shown in simplified form in fig. 2. The converter 200 includes two nested (nested) feedback loops: an inner current control loop and an outer voltage control loop.

The current control loop module 201 obtains an input signal V_ERRORAnd a current sense signal ISNS fed back from the output stage and generating a pulse width modulated drive signal for the output stage 202. Voltage on output node LX of output stage at ground voltage and supply voltage V with controlled duty cycle_INTo generate a triangular current waveform in the inductor L. Inductor L and output capacitor C1 act as a filter to ensure an average voltage V at output node 203_OUT。

In operation, the inductor current is sensed and compared to V_ERRORAnd (6) comparing. So that the feedback loop is generated in dependence on the input signal V_ERRORWhile the varying output senses the current (output sense current). In many conventional DC-DC converters, the sensed current is a peak current, although it is known to use an average current in some converters. Alternatively, a minimum or "valley" current may be used to control the duty cycle of the converter.

The variation of the delivered output current (smoothed by the output filter L, C1) regulates the output voltage at V_OUT. The voltage V_OUTIs fed back (down-converted to the appropriate voltage V by a level shifter or voltage shifter module 204)_{OUT_LS}) Back to the input of the voltage error amplifier block 205. The voltage error amplifier module 205 converts this processed V_OUTAnd a supplied reference voltage V_REFCompares and provides an error signal V_ERRORThe error signal drives the inner feedback loop to close the outer feedback loop, thereby coupling V_OUTStabilized at the desired voltage.

The level shifter 204 is shown as a resistive potential divider (resistive divider). The level shifter pair V_OUTSuch that when V is applied_OUTLevel shift signal V at the desired or target output voltage_{OUT_LS}And a reference voltage V_REFThere is a known relationship (e.g., when V_OUTJust as expected outputWhen the voltage is output, the level is shifted to change the signal V_{OUT_LS}Can be equal to V_REF). The level shifter 204 may be programmable (mechanically or digitally) to provide different voltage scaling or shifting circuits, allowing the converter to be configurable to output different V_OUTThe value is obtained. For example, the level shifter 204 may be a digital multi-bit signal (e.g., the processor-generated V shown in FIG. 1)_SELSignals) are programmable.

The voltage error Amplifier module 205 is shown as including an Operational Transconductance Amplifier (OTA)206 that drives an RC network 207, but may include other amplifiers. An RC network 207 or other impedance provides closed loop stability.

The current loop control module 201 receives a signal 208 from the output stage 202, and the signal 208 is passed through a current sensor amplifier module 209 to pre-process (pre-condition), e.g., scale or gate (strobe), the signal representative of the inductor current to produce a convenient current sense signal ISNS. A duty modulator (duty modulator)210 couples the ISNS signal to an input V_ERRORTo derive a drive signal of suitable duty cycle to drive the output stage arrangement (10, 20) on and off via the switch driver buffer stage 211. The duty modulator 210 may require a clock signal 212 and a ramp generator 213 to generate the necessary pulse sequences, as will be appreciated by those skilled in the art. The ramp generator 213 may generate a slope compensation ramp signal (VISLP), which may be added in whole or in part to the ISNS signal and/or the V signal_ERRORSignal to prevent subharmonic oscillation, as will be understood by those skilled in the art.

The output stage 202 will generally have: high side driver device, such as PMOS transistor 10, to switch the output to high side supply rail 214 (V)_IN) (ii) a And a low side driver device, such as NMOS transistor 20, to switch the output to the low side supply rail 215 (ground). The output stage 202 is also required to provide information (i.e., an indication) about the inductor current signal 208 for feedback to the current control module 201.

In electronic equipment in general, and particularly for fast moving parts such as portable consumer devices (e.g., mobile phones, MP3 players, etc.), there is a constant drive to use the latest processor technology to reduce power and cost while increasing device capacity and feature sets. As next generation processors become available, lower operating voltages are used than previous generation processors to allow process feature size (i.e., W/L) to be reduced, resulting in higher integration. This is advantageous in reducing the chip (die) size, reducing the chip cost, and reducing power consumption.

These trends have led DC-DC converters to have two design challenges in servicing these applications: one resulting from the selection of a low voltage value; another is caused by the transition of battery technology behind supplying voltage to lower processors.

(i) Under the prevailing processor load and battery conditions, the reduction of the processor supply voltage requires much more stringent (in an absolute sense) control of the DC-DC converter output voltage. If the control of the processor supply voltage is insufficient, under-voltage or over-voltage problems can occur, both of which are undesirable.

(ii) Since the battery terminal voltage has not decreased appreciably, and the duty cycle of the DC-DC converter is set by V_OUT/V_INGiven the ratio of (d), the duty cycle must be reduced. This, combined with the desire for small external components to push the DC-DC converter to a high operating frequency, results in extremely short switching on (i.e., conducting) times. Increased switching speeds caused by reduced transistor feature sizes are generally not available for power switches because the interface components must be rated for battery voltage.

Since the small conduction period (i.e., on-time) of the power switch is difficult to control, it becomes increasingly difficult to control lower processor output voltages with sufficient accuracy using conventional peak current mode control methods. Valley Current Mode (VCM) is an alternative method that has been proposed to control DC-DC converters. This DC-DC loop control method controls the off (i.e., non-conduction) time of the input transistor instead of the conduction time. For the required low duty cycle, the non-conduction time is longer than the conduction time and is therefore easier to control. VCMs are also known to provide inherently higher bandwidth and improved transient response.

One known problem of DC-DC converters is voltage overshoot and large inrush current at start-up (start-up) of the converter. This is especially a problem for valley current mode converters, since the high side device driver current is only indirectly controlled. A start-up mode that minimizes these problems but allows start-up to full load is advantageous.

Another known problem with DC-DC converters is to provide current limiting protection for current overload situations, e.g. to prevent short-circuit to ground. Conventional current limiting schemes typically monitor PMOS current for current limiting purposes and shut off the PMOS when a current limit is reached. However, in a short-to-ground situation, the voltage difference across the inductor may be high during PMOS turn-on and zero during NMOS turn-on, with the result that the inductor current decays slowly. Even if the PMOS is turned on for a short period (sufficient to allow comparison with the current limit), the current can be made to increase more than decay for the remainder of the cycle. This results in so-called step-stepping of the inductor current, wherein the inductor current ramps up (ramp up) on a cycle-by-cycle basis.

It is therefore an object of the present invention to provide a method and an apparatus for controlling a DC-DC converter which at least alleviate at least some of the above problems.

Therefore, according to the present invention, there is provided a current limiting method in a DC-DC converter, comprising: monitoring whether a first signal indicative of current in the converter is above a first threshold when a high side switch is on; turning off the high-side switch if the first signal is above the first threshold; monitoring whether a second signal indicative of current in the converter is above a second threshold when the high-side switch is off; and if the second signal is above the second threshold, forbidding to turn on the high-side switch.

The method of this aspect of the invention provides a current limiting method in a DC-DC converter. As will be readily apparent to those skilled in the art, a DC-DC converter includes a component, such as an inductor, that switches between a high-side voltage supply and a low-side voltage supply by controlling the high-side switch and the low-side switch, respectively. The high-side switch and the low-side switch may comprise transistors, for example a PMOS switch and an NMOS switch, respectively. The method provides current limiting by monitoring a first signal indicative of current in the converter (i.e., current flowing through the inductor) against a first threshold when a high-side switch is on. If the current rises above the first threshold, the high-side switch is turned off. In other words, the first threshold value serves as a peak current limit of the current flowing in the converter. The method also involves monitoring a second signal indicative of the current (i.e., the inductor current) against a second threshold when the high-side switch is off. Inhibiting turning on the high-side switch if the second signal is above the second threshold. Thus, the high-side switch may only turn on when the inductor current is not above the second threshold (which is the valley current threshold). The use of two thresholds provides a current control method that controls both the peak current delivered and the average current delivered. It will of course be appreciated that in current mode control of a DC-DC converter, the duty cycle of the converter is determined based on a comparison of the inductor current with a voltage error signal, sometimes referred to as a peak threshold in peak current mode, or a valley threshold in valley current mode. The first and second thresholds of the method provide peak and valley current thresholds, but they are separate limits to the voltage error threshold and are applied to provide current limiting.

This approach avoids the step-and-step problem that can occur in a short-circuit ground type situation (where the voltage at the output node is low). In this case, the rate of current increase when the high-side switch is on may be significantly greater than the rate of current decrease when the low-side switch is on. In this case, even if the high-side switch is turned on for only a small portion of each cycle, the resulting increase in current is greater than the subsequent decrease in current during the remainder of the cycle. The method of this aspect of the invention avoids this problem as will be described in more detail below.

The current limiting method may be applied during normal operation, i.e. operation involving normal use of the converter, to protect against current overload/short-circuit to ground. The method may additionally or alternatively be used in a method of starting a DC-DC converter that minimizes voltage overshoot and inrush current, as will be described in more detail below. Start-up refers to the transition period of the DC-DC converter from inactive to normal operation. The start-up mode is usefully employed when the output voltage is significantly lower than the target output voltage and/or any load capacitor or the like is substantially discharged.

The low-side switch may also be turned on if it is determined that the first signal is above the first threshold and the high-side switch is thus turned off. In steady state operation, the first signal reaching the first threshold may indicate an undesirably large current, and thus turning on the low side switch may help reduce this current.

However, in some situations, for example where the applied current limit is relatively low (such as may be used during start-up), if the low-side switch is on, the current may decrease to zero before the high-side switch turns on and then become negative. Negative or reverse current actually causes the supplied charge to be wasted. This is undesirable, especially in the start-up mode, as it reduces the average current, and thus the output voltage, and can potentially significantly increase the start-up duration. In one extreme case, current reversal may mean that the average current never reaches a height sufficient to initiate normal regulation.

Thus, in one embodiment, when the peak current limit is reached, the high-side switch is turned off, but the low-side switch remains in the off state. As described in more detail below, if the low-side switch is off and current flows in the inductor (e.g., if the high-side switch has been turned off, or if the low-side switch is turned off before the inductor current reaches zero), the current flows through a parallel path (diode path), such as a diode. As will be appreciated by those skilled in the art, the transistor switches may have associated parasitic body diodes (parasitic body diodes). Current may flow through the parasitic diode until the inductor current reaches zero. The diode does not conduct reverse current and therefore the inductor current does not become negative, i.e. not reverse. Passing a large current through the body diode may be undesirable, but in some embodiments an external diode or other unidirectional current carrying device may be provided in parallel with the low side switch to conduct current when the low side switch is off.

The high side switch is turned off if the first signal rises above the first threshold, i.e. the inductor current reaches the peak current limit. The low-side switch may also be switched on at this time so that the current starts to decrease. In some implementations, the low-side switch is held on to recirculate current until the high-side switch resumes on. Disabling turning on the high-side switch if the second signal (i.e., the converter inductor current) is above the second threshold. Thus, the high-side switch may be inhibited from turning on for one or more subsequent cycles. Thus, the low side switch may remain on for one or more cycles. Once the high-side switch is no longer inhibited from turning on, the low-side switch is turned off when the high-side switch is turned on.

However, as described above, if the applied current limit is relatively low, when the low-side switch is turned on, the current may decrease to zero before the high-side switch turns on and then become negative. Accordingly, the method may involve generating a low-side turn-off control signal to turn off the low-side switch before the high-side switch turns on. The low side cut-off control signal may be generated by monitoring the second signal against a third threshold, which may for example be set to near zero current. Alternatively, a third signal indicative of the current in the inductor may be monitored against the third threshold when the high-side switch is off. This third signal (which is different from the signal used to monitor against the valley current threshold) may also be derived from the properties of the low side switch, such as the source-drain voltage of the NMOS. A simple comparator circuit may be used to monitor against the third threshold.

The method involves: disabling turning on the high-side switch if the second signal is above the second threshold, i.e., the converter inductor current is above a valley current threshold. If the inductor current subsequently drops such that the second signal reaches the second threshold, turning on the high-side switch is no longer inhibited. However, the high-side switch does not have to be turned on immediately as soon as the second signal is no longer above the second threshold. Instead, the high-side switch is turned on only in response to a first control signal generated by the converter according to its operating mode.

For example, in a relevant mode of operation, such as normal operation of a peak current mode converter, the high-side switch may normally be turned on in response to a clock signal. The first control signal may thus be derived from a clock signal. In such an embodiment, if the high-side switch is turned off by reaching the peak current limit and the converter current subsequently falls below the valley current threshold before the next clock pulse (i.e., the second signal falls to the second threshold), then the high-side switch will not turn on at this time. Instead, the high-side switch is only turned on at the next clock pulse, consistent with normal operation of the converter.

The high-side switch may be turned on or off depending on the nature of the first control signal if the second signal reaches the second threshold only after the next clock pulse. If the first control signal generates a request to turn on the high-side switch (which is maintained until the high-side switch is actually turned on), the high-side switch is turned on as soon as it is no longer inhibited from turning on. In this case, when truncated, the high side switch resumes turning on at the next clock pulse or the later of the second signal reaching the second threshold. However, if the first control signal generates successive (successive) requests (synchronized with the appropriate clock pulse) to turn on the high-side switch but no on-request is maintained, then the high-side switch will only turn on at the next such request (i.e. the relevant clock edge) if the second signal falls to the second threshold between such requests.

In valley current mode, the control of the high side switch is based on a comparison of the inductor current with the voltage error (plus slope compensation), so the first control signal may comprise the result of this comparison. Thus, whether the high-side switch is turned on immediately upon the second signal falling to the second threshold depends on the current state of the comparison.

As mentioned above, the method may be used in a start-up mode of operation. In the start-up mode of operation, this current control can be used as the only way to control the high-side switch and the low-side switch, in other words, current loop control is used, while the normal voltage loop and current loop are effectively ignored. During the startup mode of operation, the voltage loop control may be left inactive or disabled. Thus, during the startup mode of operation, the high-side switch may be turned on until the first signal reaches the first threshold. At this point, the high-side switch may be turned off and subsequent turn-on of the high-side switch may be inhibited until the second signal reaches the second threshold. Preferably, in the start mode, the turning on of the high-side switch is controlled by a first control signal derived from a clock signal, preferably a clock signal of constant frequency. Thus, when the high-side switch is turned off when the first threshold is reached, the high-side switch remains turned off at least until the next clock pulse. This may provide a constant frequency startup mode of operation.

As mentioned above, in the start-up mode of operation, the applied current limit may be low, at least initially. Thus, when the low-side switch is on, the current may fall to zero or become negative before the high-side switch turns on in response to the next clock pulse. Thus, as mentioned above, the method may involve switching off the low-side switch before the current becomes negative.

The first threshold value and/or the second threshold value may increase over time during a startup mode of operation. The first threshold sets the peak current during the startup mode of operation, and by increasing this threshold over time, the maximum current drawn from the supply (supply) may be limited. Preferably, both thresholds are increased during the startup mode of operation. By increasing both the first and second thresholds over a period of time, the voltage output of the converter may increase over time and may control the peak current output and the average current output. Conveniently, the first threshold and/or the second threshold is increased in a series of steps. In one embodiment, the initial level of the second threshold may be zero, i.e.: the inductor current must fall to zero before the high-side switch can resume turning on.

The first threshold value and/or the second threshold value may be gradually increased during the start-up operation mode until the output voltage reaches the set output voltage threshold value. Once the output voltage threshold is reached, the converter may transition to a normal operating mode. In the normal operation mode, the voltage loop control is activated.

The normal operating mode may be a peak current mode or a valley current mode. Accordingly, the method may involve turning on the high-side switch in response to a clock signal during a start-up mode of operation, and subsequently turning on the low-side switch in response to the clock signal in a valley current normal mode of operation.

Once the normal operating mode is reached, current limiting may be disabled. In other words, the current limit may be applied only during the startup mode of operation. However, the method may involve applying the new first and second thresholds during normal operation to provide overcurrent/short circuit ground protection.

In some embodiments, the second threshold may be set at a level below the first threshold, but this is not necessary. The second threshold may be set at the same level as the first threshold or at a higher level than the first threshold (in terms of actual inductor current). One or both of the first threshold and the second threshold may be varied in response to an operating condition of the converter.

In some embodiments, if the high-side switch is turned off based on the first threshold, turning on of the high-side switch is inhibited based on only the second threshold. In other words, the valley current threshold is only performed when the peak current limit has been reached. However, in other embodiments, these thresholds are independently monitored and if the second signal is above the second threshold, turning on the high side switch is inhibited regardless of whether the peak current limit has been previously reached.

At least one of the first threshold and the second threshold may vary according to at least one of: a high side supply voltage, an output voltage of the converter, a switching frequency, and an inductance of the inductor. Thus, the threshold may be set based on the high side supply voltage, i.e. the input voltage of the converter. Especially for battery powered devices, the input voltage may vary over time, so the threshold may be adjusted accordingly. Further, the threshold may be adjusted based on the output voltage, such as indicated by a voltage select signal. The threshold may also vary with the switching frequency and/or the inductance value of the inductor. The switching frequency may be fixed for a particular device or may be variable in use. The inductance of the inductor is a fixed aspect of the device, but converters of the same design may use different inductors, so the ability to set the threshold based on inductance and/or operating frequency is advantageous.

In another aspect of the present invention, there is provided a DC-DC converter including: an inductor operatively connected between the first node and the output node; a high side switch operatively connected between a high side supply input node and the first node; a low side switch operatively connected between a low side supply input node and the first node; a switch control circuit operable to control the high-side switch and the low-side switch; wherein the switch control circuit comprises: a first current limiting circuit for turning off the high side switch if a first signal indicative of current in the inductor exceeds a first threshold; and a second current limiting circuit for inhibiting turning on the high side switch if a second signal indicative of current in the inductor exceeds a second threshold.

The high-side switch may comprise a P-channel transistor and the first current limiting circuit may comprise a first comparator arranged to compare a source-drain voltage of the P-channel transistor with the first threshold. The low side switch may comprise an N-channel transistor and the second current limiting circuit may comprise a second comparator arranged to compare a source-drain voltage of the N-channel transistor with the second threshold.

The switch control circuit may be configured to control turning on of the high-side switch based on a clock signal in a startup mode of operation.

Preferably, the first current limiting circuit is configured to increase the first threshold over time in a start-up mode of operation and/or wherein the second current limiting circuit is configured to increase the second threshold over time in the start-up mode of operation.

The switch control circuit may be configured to: turning off the low-side switch if the current in the inductor reaches a third threshold while the low-side switch is on.

The switch control circuit may be configured to provide valley current mode control in a normal operating mode.

In yet another aspect of the invention, there is provided a method of controlling a DC-DC converter, the DC-DC converter comprising an inductor operatively connected to a PMOS switch and an NMOS switch, the method comprising: monitoring the PMOS switch current against a PMOS current limit; if the current limit of the PMOS is reached, the PMOS switch is turned off; monitoring the NMOS switch current against an NMOS current limit; if the NMOS current limit is reached, keeping the NMOS on and prohibiting the PMOS switch from being turned on.

In another aspect of the present invention, there is provided a method of turning on a DC-DC converter, including the steps of: setting a first current limit and a second current limit; receiving a clock signal comprising a series of clock pulses; and monitoring at least one signal indicative of current in the converter; wherein the method comprises the repeated steps of: turning off the high-side switch and keeping the high-side switch off when the at least one signal indicative of the current in the inductor reaches the first current limit until at least a next clock pulse, and subsequently turning on the high-side switch after the at least one signal indicative of the current in the inductor reaches the second current limit.

In the method, in the first mode of operation, the step of subsequently turning on the high-side switch may comprise: turning on the high-side switch at a first clock pulse following a time when the at least one signal indicative of the current in the inductor reaches the second current limit.

In a second mode of operation, the step of subsequently turning on the high side switch may comprise: turning on the high side switch after the next clock pulse or when the at least one signal indicative of current in the inductor reaches a later occurrence among the second current limits.

The method may comprise: operating in the first mode of operation during at least a first period of time and operating in the second mode of operation during at least a second period of time.

The method may further comprise the steps of: the low-side switch is turned off if the inductor current is below a third threshold.

At least one of the first current limit and the second current limit may increase over time.

In yet another aspect of the invention, there is provided a method of providing a current limit for a DC-DC converter comprising a high-side supply switch and a low-side supply switch, the method comprising: providing a first control signal for turning on the high-side supply switch in normal operation; and monitoring current in the inductor against a first threshold when the high side supply switch is on, and monitoring current in the inductor against a second threshold when the high side supply switch is off; wherein the high side switch is turned off if the first threshold is exceeded, and wherein the high side switch is inhibited from being turned on when the second threshold is exceeded; and wherein the high-side switch is turned on in response to the first control signal when the high-side switch is not inhibited from turning on.

Yet another aspect of the present invention provides a method of starting a DC-DC converter, including: applying a first current limit to provide a peak current limit by turning off the high-side supply switch; and applying a second current limit to inhibit turning on the high-side supply switch; wherein the high-side supply switch is turned on in response to a constant frequency clock signal when the high-side supply switch is not inhibited from turning on.

The DC-DC converter described above may be implemented in an integrated circuit, such as a power management integrated circuit. The described DC-DC converter may be implemented in, for example, the following electronic devices: a portable computing device, a laptop computer, a personal digital assistant, a personal media player, an MP3 player, a portable television, a mobile communication device, a mobile phone, a navigation apparatus, a GPS device, or a game console.

The present invention relates generally to current limiting to provide short-circuit protection during start-up and normal operation of a DC-DC converter, especially in valley current mode control.

The problem of excessive output voltage overshoot and excessive inrush current at start-up of a (valley current mode) DC-DC converter is solved by: the voltage control loop is omitted and the output voltage is ramped up with a current controlled output stage having a positive current limit and a negative current limit set to (a sequence of) values that increase over time. The circuit may also be used for current limiting/short circuit protection once in normal operation. The threshold may be increased in steps during the start-up mode or may be a ramped threshold. The same output stage can also be used in the normal mode, as in the start-up mode. The start-up mode may end once the output voltage reaches a predetermined threshold.

If the voltage threshold is not reached after a predetermined time, the converter may be disabled and a short circuit may be flagged.

The current may be sensed by the drain-source voltage of the power switch, and the current limit may be sensed by a comparator attached thereto. The current may be sensed in current mode by a current sense amplifier with a comparator at the output, or by a resistor and direct voltage measurement.

Once truncated, the PMOS cannot be enabled until the later of the next clock edge and the valley limit is reached.

Some of the starting current limit levels may be used based on V_INAnd V_OUTAnd (and L and f) are set.

The NMOS may be turned off if the inductor current is near zero.

Preferably, the start-up mode is combined with an error voltage compensation node (which is preset to transition to the nominal value required for normal control) to reduce voltage overshoot and undershoot.

Although useful in the startup mode of operation, current limiting may also be used in normal operation, with or without a PMOS limit trigger condition.

The invention will now be described, by way of example only, with reference to the following drawings, in which:

fig. 1 shows one typical arrangement of a DC-DC converter arranged to supply a processor circuit;

FIG. 2 shows a conventional DC-DC converter;

FIG. 3 shows inductor current and voltage waveforms during a single cycle in normal operation;

FIG. 4 illustrates a problem in a conventional current limiting scheme;

FIG. 5 illustrates the operation of one embodiment of current limiting according to the present invention;

fig. 6 shows an embodiment of a DC-DC converter according to the invention;

FIG. 7 illustrates one embodiment of current limits that may be applied during a startup mode of operation;

FIG. 8 illustrates an inductor current waveform during a first portion of a start-up mode of operation using the current limits illustrated in FIG. 7;

fig. 9 shows an inductor current waveform during a second portion of a start-up mode of operation using the current limits shown in fig. 7, wherein the duty cycle is less than 50%;

fig. 10 shows an inductor current waveform during a second portion of a start-up mode of operation using the current limits shown in fig. 7, wherein the duty cycle is greater than 50%;

FIG. 11 is a flowchart illustrating the steps of current limiting according to one embodiment of the present invention;

FIG. 12a is a flowchart illustrating the general steps in a startup mode of operation according to one embodiment of the present invention;

fig. 12b is a flowchart showing the switching control steps of the process shown in fig. 12 a.

As discussed above, fig. 2 shows a conventional DC-DC converter. As discussed above, in operation, the signal representative of the current in the inductor is associated with V_ERRORThe signals are compared to control switches 10 and 20.

The inductor current may be sensed using a series resistor in series with the inductor or a corresponding transistor. However, the use of such series resistors introduces an additional source of resistive power loss, thereby reducing the efficiency of the converter. Efficiency is an important consideration, especially for battery powered devices. Therefore, it is preferable to use a "lossless" sensing technique, such as sensing the drain-source voltage across the PMOS due to its on resistance (on resistance). This gives a voltage proportional to the PMOS current.

In operation of a conventional peak mode DC-DC converter, the PMOS switch is turned on at an edge of the clock signal 212. In a lossless current sensing approach, i.e., in an embodiment without a sense resistor, the drain-source voltage of the PMOS is monitored to derive a current signal proportional to the current through PMOS 10 and thus through inductor L. The current signal (appropriately scaled) is related to a threshold value V_ERRORThe signals are compared. When the current reaches the threshold, the PMOS is turned off by the switch driver 211 and the NMOS is turned on, i.e., the switching occurs at the peak of the inductor current. In practice, a slope-compensated ramp signal is applied to the current signal or the V before the comparison_ERROREither or both signals to prevent sub-harmonic oscillation(s). The effect is therefore that the current signal is compared with a threshold value that is ramped over each cycle.

The bandwidth of the current control loop is large, thereby producing a suitable pulse width on a cycle-by-cycle basis, while the bandwidth of the external voltage control loop is relatively small, so that a substantially static input voltage V can be assumed_ERRORTo analyze the current loopAnd (4) a way.

The terminal LX of the inductor L is switched to V for a part D of each clock cycle_INThe terminal LX of the inductor L is switched to ground for the remainder 1-D of each cycle. The average voltage at node LX is therefore D × V_IN. The output capacitor C1 is large enough so that the voltage V_OUTIs substantially constant in each cycle, so V_OUTThe average voltage at is also D V_IN. Thus, for V vs_INIs a small V_OUTDuty ratio D ═ V_OUT/V_INMay be small.

Also, clock frequencies tend to be faster, allowing the use of smaller value, smaller sized inductors, which further shortens the PMOS turn-on time, as well as the time available for sensing its current.

As mentioned before, it is difficult to control very short switching times. An alternative control mode therefore uses Valley Current Mode (VCM) control. In VCM, NMOS switch 20 is turned on at the clock edge and the current in the inductor is monitored during NMOS conduction. When the inductor current drops to V_ERRORThreshold (modified by slope compensation ramp) the NMOS is turned off and the PMOS is turned on, i.e. the switching is controlled by minimum inductor current or valley current. For short duty cycles, the on-time of the NMOS switch may be significantly longer than the PMOS switch, so valley current mode control may ease certain aspects of control of the DC-DC converter at low output voltages.

Fig. 3 shows the inductor current and voltage at the output terminal LX of the output stage during one period of a set of repeated periods. The solid line (solid curve)1001 shows the waveform for a larger average current, and the dashed line (dashled curve)1002 shows the waveform for a smaller current (assuming V is_INAnd V_OUTConstant). The upper part of fig. 3 shows the current curve at the node LX and the lower part of fig. 3 shows the voltage. In the first part of the cycle shown, i.e. at t₁And t₂Between NMOS and LX is close to ground (near ground), and the inductorIs held at V by an output capacitor_OUT. The current thus flows with a slope dI_L/dt＝V_OUTthe/L is reduced. During the second part of the cycle, i.e. at t₂And t₃While PMOS is turned on and the voltage at node LX is close to the supply source V_INAnd the other end of the inductor is held at V by an output capacitor_OUTSo that the current is at a slope dI_L/dt＝(V_IN-V_OUT) the/L increases. If the load current demand decreases, the current waveform remains at substantially the same slope, but moves downward to decrease the average current supplied to the capacitor and ultimately to the load, as shown by the dashed line 1002 representing a smaller average current. As shown in the lower part of FIG. 3, when passing this current, the voltage at LX does not really reach ground or V due to I.R drop for the conducting NMOS or PMOS_IN. For a converter with good efficiency, these I.R drops off with V_OUTThe comparison is small so that the current waveform is not greatly affected, but is exaggerated in fig. 3 for explanatory purposes.

DC-DC converters are usually provided with a current limiting circuit for limiting the maximum current delivered by the converter. This is to prevent the converter from delivering very high output currents in a current overload situation or a high current fault (e.g., a short circuit to ground situation). It will be appreciated that many situations can result in current overload, but without current limiting, a short to ground will typically result in a large current overload. Embodiments of the present invention will be described in terms of a short-to-ground scenario, but it should be understood that the present method and apparatus are applicable to any type of current overload or high current fault.

As mentioned above, when the PMOS switch is on, the current is at slope dI_L/dt＝(V_IN-V_OUT) the/L increases. However, in the case of short-circuit grounding, V_OUTMay be pulled low and may be zero or near zero. Thus, when the PMOS is on, the voltage drop across the inductor is about V_IN. Thus, when the PMOS switch is on, there is a very steep increase in the current. Conversely, when the NMOS switch is on, the inductor current is at a slopedI_L/dt＝V_OUTL is reduced, but V_OUTClose to zero and therefore there is a very gradual reduction in current.

Significant over-current flowing through a DC-DC converter can cause damage to circuitry in the power domain connected to the DC-DC converter, or damage to the converter itself. The over-current flowing through the inductor can cause the inductance to decrease destructively, which actually exacerbates the problem, as the current slope increases as the inductance decreases. If this situation persists, the increased over-current may cause the converter to fail. In some converters, even if the inductor is able to handle a certain overcurrent, other circuits, even wires, packages or pcb's, may be damaged by the large overcurrent.

Therefore, a current overload limit is typically applied to the DC-DC converter to limit the maximum current in the inductor in use. If the current reaches the current limit, the PMOS turns off and the NMOS turns on wherever in the cycle. As mentioned above, the current in the inductor can be determined by monitoring a dedicated sense resistor, but the presence of the sense resistor results in resistive losses in normal operation, thereby reducing the efficiency of the converter. Therefore, in some applications, non-destructive sensing is preferred.

In lossless type control, the inductor current when the PMOS is on is determined by monitoring the electrical properties of the PMOS when it is on. This, however, leads to a problem known as step stepping because PMOS current can only be determined when the PMOS is on, and there will be a finite time delay between turning the PMOS on, determining that the current is above the current limit, and then turning the PMOS off. The finite delay is caused by comparator propagation delay and the like. This effectively means that even if the inductor current is greater than the current limit when the PMOS is on, there will be a minimum period of time for the PMOS to be on before the PMOS can be turned off. According to V_INInductor inductance and clock frequency (i.e., the duration of each cycle), the following conditions may arise: the current increase during this minimum PMOS on period is greater than the subsequent remainder of the cycleThe current in the part due to the NMOS turning on decreases. The inductor current increases each cycle even though the current limit has been exceeded.

Fig. 4 illustrates the problem of this approach. Fig. 4 shows the current in the inductor operating in valley mode. The same problem occurs for converters operating in peak mode.

At time t_AA short circuit to ground condition occurs. For ease of explanation, as shown in fig. 4, the short-circuit grounding occurs at the moment when the NMOS turns off and the PMOS turns on. It is apparent, however, that short-circuit grounding may occur at any point in the cycle. With the PMOS on, since the voltage drop is equal to almost all V across the inductor_INThe inductor current increases rapidly. At time t_BThe current limit 4001 is reached. However, due to propagation delays and other circuit delays in the comparator, the PMOS switch is only subsequently at time t_CIs truncated. t is t_BAnd t_CThe time difference between is equal to t_min，t_minIs due to the PMOS minimum on period caused by the current limiting circuit. At point t_CThe PMOS is actually turned off, the NMOS is turned on, and the current begins to decrease. However, because there is only a small or no voltage across the inductor, the current decreases at a relatively low rate.

At time t_DAnd receiving the next clock pulse. In valley current mode, the clock pulse will control the PMOS to turn off and the NMOS to turn on in normal operation. In this case, the NMOS is already on and remains on. However, the voltage error may be relatively large (because the output voltage has been pulled low), so the PMOS may be at time t_EThe switch-on is relatively fast into the cycle. At this point, the inductor current is still above the current limit, but the current limit is only applied when the PMOS is on. When the PMOS is turned on, the associated comparator determines that the current is above the current limit and acts to turn off the PMOS. Again, however, the propagation delay means that the PMOS is not immediately truncated, but it is actually only at a subsequent time t_FIs truncated.Thus, again, there is an on period t_minDuring which more current is delivered. It can thus be seen that in this scheme the inductor current can be increased in each cycle, since the step of checking the PMOS current increases more current than decays in the remainder of the cycle.

Thus, in one embodiment of the invention, current limiting is provided by applying two current thresholds. The first threshold is the peak current limit imposed on the current when the PMOS is on. The second threshold is the valley current threshold applied when the PMOS is off. The valley current threshold is also used to control the PMOS, wherein if the current is greater than the valley current threshold, turn-on of the PMOS is disabled. It will of course be appreciated that the threshold referred to herein is a current limit threshold, different from the voltage error threshold V used in the current control loop to control the switching of the PMOS or NMOS_ERROR。

Thus, if the PMOS is on and reaches the peak current limit, the PMOS is turned off. However, if the current in the inductor is below the valley current threshold (at which point the PMOS will be turned on under normal operation), the PMOS will not be turned on subsequently.

The peak current limit is used as a limit and, as described above, if the PMOS is on and the current reaches the current limit, the PMOS is turned off, no matter at what point in the cycle. As mentioned, there is a propagation delay in the current limit circuit, which means that the PMOS is actually only turned off after a short time, but in general, when the peak current limit is reached, the PMOS is turned off as soon as possible.

As mentioned, the PMOS is turned off when the peak current limit is reached. At this time, the NMOS may be turned on to reduce the inductor current. For applying current limiting during normal operation, it is likely that reaching the peak current limit will turn off the PMOS and turn on the NMOS. In some cases, however (e.g., if the peak current limit is relatively low), reaching the peak current limit may cause the PMOS to turn off, but the NMOS may not necessarily turn on. If the NMOS remains off, current flows through the parallel path. As will be appreciated by those skilled in the art, NMOS devices typically have a parasitic body diode associated therewith. If the NMOS is not turned on and current flows through the inductor, the current will continue to flow through the body diode until the current reaches zero (the diode will not conduct reverse current). Thus, at low peak current limits, (e.g., usable in a start-up mode of operation as will be described below), reaching the peak current limit may cause the PMOS to be turned off and the inductor current to be allowed to reduce to zero by conduction through the body diode (or another discrete external diode specifically arranged to provide a parallel path). However, at higher current limits, it may not be desirable to have a large current through the body diode, so reaching the peak current limit may cause the PMOS to turn off and the NMOS to turn on.

The valley current threshold is preferably used as the threshold. When the current is above the valley current threshold, turn-on of the PMOS is disabled. However, when the valley current falls below the threshold, the PMOS may be turned on, depending on the normal operation of the converter. That is, the PMOS is not necessarily turned on as soon as the current falls below the valley current threshold.

In a converter operating in peak mode, the PMOS is normally turned on by the relevant clock edge of the clock signal, and as long as the inductor current signal is at V_ERRORThe PMOS remains on hereinafter (including slope compensation). Thus, in one peak mode implementation, if the PMOS is turned on in one cycle and turned off due to reaching a current limit, the NMOS will remain on at least until the next cycle, even if the inductor current is below the valley current threshold, because the turn on of the PMOS is controlled by the clock edge. However, if the inductor current is still above the valley current threshold at the next clock edge, then the PMOS is disabled from turning on until the current falls below the valley current threshold.

In one embodimentOnce the inductor current falls below the valley current threshold, the PMOS turn-on is no longer inhibited. In peak current mode control, this can therefore mean that the PMOS is turned on no matter at what point in the cycle the inductor current falls below the valley current threshold. Thus, in this embodiment, where turn-on of the PMOS is disabled, at the beginning of a cycle, the turn-on of the PMOS is not necessarily synchronized with a clock edge since the inductor current is above the valley current threshold. Once turned on, the PMOS remains on until the current in the inductor reaches V_ERROR(including slope compensation) or reach the peak current limit.

In another embodiment, the turn-on of the PMOS is always synchronized with the clock edge. Thus, once the inductor current (when the PMOS is off) falls below the valley current threshold, the PMOS turns on at the next relevant clock edge.

In a valley current mode converter, the PMOS is turned on based on the inductor current and the error voltage signal V_ERRORIs controlled. Thus, in a valley current mode converter, once the current falls below the valley current threshold, if the current signal is at V_ERRORThe PMOS will turn on hereinafter (including slope compensation). If the short-to-ground condition persists, it is likely that the PMOS will be turned on very shortly after the current falls below the valley current threshold, since short-to-ground would result in an artificially high duty cycle, but it should be noted that the current falling below the valley current threshold is nothing more than allowing the PMOS to be turned on — which essentially does not force the PMOS to turn on.

In all cases, the converter is preferably arranged so that the PMOS is turned on no more than once in a single cycle. In valley current mode converters, once the PMOS has turned on, it typically remains on until the end of the cycle. If the PMOS is on and reaches the peak current limit, the PMOS is turned off. If, in some embodiments, the inductor current then decays before the end of the cycleFalling below the valley current threshold, it is possible that the PMOS will return to the on state in the same cycle (because of the inductor current and V)_ERRORA slope compensated comparison between may indicate that the PMOS should be on). If the PMOS is turned on more than once in a cycle, very high frequency current oscillations can occur. For converters clocked by a fixed frequency, the fixed frequency nature of operation is lost. Further, the transducer is controlled worse and tones may appear. Thus, the converter may preferably be arranged such that if the PMOS is truncated in one cycle, it remains off until at least the next cycle. However, the skilled person will of course appreciate that it is possible to implement a converter in which the PMOS may be turned on more than once during a period.

Fig. 5 shows the operation of the converter of the present invention operating in valley current mode. When the PMOS is on, peak current limit 5001 is applied to the inductor current, and when the PMOS is off, valley current threshold 5002 is applied to the inductor current. In fig. 5, the peak current limit 5001 is the same as the current limit 4001 shown in fig. 4, and for ease of comparison, the current slope and comparator propagation delay are shown as the same as in fig. 4. In this embodiment, reaching the peak current limit causes the PMOS to turn off and the NMOS to turn on.

Again, a short to ground condition occurs at time t_AConsistent with the turn-on of the PMOS. The current thus ramps up rapidly until at time t_BThe peak current limit is reached. As mentioned above with respect to fig. 4, the propagation delay means that the PMOS is actually at time t_CIs cut off at time t_CIs the moment when the NMOS is turned on and the current starts to decrease. At time t_DThe next clock pulse is received and at time t_EThe PMOS will typically be turned on based on a duty cycle controller. However, at time t_ESince the inductor current is equal to or higher than the valley current threshold 5002, the PMOS is prohibited from turning on. Over the remainder of the cycle and (in the illustrated embodiment) over the next cycle, the inductor current is slowed downSlowly decreases until at time t_GA valley current threshold is reached. At this point in time, the PMOS turn-on is no longer disabled. As the short to ground condition continues, and the duty cycle controller is forced into a high duty cycle, the PMOS is at time t_HAnd then switched on after a very short time. When the turning on of the PMOS is disabled, the normal voltage and current control loop may still operate in the background, and thus there may already be a signal indicating that the PMOS should turn on. Reaching the valley current threshold is simply to disable the pending request so there is only minimal logic/driver delay before the PMOS turns on. The inductor current is thus again ramped up rapidly until the current limit is reached and the PMOS is again forced to trip. This pattern repeats as long as the short-circuit grounding continues.

It can thus be seen that by using two current thresholds (a peak current threshold, which is monitored when the PMOS is on and is taken as a limit, and a valley current limit, which is monitored when the PMOS is off and is taken as a threshold), overcurrent protection can be achieved and the step-stepping problem can be avoided.

Monitoring the inductor current against the valley current threshold when the PMOS is off avoids the step-step problem because the PMOS can never be turned on unless the inductor current has decreased below the valley current threshold. The peak current limit provides a current limit to limit the amount of current increase in any one cycle. If the valley current threshold is applied and the peak current limit is not applied, it is possible that the PMOS is turned on below the valley current threshold and remains on for a large portion of a cycle (as shown by dashed line 5003). Even during one cycle, the current may increase to a considerable level that may cause damage. Thus, the peak current limit provides a limit to the maximum current increase in any one cycle.

In some embodiments, the control circuit may be arranged to detect a behaviour indicative of a short-circuit ground or other current overload situation, for example the peak current limit being triggered several times in succession and/or the inductor current being above and remaining above the valley current threshold for several periods. Additionally or alternatively, the brown-out threshold may be used to detect that the output voltage is below a certain threshold, which may be programmed together with the target output voltage or separate from the target output voltage. The control circuit may disable the converter if a short-to-ground condition is detected.

It should be noted that although the valley current threshold limit is shown in fig. 5 as being lower than the peak current threshold, the valley current threshold may be set at the same level as or higher than the peak current threshold. The maximum inductor current achievable is determined by the following factors: the higher of the peak current limit or valley current threshold, and the amount of current increase during the propagation delay associated with a truncated PMOS once at or above the peak current limit. The first and second thresholds, i.e., peak current limit and valley current threshold, may be set accordingly.

It should be understood that terms such as "above" or "below" the threshold are used in this specification to refer to the actual inductor current being greater than the actual threshold. The actual comparison to the threshold or limit may be accomplished in a number of ways. For example, a signal inversely related to the inductor current may be compared to a threshold value, and the signal having a value less than the threshold value means that the inductor current is above the current limit. The terms "above" or "below" thus refer to the respective sides of the threshold, wherein "above" means that the threshold has been exceeded (the inductor current is greater than the relevant limit) when converted into the actual current in the inductor, and the term "below" means that the threshold has not been exceeded. It should also be noted that it is possible that the inductor current may be negative for at least a portion of the cycle, and thus the valley current limit may be a negative current limit. In terms of inductor current, an inductor current (or zero or positive current) that is less than the negative amount of the negative current limit is "above" the threshold. It will also be appreciated that, depending on the circuitry used, an inductor current exactly equal to the threshold may trigger the same response as a current above the threshold, or below the threshold. Thus, a current equal to the peak current threshold may trigger the PMOS to turn off and the NMOS to turn on. The inhibit signal caused by the valley current threshold may be stopped as soon as the inductor current equals the valley current threshold.

During normal operation of the converter, the peak current limit and the valley current threshold may be theoretically fixed, although variations in bias, temperature, etc. may cause variations in the actual limits applied. Alternatively, one or both of the peak current limit and the valley current threshold may be adjusted in use to provide different limits depending on the operating characteristics of the converter. However, in normal steady state operation, both the peak current limit and the valley current threshold are set above the expected peak and valley currents.

In some embodiments, the effect of the valley current threshold, i.e., disabling the PMOS from turning on, may be implemented only in response to the triggering of the peak current limit. In one embodiment, where the peak current limit is set at a level that is the same as or higher than the valley current threshold, it may be assumed that if the peak current limit is reached and the PMOS is subsequently turned off, the current when the NMOS is turned on will be greater than the valley current threshold. A disable PMOS signal (or a disable flag state set) may therefore be inserted that disables the PMOS from turning on in response to the peak current limit being reached. The inductor current at which the PMOS is off is then measured against a valley current threshold until the valley current threshold is reached, at which time the disable signal is disabled (or the flag state is cleared), thereby allowing the PMOS to turn on again. In this manner, the valley current threshold is only used to disable the turn-on of the PMOS after the PMOS turns off by reaching the peak current limit.

However, in other embodiments, the peak current limit and the valley current threshold are applied independently, wherein turning on the PMOS is inhibited if the current is above the valley current threshold, even if the PMOS is turned off as part of the normal control mode rather than being truncated by reaching the peak current limit. This avoids the following fault condition occurring: if the PMOS is on for a very short time, the peak limit detection circuit may not have time to trigger in the normal control mode. In such a case, the current at which the PMOS is on may be above the peak current limit, but because the PMOS has such a small on period, the peak current limit is not triggered. Even such short on-times can cause the current to increase to unacceptably high levels cycle by cycle. By ensuring that the PMOS is inhibited from turning on when the inductor current is above the valley current threshold, such high current situations are avoided even when the peak current limit is not triggered.

The current in the inductor when the PMOS is on is preferably determined by measuring the electrical characteristic of the PMOS switch when it is on. As mentioned above, the source-drain voltage of the PMOS, when on, is proportional to the current flowing in the PMOS, and thus proportional to the current in the inductor. The current in the inductor when the PMOS is off is preferably determined by measuring the electrical characteristics of the NMOS switch (i.e., the source-drain voltage of the NMOS). The invention therefore applies a lossless technique to determine the current in the inductor.

Under relatively high current loads, most DC-DC converters operate in Continuous Conduction Mode (CCM), where there is always current flowing in the inductor and one of the PMOS and NMOS is always on for a portion of the cycle (ignoring a very short time in the switching step, where the turn-off of one switch is staggered from the turn-on of the other switch to avoid forming a secondary V_INA direct path to ground). Thus, by monitoring the PMOS when the PMOS is on and the NMOS when the NMOS is on, the current in the inductor is always effectively monitored. Some DC-DC converters can also operate (operable) in a mode called Discontinuous Conduction Mode (DCM), in which the NMOS is turned off before the PMOS turns on, to prevent the current in the inductor from becoming too negative. The negative current in the inductor effectively discharges charge from the output to ground, thus reducing the efficiency of the converter at low current demands.

In a short-to-ground situation, the current demand will increase apparently, so the converter will likely start to operate in CCM, so the current in the inductor can be monitored throughout each cycle by monitoring the current through the PMOS and/or through the NMOS. However, if a low current limit is to be applied to cause the converter to operate in the DCM regime, it will be appreciated that the current information is actually lost when the NMOS is off.

If there is still current in the inductor at the moment the NMOS is turned off, the current will flow through a parallel path, e.g. a parasitic body diode associated with the NMOS. As mentioned above, an NMOS transistor switch will typically have an intrinsic parasitic drain-bulk (drain-bulk) diode associated with it. When the NMOS is on, the diode shunts to ground. However, if the NMOS device is turned off and current still flows from ground to the drain node, the parasitic diode may turn on and allow current to flow until the inductor current reaches zero. Once the inductor current reaches zero, the diode will cut off and it will not conduct a reverse current.

In some embodiments, a separate diode (or other unidirectional current device) may be provided in parallel with the lower switch 20 to control the current when the lower switch is off. The discrete diode may be arranged to allow forward current flow when the lower switch is off (before the PMOS is on), but to prevent current reversal in the inductor. Any suitable diode may be used, such as a low drop diode (lowdrop diode) or a schottky diode.

In any case, however, any current through the parallel path that occurs when the NMOS is off cannot be determined by monitoring the source-drain voltage of the NMOS.

In DCM, the NMOS is turned off at near zero inductor current. Therefore, the truncation of the NMOS can effectively be taken as an indication of zero current for the purpose of applying a current limit. Additionally or alternatively, the valley current threshold may be set to be not lower than the threshold at which the NMOS is turned off, so that the valley current threshold is always reached before the NMOS is turned off. In this way, monitoring the NMOS while it is on is sufficient to allow detection of when the valley current threshold is reached.

Fig. 6 shows a DC-DC converter circuit according to an embodiment of the invention. Elements similar to those shown in fig. 2 are labeled with the same reference characters.

For example, in a similar arrangement to that described above with respect to fig. 2, the converter shown in fig. 6 has a PMOS switch 10 and an NMOS switch 20 connected on either side of the node LX. A voltage feedback loop from the output node 203 is fed back to the error amplifier 206 via the programmable level shifter 204 to provide a voltage error signal V to the duty modulator 210_ERROR. The current sense circuit 209 provides a current sense signal ISNS to the duty cycle modulator, which also receives a slope compensation signal from a slope compensation ramp generator 213.

The duty modulator 210 receives these signals and the clock signal 212 generates a pulse width modulated signal PWM to drive the switch driver 211 to operate the PMOS and the NMOS.

In the circuit shown in fig. 6, the current sensing circuit is arranged to monitor the source-drain voltage when the NMOS is on. The circuit shown in fig. 6 thus uses a lossless current sensing method and can operate in valley current mode. Those skilled in the art will appreciate that in valley current mode, the PMOS is turned off and the NMOS is turned on, and ISNS and V are turned on in response to a clock signal_ERRORThe comparison (including the slope compensation signal VISLP) determines when the PMOS is turned on in one cycle.

Fig. 6 also includes a peak current limit monitoring circuit 601 and a valley current threshold monitoring circuit 602. The peak current limit circuit may be implemented by a simple comparator that compares the PMOS drain-source voltage to a programmed voltage threshold (as shown in fig. 6), or alternatively using a current sense amplifier followed by a current comparator or a resistor and voltage comparator. Similarly, the valley current threshold monitor may comprise a simple comparator that compares the NMOS source-drain voltage to a suitable limit, as shown, but other arrangements, such as a current sense amplifier, may also be implemented. The current sense amplifier may be used to generate the current sense signal ISNS and a signal to be used to monitor the valley current threshold, but in some embodiments it is preferred to employ a separate monitoring circuit for the valley current threshold, as shown.

In operation, the peak current limit circuit monitors the source-drain voltage of the PMOS (when on), which is proportional to the current flowing through the PMOS, with an appropriate voltage level. If the source-drain voltage crosses the voltage threshold, this indicates that the current through the PMOS, and thus the current through the inductor, has reached the current limit. At this point the output ilipos of the comparator changes from low to high (or vice versa) and the duty modulator acts to switch off the PMOS switch 10 and switch on the NMOS switch 20.

The valley current threshold circuit acts in a similar manner, comparing the NMOS source-drain voltage (when on) to an appropriate voltage threshold, and generating an output signal iliminthr, which indicates whether the current is above or below the associated threshold. Duty cycle modulator 210 receives the iliminthr signal from the valley current threshold circuit and does not turn on the PMOS during any period in which the signal indicates that the inductor current is greater than the threshold.

Although fig. 6 shows a valley current mode DC-DC converter, it will be appreciated that the current limiting described above can be implemented as easily as a converter operating in peak current mode. As shown in fig. 6, the current limiting circuit may be separate from any current sensing circuit, and since both the PMOS current and the NMOS current are monitored, the control mode in normal operation has no effect on the current limiting arrangement.

However, as mentioned above, valley current mode converters may be particularly advantageous in situations requiring a low output voltage, since the control of the valley current makes it easier to achieve a small duty cycle. In such a VCM converter, it may be advantageous to operate in DCM, where the NMOS is turned off before the PMOS is turned on, to prevent significant negative currents. Thus, the embodiment shown in fig. 6 has a zero crossing detection circuit 603 for monitoring the source-drain voltage of the NMOS and generating a signal ILIM _ ZC when the source-drain voltage reaches a threshold Iped to cause the duty modulator 210 to turn off the NMOS. The threshold Iped is set at a level such that the inductor current does not become negative, allowing for voltage bias and propagation delay. Therefore, the NMOS will typically turn off at some small positive current. As mentioned above, the current then flows through a parasitic diode until the current drops to zero, at which point the parasitic diode stops conducting and the current in the inductor remains at zero until the PMOS turns on.

To allow current loop control when the NMOS is off, the converter implementation shown in fig. 6 emulates the inductor current when the NMOS is off. This current is simulated by: the output of the current sense amplifier 209 is maintained at the value just before the NMOS cutoff when the NMOS is off, and also emulates the change in inductor current by adding an additional slope to the slope generated by the slope compensation slope generator 213. In response to the signal ILIM _ ZC indicating that the inductor current has reached the Iped threshold level, the duty modulator generates a hold signal that causes the current sense amplifier 209 to hold its current output value and an emulation signal that causes the slope compensation circuit to generate a slope that includes an additional slope component. This additional slope simulates the change in current in the inductor through the parallel path (e.g., the body diode of the NMOS) during turn-on. Thus, this additional slope is applied until the inductor current reaches zero, which is measured by N-diode detection circuit 604 detecting when the voltage at node LX crosses the threshold. When the NMOS is turned on and conducts, the voltage at node LX will be close to ground. When the NMOS is turned off but current flows through the parasitic diode of the NMOS, the voltage at node LX falls to the diode voltage below ground. However, node LX will rise (flyhigh) once the inductor current reaches zero, and therefore the zero crossing of the voltage at node LX can be used to determine that the inductor current has reached zero. Thus, at this time, the simulation signal is stopped, and the slope of the ramp wave generated by the slope compensation signal returns to the slope necessary for slope compensation.

FIG. 11 shows a flowchart illustrating the general steps of current limiting according to one embodiment of the present invention. For ease of explanation, the flowchart begins with turning on the high-side switch (i.e., PMOS 10) 1101. The high-side switch is turned on according to the normal control mode of the converter, for example in a peak-mode converter the turn-on of the high-side switch may be responsive to a clock edge, whereas in a valley-mode converter the high-side switch may be turned on by a voltage and current control loop. When the high-side switch is on, a first signal indicative of inductor current (i.e., a signal derived from the source-drain voltage of the PMOS) is monitored 1102. The first signal is compared 1103 to the peak current limit. If the first signal exceeds the first current limit at any time, the high-side switch is turned off 1104 and the low-side switch (e.g., NMOS 20) is turned on. At this point, a second signal indicative of inductor current (e.g., the source-drain voltage of the NMOS) is monitored 1107.

However, if the peak current limit is not exceeded, at some point the normal control will turn off PMOS 1105, i.e. the inductor current will have reached V in the peak converter_ERRORA threshold value, or the next clock edge will be received in the valley mode converter. The normal control loop will then continue to turn on the low-side switch 1106, and in this case, the second signal indicative of the inductor current will be monitored again.

The second signal is compared 1108 to the valley current threshold. If the second signal is above the valley current threshold, and so long as it remains above the threshold, then turning on of the high side switch is inhibited 1109. However, once the valley current threshold is reached, the high side switch may be turned on again 1101 according to normal control.

For DC-DC converters, in particular VCM DC-DC converters such as shown in fig. 6, the current limitation of the invention can be used in a new start-up mode.

One of the biggest technical challenges of valley current mode DC-DC converters is how to start up in the following way: excessive output voltage overshoot (caused by reset-up at start-up) is prevented, inrush current is minimized (since PMOS current is only indirectly controlled), and start-up is still allowed into full load (so that current cannot be limited only to "safe" values below normal current limits).

One advantageous start-up mode of the DC-DC converter may use two current thresholds in a similar way as described above, namely: the first threshold is a peak current limit and the second threshold is a valley current threshold. In the start-up mode, the voltage loop of the DC-DC converter is effectively ignored and the driver stage is controlled using the current loop until the output voltage V_OUTHas reached the set voltage threshold V_th. During this start-up mode, the current delivered increases with time.

By implementing a series of low peak current limits during the start-up period, the maximum current, and thus the average current, can be controlled, thereby providing control over the inrush current, which tends to result in less overshoot due to less current demand.

Furthermore, if V_ERRORThe start-up method also reduces voltage overshoot if the signal line is precharged during start-up to a voltage value close to the expected operating value.

The peak current limit may be increased in various ways, but in one convenient embodiment, the peak current limit is increased in several steps. This means that the difference between the inductor current and the load current may only be smaller than or equal to the size of the step during the start-up sequence. At the end of the start-up sequence, the current in the inductor will be close to the required load current, so the inductor current does not need to vary much to achieve regulation and overshoot is minimized.

By using two current limits that vary throughout the start-up sequence, an increased output current can be conveniently implemented: the first is the peak PMOS current limit, which is used to accurately limit the maximum input current even if the system is to become sub-harmonic; the second current limit is a valley NMOS current limit for improved control of the average output current.

The regulator may normally be provided with a clock during start-up. During the startup mode, the clock edge of the clock signal is used to determine when to turn on the PMOS. In a peak current mode converter, the clock signal controls the turn-on of the PMOS in normal operation, so the start-up mode uses the same overall control mode, but does not use a voltage loop to turn off the PMOS, but only a current loop. However, in valley current mode converters, the clock signal controls the turn-on of the NMOS in normal operation. The start-up mode of operation thus provides a significantly different start-up procedure than normal operation.

If the valley current mode converter is turned on using normal VCM control without any current limitation, then in the first cycle the NMOS will be turned off quite quickly and the PMOS will remain on for the remainder of the cycle. This behavior repeats over several cycles as the output voltage slowly increases, and the inductor current increases rapidly, resulting in large inrush currents and voltage overshoots. Similar behavior occurs in an unlimited peak current mode converter: during start-up, the output voltage will initially be low and therefore the duty cycle will be high. The conditions at start-up are similar in many respects to those prevailing in a short-circuit ground situation, and the present inventors have realised that the same technique can be used to provide effective current limiting in start-up mode as well as in steady state operation.

As mentioned, in the new start-up mode, the PMOS turns on in response to the appropriate edge of the clock pulse. In each operation period, when the PMOS current reaches the peak current limit threshold IPLIMIT and then becomes effective, the current control turns off the PMOS (and turns on the NMOS). Then, the NMOS is turned off at the next clock edge (unless the NMOS current has not fallen to the valley current threshold IVLIMIT and then comes into effect), in which case the PMOS is not turned on until the NMOS current falls to IVLIMIT. Thus, the peak current limit is used to control when the PMOS turns off and when the NMOS turns on. This limits the amount of current increase in any cycle. Preventing the PMOS from turning on when the inductor current does not decrease below the valley current threshold prevents the inductor current from increasing too quickly and provides control over the average current.

As mentioned above, the PMOS is preferably turned on at most once in any cycle. Thus, if the PMOS is turned off (because the peak current limit is reached) and the inductor current then falls to the valley current threshold before the end of the cycle, the PMOS remains off until the next cycle begins. At this point, the relevant clock edge will turn on the PMOS again.

In the first operating mode, the PMOS is always turned on in synchronism with the clock edge. In other words, the PMOS turns on only one clock edge after the inductor current reaches the valley current threshold. Thus, the PMOS turns on at the beginning of a cycle and remains on until the peak current limit is reached. At this point the PMOS is turned off and the NMOS is turned on. The inductor current then decays until a valley current threshold is reached, which may be one or more cycles later. The PMOS only resumes on at the next relevant clock edge.

In the second mode of operation, the PMOS is turned on as soon as the valley current threshold is reached (preferably subject to the requirement that the PMOS is turned on at most once in a cycle). Thus, if the PMOS is turned off and the inductor current subsequently falls below the valley current threshold in the same cycle, the PMOS turns on at the next clock edge. However, if the inductor current reaches the valley current threshold only in one subsequent cycle, the PMOS is turned on as soon as the valley current threshold is reached (i.e., at any time in the cycle).

In the first operating mode, the PMOS turn-on occurs only at the clock edge. This may result in a reduced frequency of operation because the converter may wait for a clock edge to turn on the PMOS. This does result in increased ripple in the output compared to the second mode of operation, although the second mode of operation will not consistently turn on the PMOS at the clock edge.

The start-up scheme may operate using either the first mode of operation or the second mode of operation. In one embodiment, one mode of operation may be used for one or more periods during the start-up scheme, while another mode of operation may be used for the remainder of the start-up period.

During the initial portion of the start-up mode, the current in the inductor may be low, and, especially if the PMOS is only turned on at a clock edge, there may be a period in which the inductor current reverses if the NMOS remains on. Thus, the NMOS can be turned off when the current is near zero to avoid NMOS current reversal and discharge the load. There are various configurations for turning off the NMOS to prevent negative current. For example, in the converter shown in fig. 6, the NMOS may be truncated using the zero crossing detection circuit 603 as described above, with a threshold Iped to ensure that there is no reverse current regardless of bias and propagation delay.

As mentioned above, the PMOS will have a minimum on-time due to propagation delays in the comparator and PMOS predriver, so the PMOS current can slightly overshoot. However, the minimum time is short compared to the clock frequency, so the overshoot will be small.

The startup mode of operation may operate at a constant frequency by controlling the PMOS to turn on in response to a clock signal and turning off the NMOS to prevent negative current. The constant frequency may be the same as the operating frequency of the converter during normal operation and may include a small amount of frequency jitter. The start-up mode thus provides a constant frequency start-up mode. Constant frequency operation reduces the chance of interference with other device functions because the operating frequency of the converter is known in advance and can be taken into account in the design of the apparatus. Furthermore, the moment the PMOS is turned on in a cycle is known, which allows to set the timing of other functions of the device accordingly, e.g. a device designer may wish to avoid sensitive detection/decision taking place within the device when the PMOS is turned on.

It will of course be appreciated that the converter may be operable at more than one constant frequency, which may be selectable depending on operating conditions. It should also be understood that the use of jitter provides for a controlled change in frequency as is known in the art, and thus the term constant frequency should be interpreted to include a conceptual (nominal) constant frequency to which a known amount of jitter is applied. It will also be appreciated that, in use, the actual switching frequency during at least part of the start-up process may be lower than the constant frequency. If the time it takes for the inductor current to decay from the peak current limit to the valley current threshold is greater than the duration of one cycle, the PMOS will not turn on every cycle. Constant frequency means a constant maximum frequency, i.e. the switch-on occurs at most once per cycle and is synchronized with the clock edge.

During the start-up process, the peak current limit and the valley current threshold increase over time such that the current delivered to the load increases and therefore the output voltage increases. The peak current limit may be increased in a series of steps. The valley current threshold may also be increased in steps, although the two thresholds need not be increased at the same time, and at any time one threshold may be increased while the other remains at its current level.

The current threshold may be increased a set number of times during the start-up process, for example the increase may occur for a set number of cycles in the start-up. Alternatively, a series of output voltage thresholds may be used, each output voltage threshold being reached triggering an increase in the current threshold. At least some of the current thresholds used during start-up may be fixed thresholds, or at least some of the current thresholds may be based on V_INAnd a target V_OUTTo be determined. One or both of the peak current limit and the valley current threshold may also be continuously increased over time, for example as a ramp over time.

Once V is_OUTWhen a specific output voltage threshold Vth is reached, the normal control loop is activated instead of the above-mentioned start-up mode (modulation), and the converter is switched to normal control. The output voltage threshold at the end of the start-up mode may be fixed or may be variable in dependence on the target output voltage, e.g. by a voltage selection signal V_SELAnd/or input voltage V_INAnd (4) determining.

In the normal control mode, the voltage error loop is activated and used to determine the appropriate duty cycle of the modulator. It should be appreciated that if the normal operating mode is a valley current operating mode, transitioning from the startup mode to the normal mode further includes: the PMOS is turned on in response to a clock signal to the NMOS is turned on by a clock signal.

As mentioned above, during initial start-up, the error amplifier output V_ERRORPreferably pre-biased to approach its final normal mode voltage. For example, as shown in FIG. 6, the preset circuit 605 may bias the compensation device 606 to be at V_ERRORA pre-bias voltage is provided on the signal line. This avoids any large transients when transitioning from start-up mode to normal voltage and current loop control, since when V is measured_OUTThe voltage error amplifier has slewed back into the maximum voltage by the time it ramps up from zero. Once V is_OUTUp to Vth, the pre-bias is switched off and the normal loop should take over without any large transients. The control circuitry may mark the status as out of regulator. For providing V_ERRORSuitable circuits for accurate pre-biasing of signal lines are described in our co-pending patent application (our reference: P113611GB00/P1236GB00 Preset).

The current limit applied during the start-up mode also provides protection against short-circuit grounding during start-up. In a short-to-ground condition, the peak inductor current will be limited because the P-channel power switch will not turn on until the inductor current has first reached the valley current limit. Even if the output is exactly zero volts, it may take the system a long time to recirculate the inductor current to reach the valley current limit before turning on the P-channel power switch again.

If V is within a given time during initial start-up_OUTWithout crossing the output voltage threshold Vth, the system can determine that there has been a short to ground and that the DC-DC will be cut off. The control circuit may be arranged to attempt to activate the converter again after a short rest. If the converter is cut off due to a speculative (induced) short to ground, the control circuit may mark the condition as out of regulator.

Fig. 7 shows a current graph during start-up mode for one embodiment, where eight peak current limit (IPLIMIT) levels are used. Obviously, a greater or lesser number is possible. The first four levels follow a predetermined pattern that is independent of the selected input and output voltages. The latter four levels are programmed (perhaps using look-up tables) with respect to input and output voltages according to a prediction of how much ripple current is expected.

The valley current limit IVLIMIT is adjusted over time with up to the same number of current limit steps as the peak current. The illustrated embodiment uses zero for the first four levels, IVLIMIT, and the remaining tracking peak current limit, IPLIMIT, to maintain a constant difference. Other embodiments may not maintain the difference constant.

In this embodiment, the converter operates in the first mode described above in the first four time slots (i.e., the periods in which the first four current limits are used) so that the PMOS is always turned on in synchronism with the clock edge. In the next four time slots the converter operates in the second mode of operation, i.e. the P-channel power switch 10 is turned back on when the inductor current crosses the later one of the lower current limit IVLIMIT and the next clock edge, i.e. the clock edge following the PMOS truncation. Once turned on, the P-channel power switch remains on for all time slots until the peak current limit IPLIMIT is reached.

By properly setting the peak current limit and the valley current limit, a maximum average current value, given by (IVLIMIT + IPLIMIT)/2, can be set for each particular time slot; because this value increases every time slot, the total maximum average output current during each time slot during the upstream phase (upper accesses) of the startup sequence increases in a monotonic manner to its normal operating limit.

Fig. 12a shows the basic steps of the startup mode of operation according to this aspect of the invention. The process starts 1201 and peak and valley current limits are set for the current time slot 1202. Initially, the time slot is time slot T1. The startup mode controls the switching 1202 of the PMOS and NMOS based on the peak current limit and the valley current limit, as will be described with reference to fig. 12 b. If the output voltage threshold Vth 1204 is reached at any time, the start-up mode is ended 1205 and the converter transitions to normal regulation. Otherwise, the switching control remains to the end of time slot 1206 (which may be, for example, based on the output voltage or duration), at which time the appropriate peak current limit and valley current threshold are set for the next time slot, and the process repeats.

Fig. 12b shows this handover control procedure. In response to receipt 1211 of the clock pulse, the PMOS is turned on at step 1212. The PMOS current is then monitored 1213 (by monitoring the signal derived from the source-drain voltage of the PMOS). If the current is below the peak current limit (as determined in step 1214), the PMOS remains on 1215. However, once the peak current limit is reached, the PMOS is turned off and the NMOS is turned on in step 1216. In step 1217, the NMOS current is monitored and if the NMOS current is detected as being very close to zero, the NMOS is turned off. In step 1218, the NMOS current is compared to the valley current threshold. If above the threshold, the PMOS remains off 1219. However, if the inductor current has reached the valley current threshold, then the process moves to step 1220. If this is no later than the next clock edge, i.e., there has not been another clock edge of interest since the PMOS was turned on, the flow proceeds to wait for the next clock edge at step 1201. However, if there is already at least one intervening clock edge of interest, the process varies 1221 according to time slot. For slots T1 through T4, the process waits until the next clock edge to turn on the PMOS (and to turn off the NMOS if it has not been turned off). However, at time slots T5-T8, as soon as the valley current threshold is reached, the PMOS is turned on and the NMOS is turned off.

Fig. 8 shows typical current waveform characteristics of the time slots T1 to T4 (i.e., when IVLIMIT is 0) if the under-voltage threshold Vth has not been crossed. The inductor current can be seen to charge from zero to the peak current limit I_PLIMITDischarged to zero, experiences a discontinuity (i.e., zero current), and then charges again. When the current is close to zero, the inductor current is prevented from becoming negative by turning off the NMOS. In this embodiment, it is clear that since the inductor is prevented from going negative and the valley current threshold is set at zero (or indeed at the threshold for turning off the NMOS to prevent current reversal), the PMOS is only inhibited from turning on when the inductor current is above this threshold, i.e. the inductor current being equal to this threshold means that the PMOS is no longer inhibited from turning on.

During time slots T1 through T4, the turning on of the P-channel power switch is synchronized with the clock edge. I.e. the PMOS is turned on only at the next clock edge following after the inductor current reaches zero. This means that the inductor current is usually discontinuous, i.e. there is a period of zero inductor current. This ensures that the maximum average inductor current, which is achieved in the case where the inductor current becomes almost continuous (i.e. boundary condition CCM), is I_PLIMIT/2。

In operation, the PMOS is turned on at a clock edge and remains on until a peak current limit I is reached_PLIMIT. The current decay during the NMOS on period may be slow enough that the current has not been reduced to zero until the next clock edge. If the PMOS were to resume turn-on at the clock edge, the current would increase further during the next cycle. As previously discussed, there may be an inherent minimum pulse width associated with the PMOS turning on, so the current still steps up regardless of the peak current limit, as described above.

However, the control scheme causes the PMOS to not turn on at the clock edge, but only at a clock edge (possibly after a number of cycles) after the current has reached the valley current threshold.

This situation is most likely to occur initially, due to V_OUTSmall, so the fading slope will be much smaller than the rising slope, (V)_in-V_out)/L～V_in/L＞＞V_out/L。

As described above, propagation delay and the like may mean that the PMOS actually only truncates after a short time after the relevant threshold is reached. This time delay is omitted in fig. 8 and fig. 9 and 10 for clarity. Similarly, when the NMOS is actually turned off, it is likely that some current will still be flowing and will flow through a parallel path, such as a parasitic body diode associated with the NMOS. During conduction through this parasitic body diode, the slope of the inductor current may change, but for clarity, fig. 8-10 show a constant slope. The change in slope does not affect the operation of the start-up scheme. As mentioned above, for the purposes of the start-up scheme, turning off the NMOS may be considered an indication that the inductor current is zero.

As mentioned above, in this embodiment of the startup mode of operation, the turn-on of the PMOS is always synchronized with the clock edge during the time slots T1 through T4. However, in time slots T5-T8, the PMOS turns on the later of the next clock pulse and the inductor current reaching the valley current threshold.

FIG. 9 illustrates exemplary current waveform characteristics for time slots T5-T8 where the inductor current is reduced to a valley current limit I before the end of each cycle if the under-voltage threshold has not been crossed and the P-channel power switch on duty cycle is less than 50 percent_VLIMIT。

It can be seen that the inductor current is from the valley current threshold I_VLIMITOr lower to peak current limit I_PLIMITAnd then discharged again. During the time slot, the current does fall toActing of I_VLIMITThe value is below. If the current does happen to reach zero at some point, the N-channel power switch will still be off as before.

Fig. 9 shows the case where the inductor current reaches the valley current limit in the same cycle as the PMOS cutoff. The PMOS is therefore turned on only at the next edge clock. It will be appreciated, however, that the lower limit I may not be reached if the current has not yet reached the end of the cycle_VLIMITThen in the subsequent cycle the inductor current falls to the lower limit I_VLIMITThe PMOS will turn on.

This is illustrated in fig. 10, which shows typical current waveform characteristics for time slots T5 through T8 if the under-voltage threshold has not been crossed and the P-channel power switch on duty cycle is greater than 50%.

It can be seen that the inductor current is from the valley current threshold I_VLIMITOr lower to peak current limit I_PLIMITAnd then discharged again.

Only some of the P-channel power switches have their conduction period coincident with the clock edge because, in some cases, the current in the inductor reaches the valley current threshold only part way through the subsequent cycle. The sub-harmonic current behavior is generally unimportant because it is generally more important to limit the output current under fault conditions than to leave its spectrum free of confounding components. A start-up mode of operation is implemented to limit the maximum current supplied during the start-up phase. Subharmonic behavior tends to reduce the average output current and therefore does not represent a problem during start-up.

If the current happens to reach zero at some point, the N-channel power switch will switch off as before.

Note that it is strongly desirable and advantageous to have the PMOS switch on at a fixed frequency even during start-up, thus avoiding unpredictable interference with other components in the overall system, rather than using an asynchronous hysteresis mode (asynchronous hysteresis mode) with a switching frequency that varies greatly during and even after initial start-up.

Other advantages of the method are: it makes extensive use of existing circuits and gives excellent control while still allowing the sequence to end early when the load current is small (i.e. Vth may be reached even during T1 if there is no current load and the output capacitor is not very large) (refer to a scheme where VreI ramps up slowly on power up regardless of load (which may still suffer from reset clearing problems)).

Although described in a sequence of discrete steps, the method is also suitable for using a suitably designed ramp generating circuit to use ramp current limits rather than step current limits. It will be clear to a person skilled in the art how to design such a ramp circuit.

The start-up mode according to this embodiment of the invention may be applied to a peak current mode converter or a valley current mode converter. The current limit may be applied only during start-up mode, or a converter having such a start-up mode may also use the peak and valley current limits in normal operation to provide short-circuit grounding/over-current protection as previously described. In this case, once the converter leaves the start-up mode and transitions to normal operation, the peak current limit and valley current threshold may be reset to the appropriate limits for current limiting protection in normal operation.

Thus, once in the normal operating mode, the PMOS peak current limit sensor remains active (active), and if triggered turns on the NMOS to ramp down the current. In addition, the PMOS is inhibited from turning on again until the NMOS current has decreased to I_VLIMITThe following. Because of I_VLIMITAbove the normal valley current threshold, so under normal conditions this has no effect on normal operation (perhaps a small amount of additional delay can be saved due to the extra logic). As above, this may lead to sub-harmonic oscillation once the PMOS peak current limit has been triggered, but the resulting loss of spectral control is insignificant, as this is a fault mode condition.

It is also possible to operate the main loop, in which the NMOS current has been reduced to I until it is in normal operation_VLIMITOnly then is the PMOS allowed to turn on, regardless of whether the PMOS current limit has been triggered. Again, in most cases, this has no effect, since the NMOS current is usually at I_VLIMITThis is found to help limit operation in some situations, however. A comparator circuit that compares the PMOS current to the peak current limit will have a particular logic and associated propagation delay, with the result that there will be a minimum on period for the PMOS for the current limit to trigger. If the operating conditions are: in the normal control mode the PMOS is on for a period of time in a cycle shorter than the minimum on period, the PMOS peak current limit is not triggered in the cycle even if the PMOS current is above the current limit. This behavior may repeat for some cycles if there is no independent valley current threshold, where the current increases above the peak current limit but the peak current limit is never triggered. Having a separate valley current threshold prevents this behavior because turning on the PMOS would be inhibited if the inductor current was above the valley current threshold, even if the peak current threshold had not been triggered. This of course also has a minimum on period associated with the NMOS turning on to allow the valley current threshold to be determined, but clearly in the case where the PMOS is on for a very short time, there will be much time to determine the inductor current when the PMOS is off.

Although the above embodiments have been described with respect to a DC-DC buck converter, embodiments of the present invention may be generally used for a switching regulator. The switching regulator may be part of a power management device, such as a power management integrated circuit (i.e., PMIC). Embodiments of the present invention may be used for power management of subsystems of any form of electronic device, whether having a single power supply or multiple power supplies, and whether portable or not. However, embodiments of the present invention are particularly applicable to portable devices, such as: mobile computing devices, such as laptop computers, netbook computers, PDAs, and the like; mobile communication devices such as radiotelephones, cellular telephones, mobile electronic mail devices, and the like; personal media players such as MP3 or other audio players, personal radios, video players; portable video game consoles and devices; personal navigation devices, such as satellite navigators and GPS receivers, whether in-vehicle or handheld or any other portable or battery-powered device.

It should be noted that the above-mentioned embodiments illustrate rather than limit the invention, and that those skilled in the art will be able to design many alternative embodiments without departing from the scope of the appended claims. The word "comprising" does not exclude the presence of elements or steps other than those listed in a claim, "a" or "an" does not exclude a plurality, and a single processor or other unit may fulfil the functions of several units recited in the claims. Any reference signs in the claims shall not be construed as limiting the scope of the claims.

Claims (41)

1. A method of current limiting in a DC-DC converter, comprising:

monitoring whether a first signal indicative of current in the converter is above a first threshold when a high side switch is on;

turning off the high-side switch if the first signal is above the first threshold;

monitoring whether a second signal indicative of current in the converter is above a second threshold when the high-side switch is off; and

and if the second signal is above the second threshold, forbidding to turn on the high-side switch.

2. The method of claim 1, comprising the steps of: turning on a low side switch if the first signal is above the first threshold.

3. The method of claim 2, wherein when the low-side switch is on in response to the first signal being above the first threshold, the low-side switch remains on until the high-side switch is on or until a low-side cutoff control signal is received.

4. The method according to any of the preceding claims, further comprising the step of: monitoring whether the second or third signal indicative of current in the converter is below a third threshold when the low side switch is on, and generating a low side cutoff control signal if the third signal is below the third threshold.

5. The method of any of claims 1 to 4, wherein the high-side switch is turned on in response to a first control signal when turning on of the high-side switch is not disabled.

6. The method of claim 5, wherein the first control signal is derived from a clock signal.

7. The method of claim 6, wherein the clock signal has a constant frequency.

8. A method according to any preceding claim, wherein the method is used during a start-up mode of operation.

9. The method of claim 8, wherein during the startup mode of operation, a voltage loop of the converter is ignored.

10. The method of claim 8 or 9, wherein at least one of the first threshold and the second threshold increases over time during the startup mode of operation.

11. The method of claim 10, wherein the first threshold and/or the second threshold is increased in a plurality of steps.

12. The method of claim 10 or 11, wherein an initial threshold level for the second threshold is substantially zero current during a start-up mode.

13. The method according to any of claims 8 to 12, comprising: operating in a start-up mode of operation until the output voltage of the converter exceeds an output voltage threshold, and thereafter operating the DC-DC converter in a normal mode of operation.

14. The method of claim 12, wherein the converter is inhibited if the output threshold is not reached within a first time period after a start-up mode begins.

15. A method according to any one of claims 1 to 5 or 8 to 14, wherein in a normal mode of operation, the converter operates in a valley current mode control mode.

16. The method of claim 15, wherein in a normal operating mode, the second threshold is set above an expected operating valley current.

17. A method according to any preceding claim, wherein the step of inhibiting the high side switch from being turned on in response to the second signal exceeding the second threshold is performed only if the low side switch has been turned on in response to the first signal exceeding the first threshold.

18. A method according to any preceding claim, wherein the first signal is determined from an electrical property when the high side switch is on and the second signal is derived from an electrical property when the low side switch is on.

19. The method of any preceding claim, wherein at least one of the first and second thresholds varies in accordance with at least one of: a high side supply voltage, an output voltage of the converter, a switching frequency, and an inductance of the inductor.

20. A DC-DC converter comprising:

an inductor operatively connected between the first node and the output node;

a high side switch operatively connected between a high side supply input node and the first node;

a low side switch operatively connected between a low side supply input node and the first node;

a switch control circuit operable to control the high-side switch and the low-side switch;

wherein the switch control circuit comprises:

a first current limiting circuit to: if indicating a first of the currents in the inductor

The high-side switch is switched off if the signal exceeds a first threshold value; and

a second current limiting circuit to: disabling turning on the high-side switch if a second signal indicative of current in the inductor exceeds a second threshold.

21. A DC-DC converter as claimed in claim 20 wherein the high side switch comprises a P-channel transistor and the first current limiting circuit comprises a first comparator arranged to compare a source-drain voltage of the P-channel transistor with the first threshold value.

22. A DC-DC converter as claimed in claim 20 or 21 wherein the low side switch comprises an N-channel transistor and the second current limiting circuit comprises a second comparator arranged to compare a source-drain voltage of the N-channel transistor with the second threshold.

23. A DC-DC converter according to any of claims 20 to 22, wherein the switch control circuit is configured to control the turn-on of the high-side switch based on a clock signal in a start-up mode of operation.

24. A DC-DC converter as claimed in any of claims 20 to 23, wherein the first current limiting circuit is configured to increase the first threshold over time in a start-up mode of operation, and/or wherein the second current limiting circuit is configured to increase the second threshold over time in the start-up mode of operation.

25. A DC-DC converter according to any of claims 20 to 24, wherein the switch control circuit is configured to: turning off the low-side switch if the current in the inductor reaches a third threshold while the low-side switch is on.

26. A DC-DC converter according to any of claims 20 to 25, wherein the switch control circuit is configured to provide valley current mode control in the normal mode of operation.

27. A method of controlling a DC-DC converter, the DC-DC converter including an inductor operatively connected to a PMOS switch and an NMOS switch, the method comprising:

monitoring the PMOS switch current against the PMOS current limit;

if the current limit of the PMOS is reached, the PMOS switch is turned off;

monitoring the NMOS switch current against the NMOS current limit;

if the NMOS current limit is reached, the NMOS switch is kept on and the PMOS switch is prohibited from being turned on.

28. A method of turning on a DC-DC converter, comprising the steps of:

setting a first current limit and a second current limit;

receiving a clock signal comprising a series of clock pulses; and

monitoring at least one signal indicative of current in the converter;

wherein the method comprises the repeated steps of:

when the at least one signal indicative of the current in the inductor reaches the first current limit, turning off the high-side switch and keeping the high-side switch off until at least a next clock pulse, an

The high-side switch is then turned on after the at least one signal indicative of current in the inductor reaches the second current limit.

29. The method of claim 28, wherein in a first mode of operation, the step of subsequently turning on the high-side switch comprises: turning on the high-side switch at a first clock pulse following a time when the at least one signal indicative of the current in the inductor reaches the second current limit.

30. A method according to claim 28 or 29, wherein in a second mode of operation, the step of subsequently turning on the high side switch comprises: turning on the high side switch when the next clock pulse or the at least one signal indicative of current in the inductor reaches a later occurrence among the second current limits.

31. A method according to claim 30 when dependent on claim 29, wherein the method comprises: operating in the first mode of operation during at least a first period of time and operating in the second mode of operation during at least a second period of time.

32. The method according to any one of claims 28 to 31, further comprising the step of: the low-side switch is turned off if the inductor current is below a third threshold.

33. A method according to any one of claims 28 to 32, comprising the steps of: increasing at least one of the first current limit and the second current limit over time.

34. A method of providing a current limit for a DC-DC converter, the DC-DC converter including a high side supply switch and a low side supply switch, the method comprising:

providing a first control signal for turning on the high-side supply switch in normal operation; and

monitoring current in the inductor against a first threshold when the high-side supply switch is on, and monitoring current in the inductor against a second threshold when the high-side supply switch is off;

wherein if the first threshold is exceeded, the high-side switch is disabled, and

wherein if the second threshold is exceeded, disabling turning on the high-side switch;

and wherein the high-side switch is turned on in response to the first control signal when the high-side switch is not inhibited from turning on.

35. A method of starting a DC-DC converter, comprising:

applying a first current limit to provide a peak current limit by turning off the high-side supply switch; and

applying a second current limit to inhibit turning on the high-side supply switch;

wherein the high-side supply switch is turned on in response to a constant frequency clock signal when the high-side supply switch is not inhibited from turning on.

36. A power management integrated circuit comprising a DC-DC converter according to any of claims 20 to 26.

37. An electronic device comprising a DC-DC converter according to any of claims 20 to 26, or comprising a power management integrated circuit according to claim 36.

38. The electronic device of claim 37, wherein the device is one of: portable computing devices, laptops, personal digital assistants, personal media players, MP3 players, portable televisions, mobile communication devices, mobile phones, navigation devices, GPS devices, game consoles.

39. A DC-DC converter as hereinbefore described with reference to figure 6 of the accompanying drawings.

40. A current limiting method as hereinbefore described with reference to figures 5 and 11 of the accompanying drawings.

41. A method of starting a DC-DC converter as hereinbefore described with reference to figures 5, 7-10, 12a and 12b of the accompanying drawings.