HK1133334B - Efficient clock calibration in electronic equipment - Google Patents

Description

Efficient clock calibration in electronic devices

Technical Field

The present invention relates to clock calibration in electronic devices, and more particularly, to clock calibration in communication devices.

Background

There are a variety of digital communication systems, some currently existing and some still under development. The digital communication system includes: time Division Multiple Access (TDMA) systems, such as cellular radiotelephone systems that comply with the global system for mobile communications (GSM) telecommunications standard and its improvements (e.g., GSM/EDGE); and Code Division Multiple Access (CDMA) systems such as cellular radiotelephone systems that comply with IS-95, CDMA 2000, and wideband CDMA (wcdma) telecommunications standards. Digital communication systems also include "hybrid" TDMA and CDMA systems, such as cellular radiotelephone systems that comply with the Universal Mobile Telecommunications System (UMTS) standard, which specifies third generation (3G) mobile systems being developed by the european telecommunications standards institute (ETS I) within the International Telecommunications Union's (ITU) IMT-2000 framework. The third generation partnership project (3GPP) promulgates the UMTS standard. High speed downlink packet data access (HSDPA) is an evolution of WCDMA specified in Release 5 version of the 3GPP WCDMA specification. The 3GPP has begun considering the next major step or evolution of the 3G standard (sometimes referred to as super 3G- "S3G") to ensure long-term competitiveness of 3G.

Other types of digital communication systems allow devices to cooperate with each other via a wireless network. Examples include Wireless Local Area Network (WLAN) and BluetoothAn apparatus.

Common to these different systems is the need to maintain accurate timing. In modern radio transceivingDevices (e.g., WCDMA, GSM, and S3G phones and WLAN and BluetoothDevice), two different clocks are used: a System Clock (SC) and a Real Time Clock (RTC). The SC is typically a high frequency clock, running at several MHz, and is generated by a highly stable oscillator, which typically employs a temperature controlled crystal. The SC is used as a reference and is the frequency source for all radio related operations, such as Radio Frequency (RF) carrier synthesis. The crystals used for SC have an accuracy of about 20 parts per million (ppm). However, for cellular terminals, this accuracy is improved by locking the SC to the downlink signal transmitted by the mobile network base station. The SC is tuned to the downlink signal and therefore inherits a better stability of the clock reference used in the base station, which is about 0.5 ppm.

Stability of the SC is obtained at the cost of current consumption. To operate SC, several tens of milliamperes (mA) are required. In particular, the SC requires too much current when the transceiver is in a low power mode or idle mode where it sleeps most of the time. Thus, during the sleep state, the SC is turned off. To maintain timing during such sleep states, each modern transceiver also includes a non-reference clock, such as a Low Power Oscillator (LPO) or a Real Time Clock (RTC), which operates at much lower current consumption levels (tens to hundreds of microamps). The RTC usually runs at a much lower frequency than SC, typically a few kHz.

The RTC is used for several timing operations in the cellular terminal. It controls the sleep period and determines such things as when the terminal must wake up to monitor the paging control channel or scan for other broadcast control channels. The RTC also determines how long the synchronization of the uplink with the network can be maintained. Uplink synchronization is critical in time slotted systems, i.e. systems with a TDMA component, such as GSM and Long Term Evolution (LTE) of the newly developed 3G system (S3G). Due to the unknown round-trip propagation delay between the terminal and the base station, a Timing Advance (TA) control message needs to be sent to the terminal in order to align the timing of reception of its uplink transmissions with the timing of other uplink transmissions. Clock drift is a major cause of uplink timing mismatch and requires the terminal to send uplink bursts (bursts) frequently so that the base station can measure the timing misalignment (mismatch) and properly command the terminal to adjust its timing through a TA message.

The inherent stability of RTCs is very poor, typically from 50 to 100 ppm. However, the stability is improved by repeating the calibration. SC is used as a stable reference during calibration. Once the RTC is calibrated, it has a stability level close to that of the SC. Stability remained within a few ppm between calibration events.

US6,124,764 describes a calibration method using periodic page wakeup times. In particular, the LPO output signal is monitored during several monitoring windows M. These windows preferably correspond to the wake-up periods in the standby mode of the host system of which the LPO is a part. Other activities, such as page scanning (paging), may occur during the wake-up period. The results of the monitoring process are accumulated. Based on the accumulated results derived from the M monitoring windows, a decision of a correction scheme is determined for the next cycle containing another M monitoring windows.

A problem with conventional calibration techniques is that they require a relatively long calibration time. During calibration, the SC has to operate, which results in a high level of current consumption to be experienced. To limit power consumption, the calibration duty cycle is kept low. However, this means that there is a considerable time between successive calibration updates. During this time, the RTC may drift too far. Since the RTC controls the uplink timing, this drift requires frequent transmission of uplink bursts to the base station to support the TA procedure. When the terminal transmits an uplink burst, it consumes power, and this reduces the terminal standby time. Furthermore, all these uplink bursts increase the overhead in the network.

It is therefore desirable to provide clock calibration techniques and apparatus that overcome these problems.

Disclosure of Invention

It should be emphasized that the terms "comprises" and "comprising," when used in this specification, are taken to specify the presence of stated features, integers, steps or components, but the use of these terms does not preclude the presence or addition of one or more other features, integers, steps, components or groups thereof.

According to an aspect of the invention, the foregoing and other objects are achieved in methods and apparatuses that determine (ascirtin) a representative measurement indicative of a relative oscillation speed of a reference clock during a representative calibration period, wherein the reference clock generates a reference clock signal, and wherein a known number of cycles of a signal generated by a non-reference clock lasts for the representative calibration period. Determining a representative measurement indicative of a relative oscillation speed of a reference clock during a representative calibration period includes defining a plurality of calibration periods including a first calibration period and a second calibration period. The first calibration period is started at a first start time, wherein a first time offset value is equal to a difference between the first start time and a transition point (transition point) of the reference clock signal within the first calibration period. Similarly, the second calibration period is started at a second start time, wherein the second time offset value is equal to a difference between the second start time and a transition point of the reference clock signal within the second calibration period. The first time offset value is different from the second time offset value.

A plurality of measurements is generated by determining, for each of the plurality of calibration periods, a characteristic indicative of the relative oscillation speed of the reference clock during said one of the plurality of calibration periods. The plurality of measurements are used to determine an average measurement value. The average measurement value is used as a representative measurement indicative of the relative oscillation speed of the reference clock during a representative calibration period.

In some embodiments, the characteristic indicative of the relative oscillation speed of the reference clock during said one of the plurality of calibration periods is a numerical value representative of a number of cycles of the reference clock occurring during said one of the plurality of calibration periods. In other embodiments, the characteristic indicative of the relative oscillation speed of the reference clock during said one of the plurality of calibration periods is a numerical value representative of the frequency of the reference clock signal during said one of the plurality of calibration periods. In other embodiments, the characteristic indicative of the relative oscillation speed of the reference clock during said one of the plurality of calibration periods is a numerical value representative of a period of the reference clock signal during said one of the plurality of calibration periods.

In some embodiments, the plurality of calibration periods are concatenated with one another.

In some embodiments, each of the first and second start times is determined randomly or pseudo-randomly.

In some alternatives, the second start time occurs within the first calibration period. In some such embodiments, the first start time coincides with a transition point of a signal generated by the non-reference clock (coincident); the second start time coincides with a different transition point of a signal generated by the non-reference clock; and the one transition point and the different transition point of the signal generated by the non-reference clock do not coincide with each other.

In some embodiments, the processes/apparatus described herein are advantageously performed/employed within a mobile device. In some of these embodiments, each of the first and second start times is made to occur during a wake-up period of the mobile device.

In some embodiments, a representative measurement indicative of the relative oscillation speed of the reference clock during a representative calibration period is used to calibrate the non-reference clock.

Drawings

The objects and advantages of the present invention will be understood by reading the following detailed description in conjunction with the drawings, in which:

FIG. 1 depicts signals associated with a conventional calibration technique;

FIG. 2 is a graph showing how the timing of signals having different frequencies appear to have the same number of cycles during a given calibration period;

FIG. 3 is a graph depicting the input/output relationship of a conventional calibration method compared to an ideal input/output relationship;

FIG. 4 is a graph illustrating the improved accuracy that can be obtained when measuring the frequency of a real-time clock by increasing the calibration time;

FIG. 5 depicts an exemplary SC output signal and an initial portion of a calibration period;

FIG. 6 depicts a graph showing the relationship between the actual frequency value of the RTC and the measured frequency value for three different initial offset values;

FIG. 7 is a flowchart showing how repeated calibration operations are applied to SCs_OUTA timing diagram of signals;

FIG. 8 is a flowchart showing how repeated calibration operations are applied to SCs_OUTA timing diagram of signals in which the initial offset value is not held constant;

FIG. 9 is a flowchart showing how repeated calibration operations are applied to SCs during non-contiguous calibration periods_OUTA timing diagram of signals in which the initial offset value is not held constant;

FIG. 10 depicts an exemplary graph showing the relationship between actual frequency values and measured frequency values of the RTC resulting from the use of non-contiguous calibration periods, wherein for each calibration period, an initial offset value is determined randomly or pseudo-randomly;

FIG. 11 is a block diagram of an embodiment of a plurality of counters with which operations overlap one another;

FIG. 12 is a timing diagram showing how the start and stop times of the plurality of counters are determined;

fig. 13 is a flow diagram depicting steps performed in accordance with various embodiments.

Detailed Description

Various features of the present invention will now be described with reference to the drawings, wherein like parts are designated by the same reference numerals.

Various aspects of the invention will now be described in more detail in connection with several exemplary embodiments. To facilitate an understanding of the invention, many aspects of the invention are described in terms of sequences of actions to be performed by elements of a computer system or other hardware capable of executing programmed instructions. It will be recognized that in each of the embodiments, the various actions could be performed by specialized circuits (e.g., discrete logic gates interconnected to perform a specialized function), by program instructions being executed by one or more processors, or by a combination of both. Moreover, the invention can additionally be considered to be embodied entirely within any form of computer-readable carrier, such as solid-state memory, magnetic disk, optical disk or carrier wave (e.g., radio frequency, audio frequency or optical frequency carrier waves) containing a suitable set of computer instructions that would cause a processor to carry out the techniques described herein. Thus, the various aspects of the invention may be embodied in many different forms, and all such forms are contemplated to be within the scope of the invention. For each of the various aspects of the invention, any such form of embodiments may be referred to herein as "logic configured to" perform a described action, or alternatively as "logic that" performs a described action.

In one aspect, a calibration method and apparatus are presented that utilize several counters that count in parallel over a short period of time. The final calibration result is a combination of the results of the short counting period. The start time of the counter is not the same for each counting cycle.

By applying several short counters in parallel, the same accuracy can be achieved in a shorter time period, thus reducing the calibration time. This in turn allows calibration to be applied more frequently, making the non-reference clock more accurate.

In other embodiments, hardware complexity is reduced while maintaining the same level of accuracy by employing the same counter(s) in each of a series of time intervals and combining the results obtained therefrom.

These and other aspects are described in more detail below.

Fig. 1 depicts signals associated with conventional calibration techniques, involving a reference clock and a non-reference clock. More specifically, an exemplary output signal SC generated by an SC (not shown) (or more generally, a reference clock) is depicted_OUTAnd an exemplary output signal RTC generated by an RTC (not shown) (or more generally, a non-reference clock)_OUT. The RTC determines the start and stop times of the calibration period 101. Thus, the number of RTC cycles 103 (N) for the calibration period 101 lasts_RTC) Are known. Number of cycles 105 for SC (N) during calibration period 101_SC) Counting is performed. If the calibration period 101 lasts (span) N_RTCOne cycle and N is counted during the same period_SCOne cycle, then RTC frequency F_RTCAnd SC frequency F_SCThe relationship between is

Due to F_SCIs a high stable frequency, RTC frequency F_RTCCan be determined accurately. The timing circuit then considers F when determining the timing of the sleep mode procedure_RTCThe current value of (a). Can seeThe final precision of this technique is 1/N_SC. This is illustrated in fig. 2, fig. 2 showing SCs having different frequencies_OUTHow the timing of the signals appears to have the same number of cycles during a given calibration period 201. In example a), by pairing SCs_OUTThe leading edge number of the signal is counted to generate a count N_SCTo measure SC_OUTNominal frequency F of the signal_SC. In this example, N_SC6. However, if F_SCIs increased to (N)_SC+1)/N_SCMultiple, or reduced to (N)_SC-1)/N_SCMultiple times, as shown in examples b) and c), respectively, the same number N can be counted_SC＝6。

This is also apparent from fig. 3, which is a graph depicting the input/output relationship of a conventional calibration method compared to an ideal input/output relationship. In this example, N_SC＝100，N_RTC1 and F_SC100. F shown on the horizontal axis_RTCIncreases the actual value of (a) from 1 to 1.05. F_RTCIs shown on the vertical axis. The ideal relationship between actual and measured values is shown by line 301. However, F_RTCCan only obtain discrete values, thus introducing an intrinsic error (in this example, this intrinsic error is ± 0.005). If the calibration time is to be increased by a factor of 10 (in this example, N_RTC＝10，N_SC1000), the quantization error will be reduced and thus the accuracy will be improved by a factor of 10, as shown in fig. 4.

In the conventional technique, it is necessary to have at least N_SCPair of SCs in counter of size_OUTThe number of cycles of the signal is counted. To achieve + -1/N_SCThe counter has to count up to N_SC/F_SCThe duration of (c). If 0.1ppm accuracy is desired and the SC frequency is 10MHz, then the calibration duration using conventional techniques would have to be 1 second long. During this 1 second, the SC must run continuously. To keep the current consumption low, the calibration can only be performed every few minutes. An accuracy of 0.1ppm would require a counter capable of counting up to oneTen million, which is represented by 24 bits.

In the following, a calibration method and apparatus are described that can achieve improved accuracy without using the larger counters described above. In some embodiments, this may be accomplished by applying the same counter multiple times. Two of these embodiments will be described. In a first embodiment, a single short counter is used, which allows for reduced hardware complexity, but does not reduce calibration time. In a second embodiment, several short calibration periods are distributed in time.

First, it is important to understand how the initial timing of the calibration period with respect to the reference (SC) cycle affects the measurement results. Each calibration period has a start time (i.e., the time at which the measurement begins) and each reference (SC) output signal has at least one transition point (e.g., the occurrence of a leading edge, trailing edge, zero, or other level crossing), the detection of which is an indicator of the occurrence of a cycle of the SC output signal. The start time of the calibration period is related to a transition point of the non-reference signal. The first transition point of the reference output signal occurring after the start time is the first detected event (e.g., representing a cycle) to be counted during the calibration period. FIG. 5 depicts an exemplary SC output signal SC_OUTAnd an initial portion of the calibration period 501, which figure will help illustrate this example. Also shown is the start time T of the calibration period₁And SC output signal SC_OUTIs next occurring transition point T₁(in this example, the next occurring rising edge) by an initial offset value 503 or misalignment Δ T.

To show for N_SCHow the initial offset value 503 affects the measurement result, the actual and measured frequency values of the RTC (F respectively) for three different initial offset values 503 are depicted in fig. 6_{RTC_actual}And F_{RTC_measured}) The relationship between them. The ideal relationship is shown as line 601. For F_{RTC_actual}Is taken as the measured frequency value (F)_{RTC_measured}) And the difference between the ideal values. It can be seen that only when Δ T is 0.5/F_SCThe minimum error is equal to +/-0.5/N_SC. Conversely, for Δ T ═ 0.99/F_SCThe error can reach +1/N_SC(ii) a And 0.01/F for Δ T_SCThe error can reach-1/N_SC。

According to an aspect of the invention, by applying repeated calibration operations to the SC_OUTThe signals increase the accuracy of the calibration as shown in figure 7. The number of SC cycles in each calibration window is counted and the average (mean) of the results is generated. For the sake of example, assume that the calibration is repeated ten times (N)_CAL10). In the example shown in fig. 7, the initial phase Δ T is the same for each calibration window. As a result, the measured count value (N)_SC) The same for each calibration window and therefore the average value is equal to each individual count value. Therefore, the accuracy does not increase and the same input-output relationship result as shown in FIG. 3 is obtained, i.e., for N_SC＝100。

To avoid this, according to another aspect of the present invention, repeated calibration is performed as described above, but the initial offset value Δ T is not kept constant. One way to achieve this is by concatenating calibration cycles as shown in fig. 8. The initial offset value Δ T is different for different calibration periods due to time-sliding (slipping) effects. Again, the final result is obtained by averaging ten counts determined in ten consecutive calibration cycles. However, in this case, the input-output relationship (i.e., F)_{RTC_actual}And F_{RTC_measured}The relationship between) is the same as that shown in fig. 4. That is, the accuracy is actually improved by a factor of 10 (and with the count N)_SCThe same accuracy is obtained for a single long counter of 1000). The connection calibration period is neither reduced nor increased by the total calibration time (still 1000/F)_SC). However, a counter that is one tenth of that required by conventional techniques is used to obtain the results. Note that when F_SCIs F_RTCAt integer multiples of (d), the initial offset does not change; in this case, however, the measurement results in F_RTCAnd does not need to be averaged.

It may not always be possible to connect calibrations as shown in fig. 8And (4) period. For example, as previously described, US6,124,764 describes a calibration method that employs periodic page wakeup times. The above technique can now be applied, wherein during each wake-up period the number of SC cycles is counted. In order to benefit from repeated measurements, the initial offset value Δ T must be different for different measurement periods, and preferably different for each new measurement period. One way to achieve this is by randomizing the Δ T for each new wake-up time. This process is shown in the timing diagram of fig. 9. The initial timing of each calibration period is chosen randomly or pseudo-randomly, preferably with [0, 1/F ]_SC) Are evenly distributed in between.

FIG. 10 shows the input-output relationship (i.e., F on the horizontal axis) that results when averaging the counts obtained in ten different wake-up periods_{RTC_actual}And F on the vertical axis_{RTC_measured}) Examples of (2). Although not improved by a factor of 10, the accuracy is significantly improved compared to the conventional technique of performing a single measurement (please refer back to fig. 3 for comparison).

An alternative embodiment utilizing a parallel approach will now be described. An exemplary embodiment is depicted in the block diagram of fig. 11. The embodiment illustrated in fig. 11 may be included in any electronic device (not shown here for clarity) that requires the type of calibration discussed herein, including but not limited to cellular communication devices (e.g., mobile devices), wireless local area network devices, and wireless personal area network devices. This embodiment includes a plurality (i.e., an integer number n) of counters 1101_x(x is more than or equal to 1 and less than or equal to n). For example, an embodiment may include n-10 counters. Counter 1101_xCan be on a nominal number of SC duty cycles (N)_{SC_nom}) Counting, e.g. N_{SC_nom}100. For this purpose, the SC outputs a Signal (SC)_OUT) (or more generally, the output signal of the reference clock) is provided to a counter 1101_xThe clock input node of each. Counter 1101_xBy adjusting (e.g., incrementing) the count value it holds to output a Signal (SC) to the SC_OUT) Responds to the transition point (e.g., edge). It should be noted that, in an alternative embodiment,it may be the case that: counter 1101_xThe counter started earlier in the sequence may be in counter 1101_xThe other counters in (a) complete their measurements before they are completed. In this case, the embodiment may be designed such that the final counter value is stored in the memory, and the counter 1101_xIs restarted to obtain a measurement of a later occurring calibration cycle. Thus, counter 1101_xThe number of (i.e., the value of n) need not be equal to the number of calibration periods to be measured.

Each counter 1101_xIs controlled by a corresponding control signal of n control signals (counter enable signals) generated by timing control logic 1103 and provided to counter 1101_xThe enable input of the corresponding counter in (1). Each control signal (counter enable signal) is asserted (alert) for a duration equal to the duration of a representative calibration period, and counter 1101_xIs responsive to a transition point of the SC output signal only when its control signal (counter enable signal) is active. By a counter 1101_xRepresents the result of a corresponding one of the n calibration periods that overlap each other to some extent. In this example, there will be 10 overlapping calibration periods because there are 10 counters.

Counter 1101_xEach provides its output to averaging logic 1105. Averaging logic 1105 derives from the plurality of counters 1101_xThe count value is received and an average value (mean) is generated therefrom and provided at its output. Represents N_SCCan then be used to determine F from the previously described relationship_RTC。

Output of RTC (RTC) as previously described_OUT) (or more generally, a signal generated by a non-reference clock) determines when calibration is to be performed (e.g., calibration start and stop times based on the occurrence of transition points of the non-reference clock). Again, to benefit from averaging the results, the initial offset values of the different countersNot all of which are identical, and preferably all of which are different. This may be accomplished by including (e.g., by random or pseudo-random techniques) randomization of each counter 1101 within the timing control logic 1103_xIs implemented by the logic of the start time of (a). This randomization of the start times will result in an input-output relationship as shown in fig. 10.

An alternative embodiment does not use randomized counter start times, but has timing control logic 1103 that includes logic for determining counter start and stop times according to the timing diagram of FIG. 12. FIG. 12 depicts a signal SC_OUTAnd RTC_OUTExemplary relationships between. Logic continuous start counter 1101 for determining counter start and stop times_xEach of which is 1101, wherein each counter_xIs delayed by one RTC cycle, so the nth counter 1101_nWith 1 st counter 1101₁Is delayed by n-1 RTC cycles compared to the start-up of. (for clarity and to show counter 1101 in between)_xThis represents how many RTC cycles compared to the total number of RTC cycles in operation, and it should be noted that normally there are many RTC cycles in total for the total calibration window, e.g. about N for WCDMA implementations_RTC32768. ) Due to the sliding effect, the initial offset values Δ T will not all be the same (i.e., at least two or more of the initial offset values are different from each other). The input-output relationship resulting from this approach will be similar to that shown in fig. 4. Thus, in this example, the calibration accuracy is improved by a factor of 10, while the amount by which the calibration duration is increased is negligible. In other words, the desired accuracy can be obtained in a time of about 1/10.

Thus, regardless of which embodiment is implemented, the timing control logic 1103 causes, for example, a first counter enable signal to be asserted at a first start time, where the first time offset value is equal to a difference between the first start time and a first transition point of the reference clock signal; and asserting a second counter enable signal at a second start time, wherein a second time offset value is equal to a difference between the second start time and a second transition point of the reference clock signal. The timing control logic 1103 causes the first and second start times to be such that the first time offset value is different from the second time offset value.

Fig. 13 is a flow chart depicting steps that can be applied to all of the above-described embodiments, as well as other embodiments. The process begins by defining a calibration period (step 1301) that includes first and second calibration periods, as described above. (Note that the use of "first" and "second" does not refer to a temporal order in this case-rather, these markers are used merely to distinguish one of the calibration periods from any other of the calibration periods.) that is, each of the calibration periods has a start time that is related to a transition point of the non-reference clock. Each calibration period also has a time offset value equal to the start time of the calibration period and the reference clock Signal (SC) within the calibration period_OUT) Is detected by the difference between the transition points. In the above exemplary embodiment, the time offset value is different for all calibration periods. However, this may not be the case for alternative embodiments. To obtain the benefits of the present invention, the time offset values for at least two of the calibration periods (e.g., the first and second offset values corresponding to the first and second calibration periods, respectively) should be different from each other.

Next, a plurality of measurements are generated by, for each of the plurality of calibration periods, measuring a number of cycles of the reference clock that occur during the one of the plurality of calibration periods (step 1303). In the embodiment shown in fig. 8 and 9, these measurements are taken one at a time in sequence. Alternatively, in embodiments employing multiple counters (see, e.g., fig. 11), two or more of the measurements may overlap each other.

The plurality of measurements thus obtained are then used to determine an average number of cycles of the reference clock signal per calibration period (step 1305).

This average number of cycles of the reference clock per calibration period is then used as the measured number of cycles of the reference clock signal that occur during the calibration period. Such use may include, for example, determining notReference clock (RTC)_OUT) As previously described. In some embodiments, such use may optionally be to compare the measured value to a nominal value (e.g., to determine a non-reference clock, RTC_OUTWhether it is running too fast or too slow and by how much).

The above calibration techniques are advantageous because they can be used, for example, to improve accuracy using serial methods without increasing hardware complexity or to shorten calibration time using parallel methods. The latter is important as it will improve low power modes in cellular terminals; during each wake-up period for checking the paging channel, a non-reference clock (e.g., RTC) may be calibrated.

The invention has been described with reference to specific embodiments. However, it will be apparent to those skilled in the art that the present invention may be embodied in other specific forms than the embodiments described above.

For example, the above embodiments include determining a value representing a number of cycles of the reference clock that occur during the calibration period. However, this is only one possible characteristic of an oscillation speed (hereinafter, referred to as "relative oscillation speed") indicating an oscillation speed of the reference clock with respect to the non-reference clock. In other embodiments, other characteristics may be measured during the calibration period and the measured characteristics averaged. For example, the measured characteristic may be the frequency of the reference clock (e.g., expressed in Hz). In other embodiments, the measured characteristic may be a period (e.g., expressed in seconds).

Thus, the above-described embodiments are merely illustrative and should not be considered restrictive in any way. The scope of the invention is given by the appended claims, rather than the preceding description, and all variations and equivalents which fall within the range of the claims are intended to be embraced therein.

Claims (27)

1. A method of ascertaining a representative measurement indicative of a relative oscillation speed of a reference clock during a representative calibration period, wherein the reference clock generates a reference clock signal, and wherein a known number of cycles of a signal generated by a non-reference clock last for the representative calibration period, the method comprising:

defining a plurality of calibration periods, the plurality of calibration periods including a first calibration period and a second calibration period;

starting the first calibration period at a first start time, wherein a first time offset value is equal to a difference between the first start time and a transition point of a reference clock signal within the first calibration period;

starting the second calibration period at a second start time, wherein a second time offset value is equal to a difference between the second start time and a transition point of the reference clock signal within the second calibration period, and wherein the first time offset value is different from the second time offset value;

generating a plurality of measurements by determining, for each of the plurality of calibration periods, a characteristic indicative of a relative oscillation speed of the reference clock during said each of the plurality of calibration periods;

determining an average measurement value using the plurality of measurements; and

the average measurement value is used as a representative measurement indicative of the relative oscillation speed of the reference clock during the representative calibration period.

2. The method of claim 1, wherein the characteristic indicative of the relative oscillation speed of the reference clock during said each of the plurality of calibration periods is a numerical value representative of a number of cycles of the reference clock occurring during said each of the plurality of calibration periods.

3. The method of claim 1, wherein the characteristic indicative of the relative oscillation speed of the reference clock during said each of the plurality of calibration periods is a numerical value representative of the frequency of the reference clock signal during said each of the plurality of calibration periods.

4. The method of claim 1, wherein the characteristic indicative of the relative oscillation speed of the reference clock during said each of the plurality of calibration periods is a numerical value representative of a period of the reference clock signal during said each of the plurality of calibration periods.

5. The method of claim 1, wherein the plurality of calibration periods are linked to each other.

6. The method of claim 1, wherein each of the first and second start times is determined randomly or pseudo-randomly.

7. The method of claim 1, wherein the second start time occurs within a first calibration period.

8. The method of claim 7, wherein:

the first start time coincides with a transition point of the signal generated by the non-reference clock;

the second start time coinciding with a different transition point of a signal generated by the non-reference clock; and

the one transition point and the different transition point of the signal generated by the non-reference clock do not coincide with each other.

9. The method of claim 1, wherein the method is performed in a mobile device, and each of the first and second start times occurs during a wake-up period of the mobile device.

10. The method of claim 1, comprising:

the non-reference clock is calibrated using a representative measurement indicative of the relative oscillation speed of the reference clock during the representative calibration period.

11. An apparatus for determining a representative measurement indicative of a relative oscillation speed of a reference clock during a representative calibration period, wherein the reference clock generates a reference clock signal, and wherein a known number of cycles of a signal generated by a non-reference clock last for the representative calibration period, the apparatus comprising:

logic configured to define a plurality of calibration periods, the plurality of calibration periods including a first calibration period and a second calibration period;

logic configured to:

starting the first calibration period at a first start time, wherein a first time offset value is equal to a difference between the first start time and a transition point of a reference clock signal within the first calibration period; and

starting the second calibration period at a second start time, wherein a second time offset value is equal to a difference between the second start time and a transition point of the reference clock signal within the second calibration period, and wherein the first time offset value is different from the second time offset value;

logic configured to generate a plurality of measurements, wherein the plurality of measurements are generated by determining, for each calibration period of the plurality of calibration periods, a characteristic indicative of a relative oscillation speed of a reference clock during said each calibration period of the plurality of calibration periods;

logic configured to determine an average measurement value using the plurality of measurements; and

logic configured to use the average measurement value as a representative measurement indicative of a relative oscillation speed of a reference clock during the representative calibration period.

12. The apparatus of claim 11, wherein the characteristic indicative of the relative oscillation speed of the reference clock during said each of the plurality of calibration periods is a numerical value representative of a number of cycles of the reference clock occurring during said each of the plurality of calibration periods.

13. The apparatus of claim 11, wherein the characteristic indicative of the relative oscillation speed of the reference clock during said each of the plurality of calibration periods is a numerical value representative of the frequency of the reference clock signal during said each of the plurality of calibration periods.

14. The apparatus of claim 11, wherein the characteristic indicative of the relative oscillation speed of the reference clock during said each of the plurality of calibration periods is a numerical value representative of a period of the reference clock signal during said each of the plurality of calibration periods.

15. The apparatus of claim 11, wherein the plurality of calibration periods are connected to each other.

16. The apparatus of claim 15, wherein the logic configured to generate the plurality of measurements comprises only one counter used during each of the calibration periods.

17. The apparatus of claim 11, wherein each of the first and second start times is determined randomly or pseudo-randomly.

18. The apparatus of claim 11, wherein the second start time occurs within a first calibration period.

19. The apparatus of claim 18, wherein:

logic configured to generate the plurality of measurements includes as many counters as there are calibration periods; and

each of the counters operates only during a corresponding calibration period of the plurality of calibration periods.

20. The apparatus of claim 18, wherein:

the first start time coincides with a transition point of the signal generated by the non-reference clock;

the second start time coinciding with a different transition point of a signal generated by the non-reference clock; and

the one transition point and the different transition point of the signal generated by the non-reference clock do not coincide with each other.

21. The apparatus of claim 11, wherein the apparatus is an element in a mobile device, and each of the first and second start times occurs during a wake-up period of the mobile device.

22. The apparatus of claim 11, comprising:

logic that calibrates the non-reference clock using a representative measurement that indicates a relative oscillation speed of the reference clock during the representative calibration period.

23. An apparatus for determining a measured number of cycles of a reference clock signal that occur during a representative calibration period, wherein a known number of cycles of a non-reference clock signal generated by a non-reference clock last for the representative calibration period, the apparatus comprising:

timing control logic that receives the non-reference clock signal and generates therefrom a plurality of counter enable signals, including a first counter enable signal and a second counter enable signal, wherein each counter enable signal is asserted for a duration equal to a duration of the representative calibration period;

a plurality of counters, each counter having an enable input connected to receive a respective counter enable signal of the plurality of counter enable signals and each counter having a clock input node connected to receive the reference clock signal, wherein each of the counters maintains a count value that is adjusted in response to an occurrence of a transition point of the reference clock signal only when the respective counter enable signal of the plurality of counter enable signals is active; and

logic that receives the count values from the plurality of counters and generates an average therefrom,

wherein:

the timing control logic asserts the first counter enable signal at a first start time, wherein a first time offset value is equal to a difference between the first start time and a first transition point of the reference clock signal;

the timing control logic asserts the second counter enable signal at a second start time, wherein a second time offset value is equal to a difference between the second start time and a second transition point of the reference clock signal; and

the first time offset value is different from the second time offset value.

24. The apparatus of claim 23, wherein:

the timing control logic invalidates the first counter enable signal for a first stop time;

the timing control logic disables the second counter enable signal for a second stop time; and

the first stop time coincides with the second start time.

25. The apparatus of claim 23, wherein each of the first and second start times is determined randomly or pseudo-randomly.

26. The apparatus of claim 23, wherein the second start time occurs after the first start time and before a first stop time.

27. The apparatus of claim 26, wherein:

the first start time coincides with a transition point of the signal generated by the non-reference clock;

the second start time coinciding with a different transition point of a signal generated by the non-reference clock; and

the one transition point and the different transition point of the signal generated by the non-reference clock do not coincide with each other.