HK1129947B - Multi-channel esd device and method therefor - Google Patents

Description

Multi-channel ESD device and method thereof

Technical Field

The present invention relates generally to electronics, and more particularly to methods of forming semiconductor devices and structures.

In the past, the semiconductor industry utilized various methods and structures to form electrostatic discharge (ESD) protection devices. According to an international specification, namely the International Electrotechnical Commission (IEC) specification commonly referred to as IEC61000-4-2 (class 2), it is desirable for an ESD device to respond to high input voltages and currents in about 1 nanosecond (IEC is addressed at 3, rue de varebe, 1211Gen ve20, Switzerland).

Some previous ESD devices have used zener diodes and P-N junction diodes in an attempt to provide ESD protection. Typically, these prior ESD devices must compromise the choice of low capacitance to prevent sharp breakdown voltage characteristics. A sharp breakdown voltage characteristic is required to provide a low clamping voltage for the ESD device. In most cases, these device structures have high capacitances, typically greater than about 1 to 6(1-6) picofarads. The high capacitance limits the response time of the ESD device. Some previous ESD devices operate in a punch-through (punch-through) mode, which requires the device to have a very thin and accurately controlled epitaxial layer, typically less than about 2 microns thick, and requires low doping within the epitaxial layer. These structures often make it difficult to accurately control the clamping voltage of the ESD device, and particularly difficult to control low clamping voltages, such as voltages less than about 10 volts (10V). An example of such an ESD device is disclosed in U.S. patent No. 5,880,511 issued to Bin Yu et al on 9/3 1999. Another ESD device utilizes the body region of a vertical MOS transistor to form a zener diode at the interface with the underlying epitaxial layer. The doping profile and depth used for ESD devices results in high capacitance and slow response time. Furthermore, it is difficult to control the light doping level within the thin layer, which makes it difficult to control the breakdown voltage of the ESD device. An example of such an ESD device is disclosed in us patent publication No. 2007/0073807 to inventor Madhur Bobbe, published on 29.3.2007.

Accordingly, it is desirable to have an electrostatic discharge (ESD) device that has a low capacitance, has a fast response time, is responsive to both positive and negative ESD events, has a well controlled clamping voltage, is easy to control in manufacturing, and has a clamping voltage that can be controlled over a voltage range from a low voltage to a high voltage.

Drawings

FIG. 1 schematically illustrates an embodiment of a portion of a circuit representation of an electrostatic discharge (ESD) protection device according to the present invention;

fig. 2 illustrates a cross-section of a portion of an embodiment of the ESD device of fig. 1 in accordance with the present invention;

fig. 3 is a graph illustrating some of the carrier concentrations of the ESD devices of fig. 1 and 2 in accordance with the present invention;

FIG. 4 schematically illustrates an embodiment of a portion of a circuit representation of another electrostatic discharge (ESD) protection device according to the present invention;

fig. 5 illustrates a cross-sectional portion of an embodiment of the ESD device of fig. 4 in accordance with the present invention;

fig. 6 illustrates a cross-sectional portion of another embodiment of the ESD device of fig. 4 in accordance with the present invention;

fig. 7 illustrates a plan view of the ESD device of fig. 6 in accordance with the present invention;

FIG. 8 schematically illustrates an embodiment of a portion of a circuit representation of yet another electrostatic discharge (ESD) protection device according to the present invention; and

fig. 9 illustrates a cross-sectional portion of an embodiment of the ESD device of fig. 8 in accordance with the present invention.

For simplicity and clarity of illustration, elements in the figures are not necessarily drawn to scale, and the same reference numbers in different figures denote the same elements. Moreover, descriptions and details of well-known steps and elements are omitted for simplicity of the description. As used herein current carrying electrode means an element of a device that carries current through the source or drain of the device, such as a MOS transistor, or the emitter or collector of a bipolar transistor, or the cathode or anode of a diode, and a control electrode means an element of the device that controls current through the gate of the device, such as a MOS transistor, or the base of a bipolar transistor. Although these devices are explained herein as certain N-channel or P-channel devices, or certain N-type devices with P-type doped regions, one skilled in the art will recognize that complementary devices are also possible in accordance with the present invention. One skilled in the art will recognize that the use of "during.. once.. or at.. time," as used herein, is not an exact term for a behavior to coincide with an initial behavior, but rather there may be some small but reasonable delay, such as a propagation delay, between reactions that are provoked by the initial reaction. Use of the word "approximately" or "substantially" indicates that the value of an element has a parameter that is expected to be very close to the specified value or position. However, as is well known in the art, there is always a very small difference in the blocking value or position exactly as specified. It is well established in the art that differences of up to about 10% (and, for semiconductor doping concentrations, up to 20%) are considered reasonable differences from the ideal target exactly as described. For clarity of the drawings, the doped regions of the device structure are shown as having generally straight edges and precisely angled corners. However, those skilled in the art understand that due to the diffusion and activation of dopants, the edges of doped regions may not typically be straight lines and the corners may not be tight angles.

Detailed Description

Fig. 1 schematically illustrates a portion of an embodiment of an electrostatic discharge (ESD) protection device or ESD device 10 having a low capacitance and a fast response time. Device 10 includes two terminals, namely a first terminal 11 and a second terminal 12, and is configured to provide bidirectional ESD protection between terminals 11 and 12. Either one of the terminals 11 and 12 may be an input terminal or an output terminal. The output terminal is typically connected to another element (not shown) to be protected by device 10. For example, terminal 12 may serve as an output terminal and be connected to the high voltage side of a regulated power supply (e.g., a 5V supply). Device 10 is configured to have a low capacitance between terminals 11 and 12. Device 10 is also formed to limit the maximum voltage developed between terminals 11 and 12 to the clamping voltage of device 10. In addition, device 10 is formed to have sharp corner voltage or sharp breakdown voltage characteristics that help to precisely control the value of the clamping voltage. The low capacitance helps provide the device 10 with a fast response time. The device 10 includes a plurality of steering diode channels including a first steering diode channel 16 and a second steering diode channel 22. Channel 16 includes a first steering diode 14, steering diode 14 having an anode commonly connected to terminal 11 and to the cathode of a second steering diode 15. Channel 22 includes a third steering diode 20, steering diode 20 having an anode commonly connected to terminal 12 and to the cathode of a fourth steering diode 21. Diodes 14, 15, 20, and 21 are formed as P-N junction diodes with low capacitance. A zener diode 18 is connected in parallel with each of the channels 16 and 22. Diode 18 has an anode connected to the anodes of diodes 15 and 21 and a cathode connected to the cathodes of diodes 14 and 20.

In normal operation, device 10 is biased to a normal operating voltage, for example, a voltage between greater than 1 volt (1V) and the zener voltage of diode 18, for example, by applying a voltage of approximately 1 volt (1V) to terminal 11 and a ground reference voltage to terminal 12. Due to the characteristics of device 10 described below, the capacitance of device 10 remains low when the voltage between terminals 11 and 12 varies within this normal operating voltage range. However, the capacitance of an ESD device is usually specified in a state where zero volts is applied across the device. This zero voltage condition is commonly referred to as a zero bias condition. As will be seen further hereinafter, the low capacitance characteristic of device 10 described hereinafter forms very low capacitance values for diodes 14, 15, 20 and 21 under this zero bias condition. Because there are two parallel paths between terminals 11 and 12, the capacitance value of each path is the additive product (adductor) of the capacitances in each path. The first path comprises the capacitance of the diodes 14, 18 and 21 in series. Because the capacitance of the capacitors in series is less than the capacitance of the smallest capacitor, the capacitance of the first path is less than the capacitance of any of the diodes 14, 18 or 21. As will be seen further hereinafter, device 10 is formed such that the zero bias capacitance of diodes 14 and 21 is small. Similarly, the capacitance of the second path including diodes 20, 18 and 15 is also very small. The sum of the two paths creates a very small zero bias capacitance for device 10.

If a positive electrostatic discharge (ESD) event is received on terminal 11, then terminal 11 is forced to a large positive voltage relative to terminal 12. This large positive voltage forward biases diodes 14, 21 and, in addition to diodes 15 and 20, also reverse biases diode 18. When the voltage between terminals 11 and 12 reaches the positive threshold voltage of device 10 (the forward voltage of diodes 14 and 21 plus the zener voltage of diode 18), a positive current (Ip) flows from terminal 11 through diode 14 to diode 18 and through diodes 18 and 21 to terminal 12. The zener voltage of diode 18 fixes the maximum voltage developed between terminals 11 and 12 to about the zener voltage of diode 18 (plus the forward voltages of diodes 14 and 21). If a negative ESD event is received on terminal 11, then terminal 11 is forced to a large negative voltage relative to terminal 12. This large negative voltage forward biases diodes 20 and 15 and reverse biases diode 18 in addition to diodes 14 and 21. When the voltage between terminals 11 and 12 reaches the negative threshold voltage of device 10 (the forward voltage of diodes 20 and 15 plus the zener voltage of diode 18), a negative current (In) flows from terminal 12 through diode 20 to diode 18 and through diodes 18 and 15 to terminal 11. The sharp knee of diode 18 causes diode 18 to quickly fix the maximum voltage between terminals 11 and 12 to the zener voltage of diode 18 (plus the forward voltages of diodes 15 and 20).

Fig. 2 shows a cross-sectional view of a portion of an embodiment of ESD device 10. Diodes 14, 15, 20, 21, and 18 are formed on semiconductor substrate 25. The diodes 14, 15, 20, 21 and 18 are identified in a general manner by arrows. Semiconductor layer 33 is formed on substrate 25, for example, by epitaxial growth, and a portion of layer 33 may function as a drift region for diodes 14, 15, 20, and 21.

Fig. 3 is a graph illustrating a carrier concentration profile of a preferred embodiment of device 10. The abscissa represents the depth from the surface of layer 33 to device 10, while the ordinate represents increasing values of carrier concentration. Plot 68 illustrates the carrier concentration of device 10 resulting from a positive bias voltage applied from terminal 11 to terminal 12 (e.g., via a positive ESD event). The description refers to fig. 1 to 3.

To form diode 18, semiconductor region 29 is formed near the interface of the dopants forming layer 33 and the dopants of substrate 25. In a preferred embodiment, substrate 25 is formed with a P-type conductivity having a dopant concentration of not less than about 1 × 10¹⁹Atom/cm³And preferably at about 1 × 10¹⁹And 1X 10²¹Atom/cm³In the meantime. In the preferred embodiment, the semiconductor layerThe body region 29 is formed as an N-type region having a peak doping concentration of not less than about 1 x 10¹⁹Atom/cm³And preferably at about 1 × 10¹⁹And 1X 10²¹Atom/cm³In the meantime. Further, the thickness of region 29 is typically less than 1 micron, and preferably between about 1 and 3(1-3) microns. Due to the small thickness of region 19 in addition to the high doping concentration of region 29 and substrate 25, when device 10 receives a positive voltage from terminal 11 to terminal 12, the voltage causes the carrier concentration to be confined to a small high density region within region 29 and near the interface with substrate 25. This high concentration of carriers and dopants provides a very sharp transition or knee for the zener diode 18 and allows very accurate control of the breakdown voltage or zener voltage of the diode 18. By varying the carrier concentration or carrier distribution of region 29 and/or substrate 25, the breakdown voltage or zener voltage of diode 18 can be adjusted. This allows the breakdown voltage to be precisely controlled for a particular application, such as a 5 or 12 or 24 volt (5V, 12V, 24V) breakdown voltage application.

Layer 33 is preferably formed with a relatively low peak doping concentration that is at least an order of magnitude less than the doping concentration of region 29, and typically at about 1 x 10¹³And 1X 10¹⁷Atom/cm³In the meantime. Layer 33 and region 29 may be formed on substrate 25 by various methods known to those skilled in the art. For example, a thin N-type epitaxial layer, shown by dashed line 26, may be formed on substrate 25 as a first portion of layer 33. This first portion may be doped to form region 29. Thereafter, the remainder of layer 33 may be formed.

Subsequently, isolation trenches 35, 37, and 39 may be formed to isolate portions of layer 33 that form diodes 14 and 20 from portions of layer 33 that form diodes 15 and 21. Trenches 35, 37, and 39 are typically formed by creating openings through layer 33 from the top surface of layer 33 and extending into substrate 25. To prevent conduction laterally through region 29 between diode 18 and either of diodes 15 or 21, trench 35 also extends a distance into substrate 25 through region 29. Isolation is provided to trenches 35, 37 and 39, for example, by forming insulating material liners 30 along the sidewalls and bottom of trenches 35, 37 and 39 and filling the remaining openings with an insulating material or doped or undoped polysilicon. Alternatively, a liner 30 of insulating material may be formed along the sidewalls of trenches 35, 37, and 39 rather than the bottom, and the remaining portion of the opening may be filled with insulating material or with a material having the conductivity and doping of base 25. The method of forming the trenches 35, 37 and 39 is well known to those skilled in the art. Because the groove 35 extends through the region 29, it reduces alignment tolerances and facilitates reliable production of the device 10. The groove 35 is preferably formed as a closed polygon with a boundary having an opening that surrounds a portion of the layer 33, so that the groove 35 can be considered a multiply-connected domain. Similarly, each of slots 37 and 39 may be considered a multiply-connected domain. Each of the slots 35 and 37 may be considered an occluding structure that minimizes electrical coupling between the enclosed portion and other portions of the device 10.

Diode 14 includes a doped region 42 formed on the surface of layer 33 having the same conductivity as substrate 25. Similarly, diode 20 includes a doped region 48 formed on the surface of layer 33 having the same conductivity as substrate 25. Regions 42 and 48 are formed to extend into layer 33 and cover region 29. Regions 42 and 48 are generally arranged such that the boundaries of regions 42 and 48, e.g., the boundaries formed on the surface of layer 33, are completely surrounded by grooves 35. Preferably, groove 35 is a continuous groove formed around regions 42 and 48. Because trench 35 extends through layer 33, it reduces the amount of layer 33 proximate to regions 42 and 48, thereby helping to reduce the capacitance of diodes 14 and 20. The peak doping concentration of regions 42 and 48 is generally greater than the peak doping concentration of layer 33 and preferably approximately equal to the peak doping concentration of substrate 25. Regions 42 and 48 are typically formed to extend from the surface into layer 33 by a distance greater than about 2 microns and preferably about 0.1 to 2(0.1-2) microns. The large differential doping concentration between region 42 and layer 33 and between region 48 and layer 33, as well as the shallow depth of regions 42 and 48, help to provide very small zero bias capacitance for the respective diodes 14 and 20. This very small zero-bias capacitance of diodes 14 and 20 helps create a small zero-bias capacitance for device 10 as shown above. The capacitance of each of diodes 14, 18, and 20 is typically less than about 0.4 picofarads at zero bias, and the equivalent series capacitance of diodes 14, 18, and 20 forms a capacitance of about 0.2 picofarads and preferably no greater than about 0.01 picofarads for device 10.

To form diode 21, doped region 49 is formed in layer 33 having a conductivity opposite that of substrate 25. Similarly, to form diode 15, doped region 41 is formed in layer 33 having a conductivity opposite that of substrate 25. Regions 41 and 49 are formed on the surface of layer 33 and preferably extend approximately the same distance into layer 33 as regions 42 and 48. However, regions 41 and 49 do not cover region 29. Region 41 is disposed such that the boundary of region 41, e.g., at the surface of layer 33, is completely surrounded by grooves 37, and region 49 is disposed such that the boundary of region 49, e.g., at the surface of layer 33, is completely surrounded by grooves 39. Each of the grooves 37 and 39 is formed as one continuous groove. Because trenches 37 and 38 extend through layer 33, they reduce the amount of layer 33 proximate to respective regions 41 and 49, thereby helping to reduce the capacitance of respective diodes 15 and 21. In a preferred embodiment, the peak doping concentration of regions 41 and 49 is greater than the peak doping concentration of layer 33 and preferably approximately equal to the peak doping concentration of substrate 25.

Regions 42 and 48 are typically spaced a distance from region 29, which helps to minimize the capacitance of diodes 15 and 21. The spacing is typically about 2 to 20(2-20) microns. The portions of layer 33 between regions 42 and 29 and between regions 48 and 29 form the drift regions of respective diodes 14 and 20. To reduce the formation of parasitic transistors and to ensure that device 10 does not operate in the punch-through operating region, the drift region thickness of layer 33 is typically at least about 2 microns.

Optional doped region 44 may be formed in layer 33 having a conductivity opposite that of substrate 25. Region 44 is generally formed to cover region 29 and is disposed between regions 42 and 48, and thus, region 44 is within the multiply-connected region formed by groove 35. Preferably, region 44 extends approximately the same distance into layer 33 as regions 42 and 48. Region 44 acts as a channel stop that helps prevent an inversion channel from forming near the surface of layer 33 between diodes 14 and 20. In addition, the high differential doping concentration between region 44 and layer 33 helps prevent parasitic bipolar transistors from forming between region 42, layer 33, and region 48. In some embodiments where the differential doping concentration does not form such a parasitic bipolar transistor, region 44 may be omitted. As can be seen, device 10 is generally free of doped regions, which have the same conductivity as substrate 25, and is disposed between diode 14 and region 29, and thus between regions 42 and 29.

When device 10 receives a positive ESD voltage on terminal 11 relative to terminal 12, diodes 14 and 21 are forward biased, while diodes 15 and 20 are reverse biased. Due to these depletion regions, the carrier density in layer 33 is further reduced from the zero bias condition (fig. 68), which helps to further reduce the capacitance of device 10. The capacitance of device 10 at zero bias is typically less than about 0.4 picofarads and the equivalent series capacitance of device 10 is about 0.2 picofarads and preferably no greater than about 0.1 picofarads.

When device 10 receives a negative voltage on terminal 11 relative to terminal 12, diodes 20 and 15 are forward biased, while diodes 14 and 21 are reverse biased. Due to these depletion regions, the carrier density in layer 33 is further reduced from the zero bias condition, which helps to further reduce the capacitance of device 10. Note that for both ESD discharge events, ESD current flows in and out at the top surface of substrate 25 and layer 33. The ESD current does not flow through the bottom surface of the substrate 25, and therefore, the bottom surface of the substrate 25 generally has a floating potential.

Accordingly, insulating material 51 may be formed on the surface of layer 33. Openings are typically formed through insulative material 51 to expose portions of regions 41, 42, 48, and 49. A conductor 52 may be used to electrically contact the two regions 41 and 42. A conductor 53 may be used to electrically contact the two regions 48 and 49. Conductors 52 and 53 are then typically connected to respective terminals 11 and 12. Because the ESD current of device 10 does not flow through the bottom surface of substrate 25, conductors are not typically applied to the bottom surface.

When electrode-electrostatic discharge occurs, there are typically large voltage and current spikes that occur over a brief period of time. Typically, peak currents and peak voltage occur over a period of a few nanoseconds, typically less than 2 nanoseconds (2nsec.), and only for about 1 nanosecond (1 nsec.). In another time interval, typically about 20 nanoseconds, the current is typically reduced to a steady level and slowly reduced in another 20 to 40(20-40) nanoseconds. The peak of the current may be in the range of 1 to 30amps (1 to 30amps) and the peak voltage may be in the range of 2000 to 30000 volts (2000-. The size and response time of the elements of device 10 are preferably configured to respond to voltage and conduct peak current during the time interval of the peak voltage. During an ESD event between terminals 11 and 12, diodes 14 and 21 are connected in series or diodes 15 and 20 are connected in series, the effective capacitance being the total series capacitance. Because the capacitors in series result in a capacitance that is less than the minimum capacitance, the low capacitance ensures that the capacitance of device 10 is low enough for device 10 to respond to an ESD event and conduct ESD current during peak ESD voltages and currents.

In another embodiment, device 10 also includes a third terminal 17 (shown in phantom in fig. 1). In most applications of the embodiment using device 10, terminal 17 is connected to a ground reference potential of the system in which device 10 is used. This three terminal configuration provides protection between terminals 11 and 12 for large voltages received on either of terminals 11 or 12. Referring again to fig. 2, terminal 17 is formed by forming a conductor 50 (shown in phantom) such as a metal to the bottom surface of substrate 25 and providing a connection from conductor 50 to terminal 17.

Fig. 4 schematically illustrates an embodiment of a portion of a circuit representation of ESD device 55, which is an alternative embodiment of device 10 described in the description of fig. 1-3. The circuit schematic of device 55 is similar to that of device 10 except that device 55 has a fourth terminal 58 connected to the cathode of diode 18. Furthermore, it will be understood by those skilled in the art that device 55, and also device 10, may include additional channels, such as another channel 46 parallel to channel 16 and another channel 47 parallel to channel 22. Channel 46 includes series connected P-N diodes 75 and 76, diodes 75 and 76 having a terminal 77 connected to a common node of diodes 75 and 76. Further, channel 47 includes series-connected P-N diodes 79 and 80, diodes 79 and 80 having a terminal 81 connected to a common node of diodes 79 and 80. In applications using device 55, terminal 58 is typically connected to the voltage rail of a power supply, and terminal 17 is connected to a common reference potential. Terminals 11 and 12 provide ESD protection for signals passing through terminals 11 and 12.

Fig. 5 shows a cross-sectional portion of device 55. The cross-section of device 55 is similar to the cross-section of device 10, except that device 55 includes conductor 54 connected to terminal 58 and further includes conductors 62 and 64. For the embodiment shown in fig. 5, region 44 is not optional and is used to provide a low resistance electrical connection to conductor 54 with layer 33. This low resistance electrical connection facilitates connection of terminal 58 to the cathode of diode 18.

It is preferable that the diodes 14 and 20 be formed with substantially equal capacitance values. In some cases, a slight inversion layer (inversion layer) may be formed near the surface of layer 33 between regions 44 and 48 and between regions 44 and 42. Such an inversion layer may affect the capacitance of diodes 14 and 20. Conductors 62 and 64 help to minimize perturbations in the capacitance values of diodes 14 and 20, thereby matching the values more equally. Each of conductors 62 and 64 may be considered an occlusive structure that minimizes electrical coupling between the enclosed portion and other portions of device 10. Conductor 62 is formed to extend from the surface of layer 33 through layer 33 and through region 29. The boundaries of the conductor 62 generally form a closed polygon that surrounds a portion of the layer 33. Region 48 is located within the portion of layer 33 surrounded by conductor 62. To prevent the capacitance of region 48, and thus diode 20, from increasing, conductor 62 is typically disposed about 2 to 20(2-20) microns from region 48. Conductor 64 is also formed to extend from the surface of layer 33 through layer 33 and through region 29. The boundaries of the conductor 64 generally form a closed polygon that surrounds another portion of the layer 33. Region 42 is located within the portion of layer 33 surrounded by conductor 64. To prevent the capacitance of region 42, and thus diode 14, from increasing, conductor 64 is typically disposed about 2 to 20(2-20) microns from region 42. Each of conductors 62 and 64 may be considered to be an independent multi-connected domain. Conductors 62 and 64 are typically formed by creating an opening that extends from the surface through layer 33 to expose a portion of region 29. Thereafter, to form conductors 62 and 64, the openings are filled with a conductor such as doped polysilicon. In another embodiment, the openings in which conductors 62 and 64 are formed may have patches of insulating material on the sidewalls rather than on the bottom. Omitting the backing plate on the bottom facilitates making an electrical connection with the area 29. In yet another embodiment, conductors 62 and 64 may be replaced by isolation trenches such as trench 35. However, to allow conduction through region 29, such isolation trenches would extend to the surface of region 29 but not through region 29. Those skilled in the art will recognize that conductors 62 and 64 may be added to device 10 of fig. 1 and 2.

Although P-N diodes 75, 76, 79, and 80 are not shown in fig. 5, one skilled in the art will recognize that diodes 75 and 79 should be formed as doped regions overlying region 29, similar to respective diodes 14 and 20 and respective regions 42 and 48. The doped regions of diodes 75 and 79 are generally surrounded by trench 35. To form diodes 75 and 79, region 2 should be made larger, e.g., extending in a direction perpendicular to the page shown in fig. 5. Alternatively, another region similar to region 29 may be formed on substrate 25 and electrically connected to region 29. Thus, region 29 or an additional region similar to region 29 would electrically connect the cathodes of diodes 75 and 79 to the cathode of diode 18. Diodes 76 and 80 are formed within layer 33 and do not cover region 29. Each doped region for diodes 76 and 80 should be within a closed polygon formed by a slot similar to either of slots 37 or 39. Thus, the anodes of diodes 76 and 80 are connected to the anode of diode 18 through substrate 25.

Fig. 6 shows a cross-sectional portion of an ESD device 60, which is an alternative embodiment of device 55 explained in the description of fig. 5. The circuit schematic of device 60 is substantially the same as the circuit schematic of device 55. However, device 60 includes a plurality of conductors 56 extending from region 44 through layer 33 and intersecting region 29. Conductor 56 reduces the resistance of the connection between conductor 54 and the cathode of diode 18. Those skilled in the art will recognize that conductor 56 can provide reduced resistance without extending completely through layer 33 to region 29. Typically, conductor 56 should extend at least half the distance from the surface of layer 33 to region 29, and may extend further up to the distance of contact region 29. Conductor 56 is typically formed in a manner similar to conductors 62 and 64.

Those skilled in the art will recognize that conductors 62 and 64 may be omitted from device 60.

Fig. 7 shows a plan view of the device 60 explained in the description of fig. 6. Fig. 7 shows device 60 prior to formation of conductors 52, 53 and 54, so that the layout of device 60 can be seen. In addition to the multiply connected nature of conductors 62 and 64, FIG. 7 also illustrates the multiply connected nature of slots 35, 37 and 39. Conductor 56 is shown in a general manner in fig. 7 with dashed lines.

Fig. 8 schematically illustrates an embodiment of a portion of a circuit schematic of an ESD device 70, the ESD device 70 being an alternative embodiment of the device 55 explained in the description of fig. 5-7. Device 70 includes two ESD devices, each optionally having multiple channels. The first ESD device 82 comprises a zener diode 71 connected in parallel with the P-N diodes 14, 15 and optionally with the diodes 75 and 76. Device 82 has input/output terminals 11 and 77 and also includes terminal 72 which provides a connection to the cathode of diode 71. The second ESD device 83 comprises a zener diode 73 connected in parallel with the P-N diodes 20, 21 and optionally with the diodes 79 and 80. Device 83 has input/output terminals 12 and 81 and also includes terminal 74 which provides a connection to the cathode of diode 73. Devices 82 and 83 have a common connection to terminal 17 at the anodes of diodes 71 and 73 and diodes 15 and 21. Terminals 72 and 74 may be left floating, connected to each other, or connected to separate inputs to meet the requirements of different applications.

Fig. 9 shows a cross-sectional portion of an embodiment of ESD device 70 described in the description of fig. 8. The cross-section of device 70 is similar to the cross-section of device 60. However, device 70 includes isolation trenches 84 and 87 in place of trench 35. Device 70 also includes conductors 85 and 86 in place of conductor 54. Channel 84 extends from the surface of layer 33 through layer 33 and through region 29 into substrate 25. The slots 84 divide the layer 33 into a first portion and the slots 87 divide the layer 33 into a second portion. Slots 84 form a closed polygon on the surface of layer 33 that surrounds region 42, conductor 64, and a portion of plurality of conductors 56. Similarly, slots 87 form a closed polygon on the surface of layer 33 that surrounds region 48, conductor 62, and another portion of plurality of conductors 56. Thus, slots 84 and 87 divide the area previously surrounded by slot 35 (fig. 37) into 2 closed polygons. Since slots 84 and 87 extend through region 29, the two portions of layer 29 formed by slots 84 and 87 are laterally electrically isolated.

The two portions of the region 29 separated by the slots 84 and 87 form respective zener diodes 71 and 73. These two portions preferably extend outside the polygon formed by each of the slots 84 and 87. Each of the slots 84 and 87 also encompasses a portion, such as the first and second portions, of the region 44. Conductor 85 is formed to electrically connect a first portion of region 44 to form an electrical connection with a first portion of region 29 and thus with the cathode of diode 71. Conductor 86 is formed to electrically connect a second portion of region 44 to form an electrical connection with a second portion of region 29 and thus with the cathode of diode 73. Thus, slots 84 and 87 facilitate the formation of two ESD devices from one region 29.

Those skilled in the art will recognize that conductors 85 and 86 may be omitted from device 70, thereby eliminating terminals 72 and 74.

In another embodiment of device 70, slot 35 may be retained and slot 84 may be used to bisect the closed polygon formed by slot 35 into two closed polygons. For example, in fig. 7, slot 84 may extend laterally through at least slot 35, through layer 33, through region 44, and into another edge of slot 35 (as shown by the dashed lines in fig. 7).

Those skilled in the art will recognize that device 10 in fig. 1-3 may use slots 84 and 87 in place of slot 35. In addition, the region 44 may be omitted. For example, the embodiments simplify the process steps of such embodiments for forming the device 10.

Although the doping concentration given for region 29 is a preferred implementation for a 5 volt (5V) breakdown voltage for the respective diodes 18, 71 and 73, those skilled in the art will recognize that for other breakdown voltages, the doping concentration may have to be varied. For example, for a breakdown voltage of 80 volts (80V), the doping concentration of region 29 may be reduced, or the doping concentration of substrate 25 may be reduced, or the doping concentrations of region 29 and substrate 25 may be reduced.

In view of the foregoing, it is evident that a novel device and method is disclosed. Among other features, includes forming an ESD device with lateral current flow through the device rather than vertical current flow. In addition, the ESD device has a highly doped P-type substrate, a lightly doped N-type layer on the substrate, and a highly doped N-type layer disposed adjacent to a portion of the substrate and between the lightly doped N-type layers to form a Zener diode. A highly doped P-type layer is also included overlying the highly doped N-type layer to form a P-N diode. The doping concentration and thickness produce an ESD device that can respond to ESD events in less than 1 nanosecond (1 nsec.). Conductors 62 and 64 minimize capacitance mismatch between the channels of the ESD device, thereby reducing response time. The ESD device also includes a conductor slot 65 to reduce internal resistance.

While the subject matter of the present invention has been described with specific preferred embodiments, it is evident that many alternatives and variations will be apparent to those skilled in the semiconductor arts. For example, all doping types may be reversed. Those skilled in the art will recognize that trenches 37 and 39 may be removed if trench 35 remains and trench 35 omitted if trenches 37 and 39 remain, and that device 10 is functional and has a low capacitance to respond within the time interval described hereinbefore. Although the devices described herein are formed on a silicon substrate, those skilled in the art will recognize that other semiconductor materials may be used, including gallium arsenide, silicon carbide, gallium nitride, and other semiconductor materials. Also, the word "connected" is used throughout to clarify the description, however, it is intended to have the same meaning as the word "coupled". Thus, "connected" should be interpreted to include direct connections or indirect connections.

Claims (10)

1. An ESD device, comprising:

a semiconductor substrate having a first conductivity type and having a first doping concentration, the semiconductor substrate having first and second surfaces;

a first semiconductor layer of a second conductivity type on the first surface of the semiconductor base, the first semiconductor layer having a first surface opposite the first surface of the semiconductor base and having a second doping concentration;

a first semiconductor region of a second conductivity type between a first portion of the first semiconductor layer and the first surface of the semiconductor substrate, the first semiconductor region forming a zener diode with a dopant of the semiconductor substrate;

a first P-N diode formed within the first semiconductor layer and covering a first portion of the first semiconductor region;

a first blocking structure formed as a first closed polygon having a boundary surrounding the first P-N diode; and

a second P-N diode formed within the first semiconductor layer and outside of the first closed polygon.

2. The ESD device of claim 1, further comprising a first doped region of the second conductivity type formed on a surface of the first semiconductor layer and overlying a second portion of the first semiconductor region, the first doped region laterally separated from the first P-N diode.

3. The ESD device of claim 2, further comprising a third P-N diode overlying a third portion of the first semiconductor region and laterally spaced apart from the first P-N diode and the first doped region; and an isolation trench extending from the first surface of the first semiconductor layer through the first semiconductor layer, through the first semiconductor region, and into the semiconductor substrate, wherein the isolation trench is located between the first P-N diode and the third P-N diode.

4. The ESD device of claim 1, wherein the first blocking structure comprises a first conductor of the second conductivity type having a doping concentration greater than the second doping concentration, the first conductor extending from the first surface of the first semiconductor layer through the first semiconductor layer to the first semiconductor region, wherein the first conductor is formed to surround the first P-N diode on a boundary at the first surface of the first semiconductor layer.

5. The ESD device of claim 1, wherein the first blocking structure comprises an isolation trench extending from the first surface of the first semiconductor layer, through the first semiconductor region, and into the semiconductor substrate, wherein the isolation trench forms a multi-communication domain having a boundary parallel to a boundary of the first semiconductor region.

6. A method for forming an ESD device, comprising:

forming a plurality of steering diode channels, the steering diode channels including a first channel having a first P-N diode and a second channel having a second P-N diode;

coupling a zener diode in parallel with at least one of the first channel or the second channel;

providing a semiconductor substrate of a first conductivity type having a first doping concentration, the semiconductor substrate having first and second surfaces;

forming a first semiconductor layer of a second conductivity type having a second doping concentration less than the first doping concentration on the first surface of the semiconductor base, including forming the first semiconductor layer having a first surface opposite the first surface of the semiconductor base;

forming a first semiconductor region of the second conductivity type between a first portion of the first semiconductor layer and the first surface of the semiconductor substrate, wherein the zener diode is formed by the first semiconductor region;

forming a first conductor extending from the first surface of the first semiconductor layer through the first semiconductor layer and through the first semiconductor region, wherein the first conductor forms a first multi-communication domain surrounding a second portion of the first semiconductor layer; and

forming the first P-N diode in the second portion of the first semiconductor layer.

7. The method of claim 6, wherein the step of forming the first semiconductor layer on the first surface of the semiconductor substrate comprises: form not more than 1 × 10¹⁷Atom/cm³And forming of not less than 1 x 10¹⁹Atom/cm³The first doping concentration of (a).

8. The method of claim 6, further comprising: forming an isolation trench through the first semiconductor layer from the first surface of the first semiconductor layer, extending through the first semiconductor region, and into the semiconductor base, wherein the isolation trench forms a second multi-communication domain surrounding the first conductor and a third portion of the first semiconductor layer.

9. The method of claim 6, further comprising:

forming a doped region of the second conductivity type overlying the first semiconductor region on the first surface of the first semiconductor layer, the doped region being outside the second portion of the first semiconductor layer; and

a plurality of conductors are formed extending from the doped regions through the first semiconductor layer and through the first semiconductor region.

10. An ESD device, comprising:

a semiconductor substrate having a first conductivity type and having a first doping concentration, the semiconductor substrate having first and second surfaces;

a first semiconductor layer of a second conductivity type on the first surface of the semiconductor base, the first semiconductor layer having a first surface opposite the first surface of the semiconductor base and having a second doping concentration less than the first doping concentration;

a first semiconductor region of a second conductivity type between a first portion of the first semiconductor layer and the first surface of the semiconductor substrate, the first semiconductor region forming a zener diode with dopants of the semiconductor substrate;

a first P-N diode formed within the first semiconductor layer and covering a first portion of the first semiconductor region; and

a second P-N diode formed within the first semiconductor layer and overlying a second portion of the first semiconductor region, the second P-N diode being laterally spaced apart from the first P-N diode.