HK1111275A - Double data rate serial encoder - Google Patents

Abstract

A double data rate serial encoder is provided. The serial encoder comprises a mux having a plurality of inputs, a plurality of latches coupled to the inputs of the mux, an enabler to enable the latches to update their data inputs, and a counter to select one of the plurality of inputs of the mux for output. In another aspect, the mux provides a glitch-less output during input transitions. The mux includes an output selection algorithm optimized based on a priori knowledge of an input selection sequence provided by the counter.

Description

Double data rate serial encoder

Technical Field

The present invention relates generally to a serial encoder for a high data rate serial communication link. More particularly, the present invention relates to a double data rate serial encoder for a Mobile Display Digital Interface (MDDI) link.

Background

In the field of interconnect technology, the demand for ever increasing data rates, particularly in connection with video presentations, continues to grow.

The Mobile Display Digital Interface (MDDI) is a cost-effective, low power consumption delivery mechanism that enables very high speed data transfer between a host and a client over a short-range communication link. MDDI requires a minimum of only four leads plus power for bi-directional data transfer delivering a maximum bandwidth of up to 3.2 gigabits per second.

In one application, MDDI increases reliability and reduces power consumption of a flip phone (clamshell phone) by significantly reducing the number of wires that pass through the hinge of the handset to interconnect the digital baseband controller with the LCD display and/or camera. This reduction in leads also allows handset manufacturers to reduce development costs by simplifying flip or slide handset designs.

MDDI is a serial transfer protocol, and thus, data received in parallel for transmission over an MDDI link needs to be serialized. Accordingly, there is a need for a serial encoder that can be integrated in an MDDI link controller that supports the high speed data rate of MDDI.

Disclosure of Invention

In one aspect of the present invention, a double data rate serial encoder for MDDI is provided. The serial encoder includes a multiplexer having a plurality of inputs, a plurality of latches coupled to the inputs of the multiplexer, an enabler for enabling the latches to update their data inputs, and a counter for selecting one of the plurality of inputs of the multiplexer for output.

In another aspect of the invention, the multiplexer provides a glitch-free output (glitch-free) during input transitions. The multiplexer may include an output selection algorithm optimized based on a priori knowledge (priority knowledge) of the input selection sequence provided by the counter. The input selection sequence may be a Gray code (Gray code) sequence.

Further embodiments, features, and advantages of the present inventions, as well as the structure and operation of the various embodiments of the present invention, are described in detail below with reference to the accompanying drawings.

Drawings

The accompanying drawings, which are incorporated herein and form a part of the specification, illustrate the present invention and, together with the description, further serve to explain the principles of the invention and to enable a person skilled in the pertinent art to make and use the invention.

Fig. 1 is a block diagram illustrating an exemplary environment using a Mobile Display Digital Interface (MDDI) interface.

FIG. 1A is a diagram of a digital data device interface coupled to a digital device and a peripheral device.

Fig. 2 is a block diagram illustrating an MDDI link interconnect according to an embodiment of the example of fig. 1.

Fig. 3 is a block diagram illustrating the internal structure of an MDDI host core of the MDDI host of fig. 1.

Fig. 4 is a block diagram illustrating data flow within the MDDI host core of fig. 3.

Fig. 5 is a block diagram illustrating an MDDI serial encoder according to an embodiment of the present invention.

Fig. 6 is a circuit diagram illustrating an MDDI serial encoder according to another embodiment of the present invention.

Fig. 7 illustrates a multiplexer output selection algorithm responsive to a gray code input selection sequence.

FIG. 8 is an example illustration of an output glitch that may occur at the output of a multiplexer due to a select input transition and a data input transition.

FIG. 9 is an exemplary timing diagram for the input clock, select input, data input, and multiplexer output of FIG. 6.

The present invention will be described with reference to the accompanying drawings. The drawing in which an element first appears is typically indicated by the leftmost digit(s) in the corresponding reference number.

Detailed Description

This specification discloses one or more embodiments that incorporate the features of this invention. The disclosed embodiments are merely illustrative of the invention. The scope of the invention is not limited to the disclosed embodiments. The invention is defined by the appended claims.

References in the described embodiments, and specification to "one embodiment," "an example embodiment," etc., indicate that the embodiment described may include a particular feature, structure, or characteristic, but every embodiment may not necessarily include the particular feature, structure, or characteristic. Moreover, such phrases are not necessarily referring to the same embodiment. Further, when a particular feature, structure, or characteristic is described in connection with an embodiment, it is submitted that it is within the knowledge of one skilled in the art to effect such feature, structure, or characteristic in connection with other embodiments whether or not explicitly described.

Embodiments of the invention may be implemented in hardware, firmware, software, or any combination thereof. Embodiments of the invention may also be implemented as instructions stored on a machine-readable medium, which may be read and executed by one or more processors. A machine-readable medium may include any mechanism for storing or transmitting information in a form readable by a machine (e.g., a computing device). For example, a machine-readable medium may include Read Only Memory (ROM); random Access Memory (RAM); a magnetic disk storage medium; an optical storage medium; a flash memory device; electrical, optical, acoustical or other form of propagated signals (e.g., carrier waves, infrared signals, digital signals, etc.), and others. Further, firmware, software, routines, instructions may be described herein as performing certain actions. It should be understood, however, that such descriptions are merely for convenience and that such actions in fact come from computing devices, processors, controllers, or other devices executing the firmware, software, routines, instructions, etc.

Mobile Display Digital Interface (MDDI)

Mobile Display Digital Interface (MDDI) is a cost-effective, low power consumption transfer mechanism that enables very high speed serial data transfer between a host and a client over a short-range communication link.

Hereinafter, an example of MDDI will be provided with respect to a camera module included in an upper folder of a mobile phone. However, one skilled in the relevant art will appreciate that any module having functionally equivalent components to the camera module can be readily substituted and used in embodiments of the present invention.

Further, according to embodiments of the present invention, an MDDI host may comprise one of several types of devices that may benefit from using the present invention. For example, the host may be a portable computer in the form of a handheld, laptop, or similar mobile computing device. The host may also be a Personal Data Assistant (PDA), a paging device, or one of a number of wireless telephones or modems. Alternatively, the host may be a portable entertainment or presentation device (presentation), such as a portable DVD or CD player, or a gaming device. Further, the host may reside as a host device or control element in a variety of other widely used or planned commercially available products that require a high speed communication link with the client. For example, a host may be used to transfer data from a video recording device to a storage-based client at a high rate for improved response, or to a large screen of high definition for presentation. Appliances such as refrigerators that incorporate an on board inventory (on board inventory) or computing system and/or bluetooth connections to other home devices may have improved display capabilities when operating in the internet or bluetooth connection mode, or reduced wiring requirements for in-room displays (clients) and keypads or scanners (clients) when the electronic computer or control system (host) resides elsewhere in the enclosure. In general, those skilled in the art will appreciate the wide variety of modern electronic devices and appliances that may benefit from the use of such an interface, as well as the ability to retrofit older devices with higher data rates of information transfer with a limited number of conductors available in newly added or existing connectors or cables. Also, an MDDI client may include a variety of devices that may be used to provide information to an end user or to provide information from a user to a host. For example, microdisplays incorporated in goggles or glasses, projection devices built into hats or helmets, small screens or even holographic elements built into vehicles (e.g., in a viewing window or windshield), or various speakers, headphones, or sound systems for presenting high quality sound or music. Other presentation devices include projectors or projection devices for presenting information for meetings or movies and television images. Another example would be the use of touch pads or sensitive devices, voice recognition input devices, security scanners, etc., which may be invoked to convey a large amount of information from a device or system user with less actual "input" in addition to touch or sound from the user. In addition, the docking station (docking station) and car kit (car kit) or desktop kit (desk-top kit) of computers and the cradle of wireless telephones can act as interface devices to the end user or to other devices and equipment and use a client (e.g., an output or input device of a mouse) or host to assist in the transfer of data, especially where high speed networks are involved. However, the person skilled in the art will readily understand that the present invention is not limited to these devices, and there are many other devices on the market that are proposed for use that aim to provide the end user with high quality images and sounds, either in terms of storage and transmission or in terms of playback presentation. The present invention may be used to increase the amount of data processing between various elements or devices to accommodate the high data rates required to achieve a desired user experience.

FIG. 1A is a diagram of a digital data device interface 100 coupled to a digital device 150 and a peripheral device 180. Digital device 150 may include, but is not limited to, a cellular telephone, a personal data assistant, a smart phone, or a personal computer. In general, digital device 150 may comprise any type of digital device that acts as a processing unit for digital instructions and processing digital presentation data. Digital device 150 includes a system controller 160 and a link controller 170.

Peripheral devices 180 may include, but are not limited to, cameras, barcode readers, image scanners, audio devices, and sensors. In general, peripheral device 180 may include any type of audio, video, or image capture and display device in which digital presentation data is exchanged between the peripheral device and the processing unit. Peripheral device 180 includes a control block 190. For example, when peripheral 180 is a camera, control block 190 may include, but is not limited to, lens control, flash or white LED control, and shutter control. Digital presentation data may include digital data representing audio, image, and multimedia data.

Digital data interface device 100 communicates digital presentation data at a high rate via communication link 105. In one example, an MDDI communication link may be used that supports bi-directional data transfer with a maximum bandwidth of 3.2 gigabits per second. Other high rates of data transfer, higher or lower than this exemplary rate, may be supported depending on the communication link. Digital data interface device 100 includes a message interpreter module 110, a content module 120, a control module 130, and a link controller 140.

Link controller 140, located within digital data interface 100, and link controller 170, located within digital device 150, establish communication link 105. Link controller 140 and link controller 170 may be MDDI link controllers.

The video electronics standards association ("VESA") MDDI standard, which is incorporated herein by reference in its entirety, describes the requirements of a high-speed digital packet interface that allows a portable device to transfer digital images from a small portable device to a larger external display. MDDI employs miniature connector systems and thin flexible cables that are ideal for linking portable computing, communication and entertainment devices to emerging products such as wearable microdisplays. It also contains information on how to simplify the connections between the host processor and the display device in order to reduce the cost and increase the reliability of these connections. Link controllers 140 and 170 establish communication path 105 based on the VESA MDDI standard.

U.S. patent No. 6,760,772 (' 772 patent), entitled "Generating and optimizing a communication protocol and Interface for High Data Rate Signal Transfer," issued to zuu et al, 7/6, 2004, describes a Data Interface that uses packet structures to communicate digital Data between a host and a client over a communication path, where the packet structures are linked together to form a communication protocol for presentation Data. Embodiments of the present invention taught in the' 772 patent are directed to an MDDI interface. Link controllers (e.g., link controllers 140 and 170) use signal protocols that are configured to generate, transmit, and receive packets that form a communication protocol, and to form digital data into one or more types of data packets, where at least one type of data packet resides in a host device and is coupled to a client via a communication path (e.g., communication path 105).

The interface provides a cost-effective, low-power, bi-directional, high-speed data transfer mechanism over a short-range "serial" type data link, which is suitable for implementation with miniature connectors and thin flexible cables. Embodiments of link controllers 140 and 170 establish communication path 105 based on the teachings of the' 772 patent. The' 772 patent is incorporated herein by reference in its entirety.

In other embodiments, both link controllers 140 and 170 may be USB link controllers, or both may comprise a combination of controllers, such as, for example, an MDDI link controller and another type of link controller (e.g., a USB link controller, for example). Alternatively, link controllers 140 and 170 may comprise a combination of controllers, such as an MDDI link controller and a single link for exchanging acknowledgement messages between digital data interface device 100 and digital device 150. Link controllers 140 and 170 additionally may support other types of interfaces such as ethernet or RS-232 serial port interfaces. Additional interfaces may be supported as will be appreciated by those skilled in the relevant art based on the teachings herein.

Within digital data interface device 100, message interpreter module 110 receives commands from system controller 160 and generates response messages to system controller 160 via communication link 105, interprets the command messages, and routes the information content of the commands to the appropriate module within digital data interface device 100.

Content module 120 receives data from peripheral device 180, stores the data, and communicates the data to system controller 160 via communication link 105.

Control module 130 receives information from message interpreter 130 and routes the information to control block 190 of peripheral 180. Control module 130 may also receive information from control block 190 and route the information to message interpreter module 110.

Fig. 1 is a block diagram illustrating an exemplary environment using an MDDI interface. In the example of fig. 1, MDDI is used to interconnect modules across the hinge of the flip phone 100. It should be noted herein that while certain embodiments of the present invention will be described in the context of a particular example (e.g., MDDI interconnection in a flip phone), this is done for illustrative purposes only and should not be used to limit the invention to these embodiments. Based on the teachings herein one skilled in the relevant art will appreciate that embodiments of the present invention may be used in other devices, including any device that may benefit from having an MDDI interconnect.

Referring to fig. 1, a lower clamshell section 102 of a clamshell phone 100 includes a Mobile Station Modem (MSM) baseband chip 104. MSM104 is a digital baseband controller. The upper clamshell section 114 of the clamshell phone 100 includes a Liquid Crystal Display (LCD) module 116 and a camera module 118.

Still referring to fig. 1, MDDI link 110 connects camera module 118 to MSM 104. Typically, an MDDI link controller is integrated into each of camera module 118 and MSM 104. In the example of fig. 1, MDDI host 122 is integrated into camera module 122, while MDDI client 106 resides on the MSM side of MDDI link 110. Typically, the MDDI host is the master controller for the MDDI link. In the example of fig. 1, pixel data from camera module 118 is received and formatted into MDDI packets by MDDI host 122 before being transmitted onto MDDI link 110. MDDI client 106 receives the MDDI packets and re-converts them into pixel data in the same format as the pixel data generated by camera module 118. The pixel data is then sent to the appropriate block in MSM104 for processing.

Still referring to fig. 1, MDDI link 112 connects LCD module 116 to MSM 104. In the example of fig. 1, MDDI link 112 interconnects MDDI host 108 integrated into MSM104 with MDDI client 120 integrated into LCD module 116. In the example of fig. 1, display data generated by a graphics controller of MSM104 is received and formatted into MDDI packets by MDDI host 108 before being transmitted onto MDDI link 112. MDDI client 120 receives the MDDI packets and reconverts them into display data for use by LCD module 116.

Fig. 2 is a block diagram illustrating MDDI link interconnect 110 according to the example of fig. 1. As described above, one of the functions of MDDI link 110 is to transfer pixel data from camera module 118 to MSM 104. Thus, in the embodiment of fig. 2, frame interface 206 connects camera module 118 to MDDI host 122. Frame interface 206 is used to transfer pixel data from camera module 118 to MDDI host 122.

In general, camera module 118 receives pixel data from the camera through the parallel interface, stores the pixel data, and passes it to MDDI host 122 when the host is ready. MDDI host 122 encapsulates the received pixel data into MDDI packets. However, in order for MDDI host 122 to be able to transmit pixel data onto MDDI link 110, it is necessary to serialize the MDDI packets.

In the embodiment of fig. 2, serializer module 202, integrated within MDDI host 122, is used to serially shift out MDDI packets onto MDDI link 110. At the MSM end of MDDI link 110, deserializer module 204, integrated within MDDI client 106, reconstructs MDDI packets using serial data received over MDDI link 110. MDDI client 106 then removes the MDDI encapsulation and passes the parallel pixel data to the appropriate block of MSM104 via frame interface 208.

MDDI host core architecture

The MDDI host core provides a host-side hardware implementation of the MDDI specification defined by VESA (video electronics standards association). The MDDI host core interfaces with both an MDDI host processor and external connections that operate as specified in the MDDI specification.

Fig. 3 is a block diagram illustrating the internal structure of MDDI host core 300 of MDDI host 122. MDDI host core 300 includes a command processor (CMD) block 302, a Microprocessor Interface (MINT) block 304, a Register (REG) block 306, an MDDI Packet Builder (MPB) block 308, a direct access memory (DMA) interface (DINT) block 310, a data input/output (DIO) block 312, and a DIO padding block (Pad block) 314. The function of each block of MDDI host core 300 will now be described with reference to fig. 3.

CMD block 302 is responsible for processing commands issued by MDDI host 122 processor. Commands issued by the host processor include tasks such as powering up/down the MDDI link and generating certain MDDI packets.

The MINT block 304 is responsible for interfacing with the MDDI host processor. MDDI host processor uses MINT block 304 to set registers, read registers, and issue commands to MDDI host core 300. MINT block 304 passes processor commands to CMD block 302 and register read/write commands to REG block 306.

REG block 306 stores various registers necessary to transfer data over the MDDI link. Registers of REG block 306 control the behavior of the MDDI link and the configuration of MDDI host core 300.

MPB block 308 is responsible for generating MDDI packets to be transmitted over the MDDI link, as well as determining the transmission order. MDDI packets are created based on internal register values and data retrieved by DINT block 310.

DINT block 310 is responsible for interfacing with the DMA bus of MDDI host 122. DINT block 310 issues a burst request to an external SDRAM memory of MDDI host 122 to buffer data for MPB block 308. In addition, DINT block 310 helps MPB block 308 determine the order in which packets are transmitted on the MDDI link.

DIO block 312 is responsible for managing the physical MDDI link. DIO block 312 is responsible for host-client handshaking, data out, and round trip delay measurements. DIO block 312 receives data from MPB block 308 and passes it out to DIO pad block 314 block to be shifted out.

DIO fill block 314 receives parallel data from DIO block 312 and shifts it out serially onto the MDDI link. In essence, DIO pad block 314 is responsible for the serialization of data required for transmission over the MDDI link. As shown in fig. 3, DIO fill block 314 receives an MDDI input/output clock signal (MDDI _ IO _ CLK) from an MDDI host and outputs an MDDI data OUT (MDDI _ DOUT) and an MDDI strobe OUT (MDDI _ STB _ OUT) signal. In one example, DIO fill block 314 shifts out data at twice the MDDI input/output clock rate.

Fig. 4 is a block diagram illustrating the flow of data from MDDI host core 300. For simplicity of illustration, certain blocks of MDDI host core 300 have been omitted.

Typically, at MDDI link startup, output data is generated entirely within DIO block 312 for host-client handshaking. Once the handshake sequence is complete, MPB block 308 is allowed to direct the output stream of data received from the three sources. A sub-block of MPB block 308, MPB _ AUTOGEN block 402, generates packets inside MPB block 308. Data from MPB _ AUTOGEN block 402 is received on an 8-bit parallel bus. These packets include, for example, filler packets, round trip delay measurements, and link shutdown packets.

DINT block 310 of MDDI host core 300 routes packets received from an external SDRAM memory of MDDI host 122 to MPB block 308. DINT block 310 uses four 32-bit parallel buses to route data to MPB block 308. MDDI Data Packet (MDP) interface (MDPINT) block 404, which is a sub-block of MPB block 308, interfaces with MDP blocks external to the MDDI host core and typically receives video data packets for transmission. MDPINT block 404 interfaces with MPB block 308 using an 8-bit parallel bus.

MPB block 308 determines the transmission order of packets received from DINT block 310, MPB _ AUTOGEN block 402, and MDPINT block 404. MPB block 308 then directs the data to be transmitted over an 8-bit parallel bus to DIO block 312. DIO block 312 in turn forwards the data on an 8-bit parallel bus to DIO pad block 314. DIO pad block 314 serializes the data received from DIO block 312 for transmission over the MDDI link. Embodiments of DIO fill block 314 according to the present invention are discussed further below.

MDDI serial encoder

In essence, DIO fill block 314 comprises a serial encoder for MDDI. Fig. 5 is a block diagram illustrating an MDDI serial encoder 500 according to an embodiment of the present invention.

MDDI serial encoder 500 includes a block of latches 502, an enabler block 504, a counter block 506, and a multiplexer 508. The parallel data interface provides a parallel data stream 518 to the serial encoder 500. The parallel data streams are received and stored by latches 502. Counter 506 outputs an input selection sequence to control the output of multiplexer 508. In the embodiment of fig. 5, counter 506 periodically provides a set of select signals 512 to multiplexer 508 to select the output of multiplexer 508.

The enabler 504 updates its data inputs by using the signal obtained from the set of select signals 512 to provide a set of signals 514 to the latch 502 to enable the latch 502. A set of signals 510 couples latch 502 to the inputs of multiplexer 508. Thus, the data input of the latch 502 and the input of the multiplexer 508 are updated according to the input selection sequence generated by the counter 506.

Multiplexer 508 outputs serial data stream 520 onto the MDDI link. In one example, multiplexer 508 is an N: 1 multiplexer having N inputs and a single output, where N is an integer power of 2.

Fig. 6 is a circuit diagram illustrating an MDDI serial encoder 600 according to another embodiment of the present invention. In the embodiment of fig. 6, MDDI serial encoder 600 includes a first layer of latches 602, a second layer of latches 604, a multiplexer 606, a counter 608, and an enabler 610.

The first tier of latches 602 includes first and second sets of latches 612 and 614. Similarly, the second tier of latches 604 includes first and second sets of latches 616 and 618. The first and second sets of latches 612 and 614 of the first layer of latches 602 are coupled to the first and second sets of latches 616 and 618, respectively, of the second layer of latches 604. Each set of latches 612, 614, 616, and 618 includes a set of four D-latches. An input clock signal 640 is coupled to a clock input of each of the D latches in the first and second layers of latches 602 and 604.

The multiplexer 606 has a plurality of data inputs coupled to the outputs of the second tier latches 604. In addition, multiplexer 606 includes a set of select inputs provided by counter 608. Typically, the multiplexer has 2^NA number of data inputs, where N is the number of select inputs. In the embodiment of FIG. 6, multiplexer 606 has 8 data inputs and 3 select inputs b0, b1, and b 2.

Counter 608 includes a plurality of D-latches. In the embodiment of FIG. 6, counter 608 includes a set of three D-latches 620, 622, and 624. Clock signal 640 provides an input to counter 608. The outputs of the D-latches 620, 622, and 624 correspond to the select inputs b0, b1, and b2, respectively, of the multiplexer 606. Further, the outputs of the D-latches 620 and 624 are inputs to the enabler 610. The input clock signal 640 drives the counter 608.

Enabler 610 includes a plurality of AND gates. In the embodiment of FIG. 6, enabler 610 includes three AND gates 626, 628, AND 630. The inputs to AND gates 626, 628, AND 630 are obtained from the outputs of D latches 620 AND 624 of counter 608. The outputs of AND gates 626, 628, AND 630 are coupled to the second set of latches 618, the first set of latches 616, AND the first AND second sets of latches 612 AND 614, respectively.

The operation of MDDI serial encoder 600 will now be described.

Assuming that the serial encoder 600 has just started on the first rising edge of the input clock signal 640, the counter 608 outputs { b2, b1, b0} ═ 0, 0, 1 }. For this { b2, b1, b0} value, the outputs of AND gates 628 AND 630 of enabler 610 are true AND, therefore, the inputs of the first AND second sets of latches 612 AND 614 of first tier latch 602 AND the input of the first set of latches 616 of second tier latch 604 may be updated. Further, assuming that the clock signal 640 is at a rising edge, the outputs of the first and second sets of latches 612 and 614 follow their respective inputs. Similarly, the outputs of the first set of latches 616 of the second tier of latches 604 also reflect their respective inputs. However, the inputs of the second set of latches 618 of the second tier of latches 604 remain unchanged. The multiplexer 606 selects the input corresponding to the input select value 001 for output.

On the next falling edge of the input clock signal 640, the counter 608 outputs { b2, b1, b0} ═ 0, 1, 1 }. Assuming { b2, b0} ═ 0, 1}, the inputs to the first and second sets of latches 612 and 614 can be updated. However, since the input clock signal 640 is on a falling edge, the outputs of latches 612 and 614 will not still reflect the updated input. In other words, the outputs of latches 612 and 614 will remain the same. Thus, the input of latch 616 will remain the same as well. The multiplexer 606 selects the input corresponding to the input select value 011 for output.

On the next two rising and falling edges of the input clock signal 640, the counter 608 outputs { b2, b1, b0} ═ 0, 1, 0} and { b2, b1, b0} {1, 1, 0}, respectively. Neither the input nor the output of any set of latches changes.

On the next rising edge of the input clock signal 640, the counter 608 outputs { b2, b1, b0} ═ 1, 1, 1 }. For { b2, b0} - {1, 1}, the output of the AND gate 626 of the enabler 610 is true, AND thus, updates the inputs of the second set of latches 618 of the second tier of latches 604. Further, assuming that the input clock 640 is at a rising edge, the output of the latch 618 follows its respective input. The multiplexer 606 selects the input corresponding to the input select value 011 for output.

For the next three rising and falling clock edges, the counter transitions through the sequence b2, b1, b0 ═ 101, 100, 000. The inputs and outputs of all the bank latches 612, 614, 616, and 618 remain the same throughout these transitions. Subsequently, the input selection sequence returns { b2, b1, b0} ═ 0, 0, 1}, and the above loop begins anew.

In accordance with the description of the operation of MDDI serial encoder 600 above, it should be noted that counter 608 transitions on either the rising or falling edge of input clock signal 640, and multiplexer 606 outputs one bit on each edge of input clock signal 640. Thus, MDDI serial encoder 600 is a double data rate encoder. Furthermore, the input selection sequence b2, b1, b0 has a single bit that changes only at each counter transition. Thus, the input selection sequence output by counter 608 represents a gray code sequence.

Fig. 7 illustrates a multiplexer output sequence responsive to the gray code input selection sequence of the embodiment of fig. 6. From the multiplexer output sequence of fig. 7, it should be noted that multiplexer 606 sequentially selects the inputs coupled to the second set of latches 618 during the first half of the input selection sequence, and selects the inputs coupled to the first set of latches 616 for output during the lower half of the input selection sequence.

At the same time, the enabler 610 enables the first set of latches 616 during the upper half of the input selection sequence and the second set of latches 618 during the lower half of the input selection sequence for updating. Thus, the first and second sets of latches 616 and 618 are updated when not selected for output by the multiplexer 606.

Glitch-free output

In accordance with the present invention, multiplexer 606 of MDDI serial encoder 600 provides a glitch-free output during input select transitions. FIG. 8 is an example illustration of an output glitch that may occur at the output of a multiplexer due to transitions of select inputs and/or data inputs.

In the example of FIG. 8, the multiplexer 802 has four data inputs D0, D1, D2, D3 and two select inputs S0 and S1. The first output glitch 804 is due to a transition of the select input of the multiplexer. In the example, the input selection sequence S1, S0 is converted from 0, 0 to 1, 1 in order to change the multiplexer output from D0 to D3. However, due to the skew delay between the "0 to 1" transitions of S0 and S1, the input selection sequence { S1, S0} temporarily takes the erroneously selected value {0, 1} of the data input D1. Throughout the transition, a "0" glitch appears at the output of multiplexer 802 when the output should remain at a "1".

Typically, a glitch of the type of glitch 804 may occur at the output of the multiplexer whenever more than one select input changes value during an input select transition. Thus, to prevent such glitches from occurring at the output of multiplexer 606 of MDDI serial encoder 600, embodiments of the present invention use a gray code input selection sequence.

Another type of output glitch (illustrated as 806 in fig. 8) occurs due to a transition of the data input of the multiplexer. In the example of FIG. 8, the input selection sequence S1, S0 is converted from 0, 0 to 0, 1 in an input selection loop. However, due to a time lag (timing skew) between the select signals S1, S0 and the data signal D0, the data signal D0 changes value before the end of its select period. Throughout the transition, a "0" glitch appears at the output of multiplexer 802 when the output should remain at a "1". To prevent such glitches from occurring at the output of multiplexer 606 of MDDI serial encoder 600, embodiments of the present invention ensure that the data input to the multiplexer remains stable for one clock cycle before being used. This is done by delay matching the paths from the select inputs to the outputs of the multiplexers.

In addition to the two types of multiplexer output glitches illustrated in fig. 8, another type of output glitch may occur at the output of the multiplexer. This type of glitch is typically caused by timing imbalance between internal signals within the multiplexer itself, which causes the multiplexer to not select any input during an input transition. Thus, as long as an input transition is made between two data inputs, each having a value of "1", it is possible to see this type of glitch at the output of the multiplexer. To prevent such glitches, the output of multiplexer 606 of MDDI serial encoder 600 is designed such that it remains at a "1" throughout any input transition between two data inputs that both have a value of "1" at the time of the transition.

Optimized output selection algorithm

The output of multiplexer 606 of MDDI serial encoder 600 is controlled by the following output selection algorithm:

multiplexer output ═

(sn(2)AND sn(1)AND sn(0)ANDd(0)) OR (sn(2)AND sn(1)AND s(0)AND d(1))OR

(sn(2)AND s(1)AND sn(0)AND d(2)) OR (sn(2)AND s(1)AND s(0)AND d(3))OR

(s(2)AND sn(1)AND sn(0)AND d(4)) OR (s(2)AND sn(1)AND s(0)AND d(5))OR

(s(2)AND s(1)AND sn(0)AND d(6)) OR (s(2)AND s(1)AND s(0)AND d(7))OR

(sn(2)AND sn(1)AND d(1)AND d(0)) OR (sn(1)AND sn(0)AND d(4)AND d(0))OR

(sn(2)AND s(0)AND d(3)AND d(1)) OR (sn(2)AND s(1)AND d(3)AND d(2))OR

(s(2)AND sn(1)AND d(5)AND d(4)) OR (s(1)AND sn(0)AND d(6)AND d(2))OR

(s(2)AND s(0)AND d(7)AND d(5)) OR (s(2)AND s(1)AND d(7)AND d(6))；

Where s (n) represents the value of the nth select input of the multiplexer, sn (n) represents the inverse of s (n), and d (k) represents the value of the kth data input of the multiplexer. For example, in the case of the gray code input selection sequence of fig. 7, the data inputs D (0), D (1), … D (7) of the above equations correspond to D7, D0, D2, D1, D6, D5, D3, and D4, respectively.

As understood by those skilled in the relevant art, the first eight terms of the above equation relate to selecting the output of the multiplexer. The last eight entries ensure that the internal multiplexer glitches described above do not occur during input transitions. Furthermore, having a stable multiplexer input and using the gray code input selection sequence ensures that the other two types of output glitches described above do not occur.

The above output selection algorithm is optimized based on a priori knowledge of the multiplexer's input selection sequence. In other words, given an input selection sequence, the output selection algorithm is designed to provide glitch-free multiplexer outputs only for input transitions according to the input selection sequence. Thus, the output selection algorithm is independent of providing glitch-free outputs for input transitions that are not within the input selection sequence. This design choice of the present invention reduces the number of terms in the above output selection algorithm to the necessary minimum. Therefore, the physical size of the multiplexer is also reduced.

Exemplary timing diagrams

FIG. 9 is an exemplary timing diagram for the input clock, select input, data input, and multiplexer output of multiplexer 606. In the example of fig. 9, the input selection sequence { S2, S1, S0} is in accordance with the gray code input selection sequence illustrated in fig. 7.

It can be noted from fig. 9 that the input selection sequence S2, S1, S0 transitions at each rising or falling edge of the input clock, and the single selection input changes at each transition. The multiplexer output is less glitched and outputs a byte of data every 4 cycles of the input clock. Data bits D0, …, D7 are exemplary sequences that are used for illustrative purposes only and do not necessarily correspond to actual sequences in an implementation.

Conclusion

While various embodiments of the present invention have been described above, it should be understood that they have been presented by way of example only, and not limitation. It will be understood by those skilled in the relevant art that various changes in form and details can be made therein without departing from the spirit and scope of the invention. Thus, the breadth and scope of the present invention should not be limited by any of the above-described exemplary embodiments, but should be defined only in accordance with the following claims appended hereto and their equivalents.

Claims (23)

1. A double data rate serial encoder, comprising:

a multiplexer having a plurality of inputs;

a plurality of latches coupled to a plurality of inputs of the multiplexer and having a data input;

an enabler coupled to the latch to enable the latch to update its data input; and

a counter coupled to the multiplexer to select one of a plurality of inputs of the multiplexer for output.

2. The encoder of claim 1, wherein the multiplexer is an N: 1 multiplexer, where N is an integer power of 2.

3. The encoder of claim 1, wherein the multiplexer has eight inputs.

4. The encoder of claim 1, wherein the multiplexer provides a glitch-free output during a select input transition.

5. The encoder of claim 1, wherein the counter provides an input selection value to the multiplexer according to a gray code sequence.

6. The encoder of claim 5, wherein the multiplexer includes an output selection algorithm optimized based on a priori knowledge of the Gray code sequence.

7. The encoder of claim 6, wherein the output selection algorithm provides a non-interfering output only during input transitions according to the gray code sequence, thereby reducing the size of the multiplexer.

8. The encoder of claim 7, wherein the output selection algorithm selects the multiplexer output according to:

output ═ output

(sn(2)AND sn(1)AND sn(0)AND d(0)) OR (sn(2)AND sn(1)AND s(0)ANDd(1)) OR

(sn(2)AND s(1)AND sn(0)AND d(2)) OR (sn(2)AND s(1)AND s(0)ANDd(3)) OR

(s(2)AND sn(1)AND sn(0)AND d(4)) OR (s(2)AND sn(1)AND s(0)ANDd(5)) OR

(s(2)AND s(1)AND sn(0)AND d(6)) OR (s(2)AND s(1)AND s(0)AND d(7))OR

(sn(2)AND sn(1)AND d(1)AND d(0)) OR (sn(1)AND sn(0)AND d(4)ANDd(0)) OR

(sn(2)AND s(0)AND d(3)AND d(1)) OR (sn(2)AND s(1)AND d(3)ANDd(2)) OR

(s(2)AND sn(1)AND d(5)AND d(4)) OR (s(1)AND sn(0)AND d(6)ANDd(2)) OR

(s(2)AND s(0)AND d(7)AND d(5)) OR (s(2)AND s(1)AND d(7)ANDd(6))；

Wherein s (n) represents one bit of the input select value;

sn (n) denotes the inverse of s (n); and is

d (k) represents a bit of the input of the multiplexer.

9. The encoder of claim 1, wherein the counter transitions on a rising or falling edge of an input clock.

10. The encoder according to claim 9, wherein the multiplexer outputs a bit at each edge of the input clock.

11. The encoder of claim 1, wherein only a subset of the latches are updated when another subset of the latches are being selected for output by the multiplexer.

12. The encoder of claim 5, wherein the enabler enables the latch based on the input selection value generated by the counter.

13. The encoder of claim 1, wherein the encoder receives parallel input data and outputs it serially onto a serial communication link.

14. The encoder of claim 1, wherein the serial communication link is a Mobile Display Digital Interface (MDDI) link.

15. A serial encoder, comprising:

means for storing a plurality of input bits;

means for generating an input selection sequence; and

means for outputting the plurality of input bits in a serial manner according to the input selection sequence.

16. The serial encoder according to claim 15, further comprising:

means for updating the plurality of input bits in the storage.

17. The serial encoder according to claim 15, wherein the means for outputting provides a glitch-free output during an input transition in the input selection sequence.

18. A serial encoder according to claim 15, wherein the input selection sequence is a gray code sequence.

19. The serial encoder according to claim 18, wherein the means for outputting includes an output selection algorithm optimized based on a priori knowledge of the gray code sequence.

20. A serial encoder according to claim 19, wherein the output selection algorithm provides a non-interfering output only during input transitions according to the gray code sequence.

21. The serial encoder according to claim 17, wherein the input transition occurs on a rising or falling edge of an input clock.

22. The serial encoder according to claim 21, wherein the serial output means outputs a bit at each edge of the input clock.

23. A system, comprising:

a multiplexer having a plurality of inputs;

a plurality of latches coupled to a plurality of inputs of the multiplexer and having a data input;

an enabler coupled to the latch to enable the latch to update its data input; and

a counter coupled to the multiplexer to select one of a plurality of inputs of the multiplexer for output.