HK1109495B - Field effect transistor and method of its manufacture - Google Patents

Description

Field effect transistor and method for manufacturing the same

The application is as follows: 1998.11.13, application No. 98122326.5, entitled "field effect transistor and method of making same".

Technical Field

The present invention relates to field effect transistors, and more particularly, to DMOS transistors with trenches (trenches) and methods of fabricating the same.

Background

In the semiconductor industry, power field effect transistors, such as MOSFETs (metal oxide semiconductor field effect transistors), are well known. One type of MOSFET is a DMOS (double diffused metal oxide semiconductor) transistor. DMOS transistors typically include a substrate on which an epitaxial layer is grown, a doped source region, a heavily doped body (dopedhehavy body), a doped well having the same doping (p or n) as the heavily doped body, and a gate. In a trenched DMOS transistor, the gate is a vertical trench. The heavily doped body typically diffuses deeper than the trench bottom to minimize the electric field at the bottom corners of the trench to prevent avalanche breakdown from damaging the device. The trenches are filled with conductive polysilicon, which is typically over-etched to ensure complete removal of the polysilicon on the surfaces surrounding the trenches. This over-etching typically leaves a recess between the top of the polysilicon and the surface of the semiconductor substrate (i.e., the surface of the epitaxial layer). The depth of this recess must be carefully controlled so that it is shallower than the depth of the source region. If this recess is deeper than the source region, the source will miss the gate resulting in a high on-resistance and high threshold, which may become an inoperative transistor.

The source and drain junctions may be doped with p-type or n-type impurities; in either case, the heavily doped body is doped with the opposite impurity, e.g., p-type for n-type source and drain. DMOS transistors that dope the source and drain with p-type carriers are called "p-channel". In a p-channel DMOS transistor, applying a negative voltage to the gate of the transistor causes current to flow from the source region to the drain region through the channel region of the heavily doped body, the accumulation region of the epitaxial layer and the substrate. In contrast, a DMOS transistor in which the source and drain are doped with n-type carriers is called an "n-channel". In an n-channel DMOS transistor, a positive voltage is applied to the gate of the transistor to cause current to flow from the drain to the source.

It is desirable to have a DMOS transistor with a low source-drain resistance (Rds) when turned on_on) And low parasitic capacitance. It is also desirable to prevent "punch through" of the transistor structure. Punch-through occurs when a high drain-source voltage is applied to extend the depletion layer in the heavily doped body region to the source region, thereby forming an unwanted conductive path through the heavily doped body region when the transistor should be turned off. Finally, the transistor should have good "endurance", i.e. a high start-up current is required to turn on the parasitic transistor inherent in the DMOS transistor.

Typically, a large number of MOSFET cells are connected in parallel to form a single transistor. The cells may be arranged in a "closed cell" structure in which the trenches are arranged in a grid and the cells are surrounded by sides of the trench walls. Alternatively, the cells may be arranged in an "open cell" structure in which the trenches are arranged in a "stripe" fashion, with the cells being surrounded by only two sides of the trench walls. An electric field termination technique is used to terminate the junctions (doped regions) at the periphery (edge) of the silicon wafer on which the transistors are formed. This will cause the breakdown voltage to be higher than would be controlled by the characteristics of the active transistor cells in the central portion of the silicon only.

Disclosure of Invention

The present invention provides a field effect transistor having an open cell layout that provides good uniformity and high cell density and is easily scalable. Preferred trench DMOS transistors have low Rds_onLow parasitic capacitance, excellent reliability, resistance to avalanche breakdown degradation, and durability. Preferred devices also include field termination to enhance resistance to avalanche breakdown. The invention also features a method of making a trench DMOS transistor.

In one aspect, the invention features a field effect transistor that includes a semiconductor substrate having impurities of a first conductivity type; a plurality of gate forming trenches arranged substantially parallel to each other, each trench extending to a first depth in the substrate, the spaces between adjacent trenches defining a contact region; a pair of doped source regions on both sides of each trench, the source regions having impurities of a first conductivity type; a doped well having impurities of a second conductivity type opposite in charge to the first conductivity type, the doped well being formed in the semiconductor substrate between each pair of gate forming trenches; a heavily doped body formed within the doped well, the heavily doped body having a second depth less than the first depth of the trench; and a heavily doped body contact region defined at a surface of the semiconductor substrate along a length of the contact region, wherein the heavily doped body forms an abrupt junction with the well, and a depth of the heavily doped body is adjusted relative to a depth of the well such that a peak electric field of the transistor is spaced from the trench when a voltage is applied to the transistor.

Preferred embodiments include one or more of the following features. The doped well has a substantially flat bottom. The depth of the heavily doped body region is selected relative to the depth of the well and the trench so that the peak electric field is isolated from the trench when a voltage is applied to the transistor. The depth of the doped well is shallower than the predetermined depth of the trench. The groove has an arc-shaped top angle and a bottom angle. There is an abrupt junction at the interface between the heavily doped body and the well, creating a peak electric field in the interface region when a voltage is applied to the transistor.

In another aspect, the invention features an array of transistor cells. The array includes a semiconductor substrate; a plurality of gate forming trenches arranged substantially parallel to each other and extending in a first direction, the spaces between adjacent trenches defining a contact region, each trench extending in said substrate to a predetermined depth which is substantially the same for all of said gate forming trenches; a pair of doped source regions located on both sides of the trench and extending along the length of the trench; forming a doped heavily doped body near each source region between each pair of gate forming trenches, the deepest portion of each heavily doped body extending into the semiconductor substrate to an adjustable depth that is greater than the depth of the doped source region and less than the predetermined depth of the trench; a doped well surrounding each heavily doped body below the heavily doped body; and wherein the adjustable depth of the heavily doped body is such that when a voltage is applied to the array of transistor cells, a peak electric field will be isolated from adjacent trenches.

Preferred embodiments include one or more of the following features. The doped well has a substantially flat bottom. The depth of the heavily doped body region is selected relative to the depth of the well and gate forming trenches so that the peak electric field is isolated from the trenches when a voltage is applied to the transistor. The depth of the doped well is shallower than the predetermined depth of the trench. The groove has an arc-shaped top angle and a bottom angle. There is an abrupt junction at the interface between each heavily doped body and the corresponding well, so that when a voltage is applied to the transistor, a peak electric field is generated in the interface region. The array also includes an electric field termination structure surrounding the perimeter of the array. The electric field termination structure includes a well having a depth greater than a depth of the gate forming trench. The electric field termination structure includes a termination trench extending continuously around the perimeter of the array, preferably a plurality of concentrically arranged termination trenches.

In another aspect, the invention features a semiconductor chip (die) that includes (a) a plurality of DMOS transistor cells arranged in an array on a semiconductor substrate, each DMOS transistor cell including a gate-forming trench, each said gate-forming trench having a predetermined depth, the depth of all gate-forming trenches being substantially the same; and (b) an electric field termination structure surrounding a periphery of the array, extending in the semiconductor substrate to a depth greater than the predetermined depth of the gate forming trench.

Preferred embodiments include one or more of the following features. The electric field termination structure includes a doped well. The electric field termination structure includes a termination trench. The electric field termination structure includes a plurality of concentrically arranged termination trenches. Each DMOS transistor cell further includes a heavily doped body doped to a depth extending in the semiconductor substrate limited to less than a predetermined depth of a trench formed by the gate.

The invention also features a method of forming a heavily doped body structure for a trench DMOS transistor that includes (a) providing a semiconductor substrate; (b) implanting a first impurity into a region of the substrate at a first energy and dose; and (c) subsequently implanting a second impurity into said region at a second energy and dose, said second energy and dose being relatively less than said first energy and dose.

Preferred embodiments include one or more of the following features. The first and second impurities both include boron. The first energy is from about 150 to 200 keV. The first dose is from about 1E15 to 5E 15. The second energy is from about 20 to 40 keV. The second dose is from about 1E14 to 1E 15.

In addition, the invention features a method of forming a source of a trench DMOS transistor that includes (a) providing a semiconductor substrate; (b) implanting a first impurity into a region of the substrate at a first energy and dose; and (c) subsequently implanting a second impurity into the region at a second energy and dose, the second energy and dose being relatively less than the first energy and dose.

Preferred embodiments include one or more of the following features. The first impurity includes arsenic and the second impurity includes phosphorus. The first energy is from about 80 to 120 keV. The first dose is from about 5E15 to 1E 16. The second energy is from about 40 to 70 keV. The second dose is from about 1E15 to 5E 15. The source depth obtained in the completed DMOS transistor is from about 0.4 to 0.8 um.

In another aspect, the invention features a method of fabricating a trench field effect transistor. The method includes (a) forming an electric field termination junction around a perimeter of a semiconductor substrate; (b) forming an epitaxial layer on a semiconductor substrate; (c) patterning and etching a plurality of trenches in the epitaxial layer; (d) depositing polysilicon to fill the trenches; (e) doping the polysilicon with a first type of impurity; (f) patterning the substrate and implanting an opposite second type of impurity to form a plurality of wells between adjacent trenches; (g) patterning the substrate and implanting a second type of impurity to form a plurality of second impurity type contact regions and a plurality of heavily doped bodies over the well, each of the heavily doped bodies having an abrupt junction with respect to the well; (h) patterning the substrate and implanting a first type of impurity to provide a source region and a first impurity type contact region; and (i) applying a dielectric to the surface of the semiconductor substrate and patterning the dielectric to expose the electrical contact regions.

In accordance with another aspect of the present invention, there is provided a method of manufacturing a trench transistor, comprising: providing a semiconductor substrate having impurities of a first conductivity type; forming a trench extending to a first depth in a semiconductor substrate; forming a gate dielectric material layer along the trench walls of the plurality of trenches; filling the grooves with conductive materials, wherein the gate dielectric material layers are formed in the grooves; forming a doped well of a second depth in the substrate, the second depth being less than the first depth of the plurality of trenches, the doped well having impurities of a second conductivity type opposite the first conductivity type; forming a heavily doped body extending within a doped well to a third depth, the third depth being less than the second depth of the doped well, the heavily doped body having impurities of a second conductivity type and forming an abrupt junction with the well; forming a source region in the well, the source region having impurities of a first conductivity type; and adjusting the location of the abrupt junction relative to the depth of the well, thereby isolating the transistor peak electric field from the trench.

In the above method, further comprising a heavily doped region having impurities of the second conductivity type, the heavily doped region extending in the substrate to a fourth depth, the fourth depth being deeper than the first depth of the trench.

In the above method, the step of forming the deep doped region forms a PN junction diode with the substrate, the PN junction diode facilitating an increase in breakdown voltage of the transistor.

In the above method, the heavily doped region forms a termination structure around the perimeter of the substrate.

In the above method, the step of forming the heavily doped body includes a dual implant process.

In the above method, the dual injection process comprises: implanting a first impurity of the first conductivity type at a first energy level and a first dose to form a first doped region of a heavily doped body; and implanting impurities of the first conductivity type at a second energy level and a second dose a second time to form a second doped region of the heavily doped body.

In the above method, the first implant implants the heavily doped body as deeply as possible.

In the above method, the first energy level is higher than the second energy level.

In the above method, the first dose is higher than the second dose.

In the above method, the step of forming the heavily doped body includes a process of diffusing impurities of the second conductive type.

In the above method, the step of forming the heavily doped body includes using a continuous impurity source at the surface of the semiconductor substrate.

In the above method, the step of forming a plurality of trenches includes patterning and etching the plurality of trenches, the plurality of trenches extending in parallel along the longitudinal axis.

In the above method, further comprising forming a contact region on the substrate surface between adjacent trenches.

In the above method, the step of forming the contact regions comprises forming alternating source contact regions and heavily doped body contact regions.

Other features and advantages of the invention will become apparent from the following detailed description, and from the claims.

Drawings

Fig. 1 is a highly enlarged schematic perspective cross-sectional view illustrating a portion of a cell array including a plurality of DMOS transistors in accordance with an aspect of the present invention. The source metal layer and a portion of the dielectric layer are omitted to show the underlying layers. Fig. 1A and 1B are cross-sectional side views of a single row of transistors of the array of fig. 1 taken along lines a-a and B-B, respectively. In fig. 1A and 1B, the source metal and dielectric layers are shown.

Fig. 2 is a highly enlarged cross-sectional side view of a semiconductor chip showing a portion of the cell array and electric field termination.

Fig. 3 is a flow chart illustrating a photomask sequence for a preferred process for forming the trench DMOS transistor of fig. 1.

Fig. 4-4K are cross-sectional side views illustrating steps of the process shown in fig. 3. The figure numbers of the detailed figures in fig. 4-4K are shown incidentally below the corresponding boxes in fig. 3.

Fig. 5, 5A and 5B are graphs of diffusion resistance reflecting impurity concentration distributions in different regions of a transistor.

Detailed Description

In fig. 1, a cell array 10 is shown that includes a plurality of rows 12 of trench DMOSA transistor. The cell array 10 has an open cell structure in which the trenches 14 are arranged only in one direction instead of forming a grating. By making n⁺Source contacts 16 and p⁺The contacts 18 are arranged in parallel rows 20 staggered between the trenches 14 to form individual cells. Shown in cross-section in FIG. 1A with n⁺The structure of each row of regions of source contacts, with p being shown in FIG. 1B⁺The area of the contact.

As shown in fig. 1A and 1B, each trench DMOS transistor includes a doped n⁺A substrate (drain) layer 22, a lightly doped n-epitaxial layer 24, and a gate 28. Gate 28 comprises conductive polysilicon that fills trench 14. Gate oxide 26 coats the trench walls and underlies the polysilicon. The upper surface of the polysilicon is recessed a distance R (typically from about 0 to 0.4 μm) from the surface 30 of the semiconductor substrate. N is a radical of⁺Doped source regions 32A, 32B are located on either side of the trench 14. A dielectric layer 35 covers the trench opening and the two source regions 32A, 32B. p is a radical of⁺Heavily doped body regions 34 extend between the source regions of adjacent cells, under which is a flat-bottomed p-well 36. In the presence of n⁺In the cell array region of the contact 16, there is a shallow n⁺Doping contact region at n⁺Extending between the source regions. A source metal layer 38 covers the surface of the cell array.

The transistor shown in fig. 1A and 1B includes several features that enhance the endurance of the transistor and its resistance to avalanche breakdown degradation.

First, p is selected relative to the depth of the trench 14 and the flat bottom of the p-well⁺The depth of the body region 34 is heavily doped so that when a voltage is applied to the transistor, a peak electric field will occur midway between adjacent trenches. For different layouts, p⁺The preferred relative depths of the heavily doped body, the p-well and the trench are different. However, the preferred relative depth can be readily determined empirically (by observing the location of the peak electric field) or by finite element analysis.

Second, the bottom corners of the grooves 14 are curved (preferably the top corners are also curved; this feature is not shown). Can be used as submitted in 1997 on 10/2808/959,197Number U.S. under examinationThe process described in the application achieves the arc of the corner. The curved corners of the trenches will also move the peak electric field away from the trench corners and towards the middle between adjacent trenches.

Third, p⁺The abrupt junction at the interface between the heavily doped body and the p-well causes a peak electric field to be generated in the interface region. Avalanche multiplication is induced at the location of the peak electric field, which directs hot carriers away from the sensitive gate oxide and channel region. As a result, this structure improves reliability and avalanche endurance without sacrificing cell density as with deeper heavily doped body junctions. This abrupt junction may be achieved by a double doping process as described below or by other abrupt junction formation processes, most of which are well known in the semiconductor art.

Finally, referring to fig. 2, the array of cells is surrounded by electric field termination junctions 40, which increase the breakdown voltage of the device and conduct avalanche current from the array of cells to the periphery of the chip. The electric field termination junction 40 is deep p⁺The well, preferably having a deepest point of from about 1 to 3 μm, the depth being greater than p⁺The depth of body region 34 is heavily doped to reduce the electric field caused by the curvature of the junction. A preferred process for fabricating the above-described transistor is illustrated in the flow chart of fig. 3, with fig. 4-4K schematically showing the various steps. Note that some conventional steps that need not be explained are described below, and these steps are not shown in fig. 4-4K. The order of the steps shown in fig. 4-4K may be changed as indicated by the arrows in fig. 3 and described below. Additionally, some of the steps shown in FIGS. 4-4K are arbitrarily chosen, as described below.

A semiconductor substrate is initially provided. The substrate is preferably an N + + Si substrate having a standard thickness of, for example, 500 μm and a very low resistivity of, for example, 0.001 to 0.0050 hm-cm. It is well known to deposit an epitaxial layer on this substrate, preferably from about 4 to 10 μm thick. The resistivity of the epitaxial layer is preferably from about 0.1 to 3.00 hm-cm.

Next, the electric field termination junction 40 is formed by the steps shown in fig. 4-4C. In fig. 4, an oxide layer is formed on the surface of the epitaxial layer. The oxide thickness is preferably from about 5 to 10K. Next, as shown in FIG. 4A, the oxide layer is patterned and etched to define a mask, introducing p⁺Impurities to form deep p⁺The trap electric field is terminated. A suitable impurity is boron, at an energy of about 40 to 100keV and 1E14 (1X 10)¹⁴) To 1E16cm^-2The dose implantation of (2). As shown in fig. 4B, and then p is made, for example, by diffusion⁺Impurities enter the substrate at p⁺A field oxide layer is formed on the junction. The oxide layer preferably has a thickness of from about 4 to 10k. Finally, the oxide of the active area of the substrate (the area where the array of cells is formed) (fig. 4) is patterned and removed by a suitable etching process, leaving the field oxide only in the appropriate areas. This prepares the substrate for the following steps in forming the array of cells.

Note that, as an alternative to the method of steps 4-4 c, a suitable electric field termination structure may be formed with a ring-shaped trench surrounding the periphery of the cell array and capable of reducing the electric field and increasing the resistance to avalanche breakdown degradation. This trench field termination does not require active field oxide or deep p⁺The body junction is heavily doped. As a result, the number of process steps can be reduced. The use of a trench ring (or multiple concentric trench rings) to form an electric field termination is described, for example, in U.S. patent No. 5,430,324, which is incorporated herein in its entirety. The depth of the trench is preferably the same as the depth of the trench in the cell array.

The cell array is formed by the steps shown in fig. 4D-4K. First, a plurality of trenches are patterned and etched in an epitaxial layer of a substrate (fig. 4D). As described above, the grooves are preferably formed using the process described in U.S. copending application No. 08/959,197, whereby the top and bottom corners of each groove will become smoothly curved. As shown in fig. 1 and described above, the trench pattern is aligned in only one direction to define an open cell structure. After the trench is formed, a gate oxide layer is formed on the trench walls as is well known in the art. The gate oxide layer preferably has a thickness of from about 100 a to about 800 a。

Next, as shown in fig. 4E, polysilicon is deposited to a thickness of from about 1 to 2 μm to fill the trench and cover the substrate surface, depending on the trench width (as shown by the dashed line in fig. 4E). This layer is then planarized by its thickness versus trench width characteristics, typically from about 2 to 5k(as shown by the solid line in fig. 4E). Then, for example, by conventional POCL₃Doping or phosphorus implantation dopes the polysilicon to n-type. Since any further doping of the highly doped substrate is also less likely to enhance defect absorption, there is no need to strip the reverse side of the wafer (which is typically done before doping the polysilicon to enhance defect absorption).

The polysilicon is then patterned and etched with a photoresist mask to remove the polysilicon from the trench regions, as shown in fig. 4F. When the polysilicon is completely etched to remove all of the polysilicon from the substrate surface, a small recess is naturally left between the top of the polysilicon in the trench and the substrate surface. The depth of this groove must be controlled so that it does not exceed n to be formed in a later step⁺The depth of the source region. To reduce the need for control in this respect in the process, relatively deep n is formed, as described below⁺A source region.

Then, as shown in FIG. 4G, p is formed by implanting an impurity (e.g., boron implanted at an energy of 30 to 100keV and a dose of 1E13 to 1E 15) and bringing the impurity to a depth of about 1 to 3 μm using conventional introduction techniques^-And (4) a trap.

As shown by the arrow in fig. 3, may be at n⁺The next two steps (forming p) are performed before or after the source region is formed⁺A heavily doped body). P can be performed in either order⁺Formation of a heavily doped body and n⁺Formation of source regions because they are both a step of resist masking and in themWithout a diffusion step in between. This is advantageous in improving process flexibility. P performed before source formation will be described below⁺A heavy doping body forming step; it will be appreciated that n may be performed first by simply changing the order of the steps described below⁺And forming a source electrode.

First, as shown in FIG. 4H, the dopant is not doped to p⁺A mask is formed on the region. (Note that after the dielectric layer for the contact hole has been added and patterned (see FIG. 4K below) so that the dielectric itself provides a mask, if p is formed⁺Heavily doped bodies do not require this masking step). As mentioned above, p^-Well and p⁺The junction at the interface between the heavily doped bodies is preferably abrupt. For this purpose, a double implantation of an impurity (e.g., boron) is performed. For example, a preferred dual implant is a first boron implant having an energy of 150 to 200keV and a dose of 1E15 to 5E15 and a second boron implant having an energy of 20 to 40keV and a dose of 1E14 to 1E 15. High energy first implant makes p⁺The heavily doped body penetrates into the substrate as deep as possible, so that it does not compensate for n introduced later⁺A source region. Lower energy/lower dose second implant to p⁺The heavily doped body extends from the deep region formed in the first implant up to the substrate surface to provide p⁺A contact 18. P obtained during the process⁺The heavily doped body junction is preferably from 0.4 to 1 μm deep (the final junction depth after entry is preferably about 0.5 to 1.5 μm) and it includes a region of high impurity concentration near the p-well interface and p⁺The heavily doped body contacts a region at the surface where the impurity concentration is relatively low. A preferred concentration profile is shown in fig. 5.

One skilled in the art will appreciate that abrupt junctions can be formed by impurity diffusion, using a continuous source of impurities at the surface, or using atoms that diffuse more slowly, among many other ways.

In the formation of p⁺After heavily doping the body, a conventional resist stripping process is performed to remove the mask, and the new mask is patterned to prepare a mask for n formation⁺A substrate of the source region. The mask is n⁺A block mask, which is patterned to cover as shown in FIG. 4IThe cover will provide p⁺The substrate surface area of contact 18 (fig. 1 and 1B). This results in the formation of alternating p-type after n-type doping⁺And n⁺Contacts (see lines a-a and B-B and cross-sectional views a-a and B-B in fig. 4I corresponding to fig. 1A and 1B).

Then, double implantation is used to form n⁺Source region and n⁺And (4) a contact. For example, a preferred dual implant process is a first arsenic implant at an energy from 80 to 120keV and dose from 5E15 to 1E16, followed by a second phosphorus implant at an energy from 40 to 70keV and dose from 1E15 to 5E 15. Phosphorus implantation to form relatively deep n⁺The source region, as described above, thus allows more flexibility in the depth process for the polysilicon recess. The phosphorus ions will penetrate further into the substrate during implantation and in the subsequent diffusion step. Thus, n is favorably made⁺The region has a depth of about 0.4 to 0.8 μm after diffusion. Arsenic implant of n⁺The source extends to the surface of the substrate and also through p in the desired contact region⁺P-type surface compensation (conversion) of heavily doped bodies to n-type to form n⁺Contacts 16 (see fig. 1 and 1A). N along the edge of the trench is shown in FIGS. 5A and 5B, respectively⁺A source and n⁺Preferred sheet resistance curves for the contacts.

Thus, as described above, the substrate is patterned by using an appropriate mask and is provided with the first p⁺Implant and second n⁺Implanted to form p interleaved as shown in FIG. 1⁺And n⁺Contacts 18 and 16. This manner of forming staggered contacts facilitates the formation of open cell arrays having cell pitches less than typical pitches of such arrays, thereby increasing cell density and reducing Rds_on。

Then, conventional n is performed⁺To activate the impurities. Short cycles of preferably 10 minutes at 900 c are used to produce activation without excessive diffusion.

Then, a dielectric material such as borophosphosilicate glass (BPSG) is deposited over the entire substrate surface, the material is flowed in a conventional manner (FIG. 4J), and the dielectric is then patterned and etched to n⁺And p⁺Upper limit of contacts 16, 18The stationary contact opening.

As described above, at this point (rather than at n), if necessary⁺Before source formation) can be performed⁺The heavy body implantation step requires no mask, thereby reducing cost and process time.

The medium is then refluxed in an inert gas, for example, nitrogen purge. If p is injected just before this⁺Heavily doped body, this step is required to activate p⁺Impurities. If at n⁺P is injected before entering⁺The heavily doped body can be omitted if the edge of the dielectric surface around the contact opening is sufficiently smooth.

This array of cells is then completed by conventional metallization, passivation deposition and fusion steps well known in the semiconductor art.

Other embodiments are within the scope of the following claims. For example, although n-channel transistors are described above, the process of the present invention may also be used to form p-channel transistors. For this reason, the "p" and "n" in the above description may simply be reversed, i.e., "p" doping in the above regions will be exchanged for "n" doping, and vice versa.

Claims (28)

1. A field effect transistor, comprising:

a semiconductor substrate having impurities of a first conductivity type;

a plurality of gate forming trenches, each trench extending to a first depth in the substrate;

a doped well having impurities of a second conductivity type opposite to the first conductivity type, the doped well being formed in the semiconductor substrate between the plurality of gate forming trenches;

a plurality of doped source regions respectively located at both sides of the gate forming trench, each of the source regions extending to a second depth of the substrate, the source regions having impurities of a first conductivity type;

a heavily doped body formed in the doped well, wherein the depth of the heavily doped body is smaller than the first depth of the groove, and the depth of the doped well is deeper than the second depth of the source region; and

wherein the heavily doped body forms an abrupt junction with the well such that a peak electric field is isolated from the plurality of trenches when a voltage is applied to the plurality of trenches.

2. The field effect transistor of claim 1 wherein the abrupt junction has a depth such that a peak electric field is generated midway between adjacent gate forming trenches.

3. The field effect transistor of claim 1 wherein said heavily doped body has a region of high impurity concentration near said abrupt junction and doped well and a relatively low impurity concentration near said substrate surface.

4. The field effect transistor of claim 1 further comprising a heavily doped region having impurities of the second conductivity type, said heavily doped region extending into the substrate to a depth greater than said first depth of said plurality of gate-forming trenches.

5. The field effect transistor of claim 4 wherein said heavily doped region forms a PN junction diode with said substrate.

6. The field effect transistor of claim 4 wherein said heavily doped region forms a field stop structure around the periphery of a plurality of gate forming trenches.

7. The field effect transistor of claim 1 further comprising a field stop structure comprising a stop trench extending continuously around a perimeter of the plurality of gate forming trenches.

8. The field effect transistor of claim 7 wherein said field stop structure comprises a plurality of stop trenches arranged concentrically.

9. The fet of claim 1 wherein the plurality of trenches extend in parallel and the spaces between adjacent trenches define a contact region, the heavily doped body forming a continuous doped region along the entire length of the contact region.

10. The field effect transistor of claim 9 wherein said plurality of doped source regions extend along the length of the trench.

11. The field effect transistor of claim 10 further comprising a source contact region defined at a surface of the semiconductor substrate, the source contact region configured to contact the doped source region.

12. The field effect transistor of claim 10 further comprising a plurality of source contact regions disposed along the length of the contact region in alternating fashion with the plurality of heavily doped body contact regions.

13. The field effect transistor of claim 1 wherein between a pair of adjacent trenches, the heavily doped body extends between adjacent source regions.

14. The field effect transistor of claim 1 wherein between a pair of adjacent trenches, the heavily doped body extends continuously parallel to the longitudinal axis of the trench.

15. A method of fabricating a trench transistor, comprising:

providing a semiconductor substrate having impurities of a first conductivity type;

forming a plurality of gate forming trenches, each trench extending to a first depth in the semiconductor substrate;

forming a gate dielectric material layer along the trench walls of the trenches;

filling the grooves with conductive materials, wherein the gate dielectric material layers are formed in the grooves;

forming a doped well of a second depth in the substrate, the second depth being less than the first depth of the plurality of trenches, the doped well having impurities of a second conductivity type opposite the first conductivity type;

forming doped source regions on two sides of the gate forming groove respectively, wherein each source region extends to a third depth in the substrate and is provided with impurities of the first conduction type;

forming a heavily doped body extending to a fourth depth within a doped well, the fourth depth being less than the first depth of the trench, the second depth of the doped well being deeper than the third depth of the source region, the heavily doped body having an impurity of a second conductivity type and forming an abrupt junction with the well, wherein

The depth of the abrupt junction is selected relative to the depth of the well and gate forming trenches such that a peak electric field is spaced from the plurality of trenches when a voltage is applied to the plurality of trenches.

16. The method of claim 15 further comprising a heavily doped region having impurities of the second conductivity type extending into the substrate to a fifth depth, the fifth depth being deeper than the first depth of the trench.

17. The method of claim 16 wherein the step of forming a heavily doped region forms a PN junction diode with said substrate, said PN junction diode promoting an increase in the breakdown voltage of the transistor.

18. The method of claim 16 wherein the heavily doped region forms a termination structure around the perimeter of the substrate.

19. The method of claim 15 wherein the step of forming the heavily doped body comprises a dual implant process.

20. The method of claim 19, wherein the dual implant process comprises:

implanting a first implant of a second conductivity type impurity at a first energy level and a first dose to form a first doped region of a heavily doped body; and

a second implantation of impurities of the second conductivity type at a second energy level and at a second dose is carried out to form a second doped region of the heavily doped body.

21. The method of claim 20 wherein the first implant implants the heavily doped body as deeply as possible.

22. The method of claim 20, wherein the first energy level is higher than the second energy level.

23. The method of claim 22 wherein the first dose is higher than the second dose.

24. The method of claim 15, wherein the step of forming the heavily doped body comprises a process of diffusing an impurity of the second conductivity type.

25. The method of claim 15 wherein the step of forming the heavily doped body comprises using a continuous source of impurities at the surface of the semiconductor substrate.

26. The method of claim 15 wherein the step of forming a plurality of trenches comprises patterning and etching the plurality of trenches, the plurality of trenches extending parallel along the longitudinal axis.

27. The method of claim 15 further comprising forming contact regions on the substrate surface between adjacent trenches.

28. The method of claim 27 wherein the step of forming a contact region comprises forming a plurality of source contact regions and a plurality of heavily doped body contact regions in an alternating manner along the contact region.