HK1060647A - High speed, low voltage non-volatile memory - Google Patents

Description

High speed, low voltage non-volatile memory

The application is a divisional application of Chinese patent application with the application date of 1996, 7/19, and the application number of 96190845.9, entitled "high-speed and low-voltage nonvolatile memory".

Technical Field

The present invention relates to low voltage semiconductor non-volatile memories such as erasable programmable read-only memories (EPROMs), electrically erasable programmable read-only memories (EEPROMs) and flash electrically erasable programmable read-only memories (flasheproms).

Background

The primary benefit of transitioning from a standard 5 volt EPROM (Vcc voltage range of 4.5 to 5.5 volts) to a low voltage EPROM (with an unregulated Vcc voltage range of 2.7 to 3.6 volts) is that the low voltage EPROM consumes much less power. Several problems are encountered in implementing such Vcc voltage transitions.

First, older programming machines (e.g., EPROM programmers) are designed to program standard 5-volt EPROM and are generally incompatible with newer low-voltage EPROM's, primarily due to two separate problems.

The first problem is the output driver of EPROM. Speed is a major concern with low voltage EPROMs, and the output driver of an EPROM is the primary element in determining the EPROM read access time. To compensate for the lower Vcc values, low-voltage EPROMs incorporate large output drivers with large current start-up capability that provide faster rise and fall signal response rates at a given Vcc value. However, standard EPROM programmers typically use Vcc values of 6 volts or higher to verify program instructions. This high Vcc value can cause ringing and signal bouncing (ringing) in low voltage EPROM with large output drivers, and even damage to the EPROM. One way to solve this problem is to reduce the current drive capability of the low voltage EPROM, but this adversely affects the speed of the EPROM.

A second problem faced in using low voltage EPROM on a standard 5 volt EPROM programmer is the programmer algorithm rules themselves. EPROM memory can determine the logic level of a memory cell by comparing the amount of current that the memory cell can supply to a reference current. A memory cell is classified as erased if it supplies a large current compared to the reference current, but is classified as programmed if it supplies a smaller current compared to the reference current. When the erased memory cell is to be kept erased, it is possible to program the erased cell partially by an EPROM programmer. This means that the threshold voltage of the cell is raised slightly, but still low enough so that when verified with Vcc set to 6 volts or higher, enough current can be supplied for the EPROM programmer to verify the cell as erased. When the same EPROM is set to operate at a low voltage Vcc of 2.7 to 3.6 volts, the same memory cell that has been tested erased under high Vcc conditions may no longer be able to supply enough current to read as erased to read as programmed. Therefore, the memory cell can verify correct data under high Vcc conditions, but produce incorrect data under low Vcc conditions. Both of these problems prevent the use of low-voltage EPROM unless the user replaces or modifies an old EPROM programmer to work with the low-voltage EPROM.

In addition, the advantage of lower power consumption resulting from the transition from a standard 5 volt EPROM to a low voltage EPROM is generally accompanied by degradation of the EPROM performance. The lower Vcc voltage results in a lower voltage on the word line for a cell that translates to a lower memory cell current on the bit line. Since the memory takes more time to determine whether the memory cell is sourcing enough current to be classified as erased or programmed, a lower memory cell current in turn means a slower read count. This problem not only reduces the rate of the memory, but also reduces the yield and generally also degrades the performance of the memory.

In addition, the low voltage EPROM may use a voltage pump (voltage pump) to raise an internal voltage of the memory to a high voltage for a program operation. These voltage pumps are controlled by oscillators that specify the time for charge transfer to the charge storage capacitors of the voltage pumps. The oscillator is sensitive to Vcc variations and temperature variations. However, this is not typically a problem in prior art EPROMs because the voltage pump is only used in programming operations and the operation only takes up a small fraction of the EPROM operating time.

Other low voltage memories, such as low voltage EEPROMs and flash EEPROMs, also have some of the same problems that plague low voltage EPROMs. Similar to low-voltage EPROMs, low-voltage EEPROMs and flash EEPROMs are equipped with large output drivers with high current drive capability to compensate for lower Vcc values. If a low voltage EEPROM or a low voltage flash EEPROM were to be used in a standard 5 volt Vcc environment, the relatively high Vcc values would cause large output drivers to have noise issues such as ringing and signal bouncing. Similarly, by comparing the current bounce capability of the memory cell to a reference current, the EEPROM and flash EEPROM determine the logic level of the memory cell. Therefore, as described above, the low-voltage EEPROM and the flash EEPROM also have problems of slow reading times and erroneous data reading which plague the low-voltage EPROM.

Manufacturers have taken various measures to mitigate the negative effects of low voltage EPROM. Us patent 5,226,013 assigned to Secol et al describes a method of amplifying the voltage imbalance between the bit line cell and a reference voltage by precharging a bit line and terminating the charging of the bit line immediately after the cell has been read by a sense amplifier. U.S. patent 5,367,206 assigned to Yu et al discloses an output driver circuit that interfaces a low voltage EPROM to a standard 5 volt EPROM by incorporating a circuit that decelerates the output driver during standard 5 volt Vcc programming operations and accelerates the output driver during low voltage Vcc. U.S. patent 5,331,295 assigned to Jelinek also discloses an oscillator with temperature, voltage and process compensation. "EE Times" in an article at 5/10 1993 discusses the development by Toshiba corporation of EPROMs that can operate with Vcc set at 1.5 to 6 volts. The low side voltage of 1.5 volts is lower than the threshold voltage of the EPROM cell, so the word line boosting technique is used to raise the word line voltage to a read voltage of 4V. The boosted voltage is applied to the word line through the decoder switching from a programming voltage of 12.5V to a read voltage of 4V. Although the article does not describe toshiba's circuitry, the article mentions that their technology is limited to consumer or ASIC applications, which have limited EPROM densities.

It is an object of the present invention to provide a mechanism for improving the read access time of low voltage non-volatile memories.

It is another object of the present invention to provide a low voltage EPROM that is compatible with standard 5 volt EPROM programmers while allowing for increased speed and performance.

Disclosure of Invention

The above objects have been met in a low voltage non-volatile EPROM memory that monitors its Vcc voltage level and selectively enables and disables certain circuitry to improve performance under standard 5v Vcc and low voltage Vcc conditions.

The speed at which a non-volatile silicon memory operates is determined in large part by how quickly it can compare the current supplied by the memory cell to a reference current and make logic level decisions about the memory cell. Also, the speed at which a non-volatile silicon memory can make this comparison depends on the current sourcing capability of the memory cell, which is directly related to the voltage level on its word line.

Typically, the voltage level on a certain word line is close to Vcc. If Vcc is within the standard 5V voltage range of 4.5 volts to 5.5 volts, the word line may provide sufficient voltage to the memory cell to make it have a fast response time. However, if Vcc is lowered to a voltage range of 2.7 volts to 3.6 volts, such as is the case in commercially available low voltage memories, the voltage on the word line is likewise lowered to a similar voltage range. The lower current reduces the ability of the memory cell to source current, which increases the time required for the nonvolatile memory to determine the logic level of the memory cell, resulting in reduced performance.

Under standard 5 volt operating conditions, the memory of the present invention functions the same as any standard 5 volt non-volatile silicon memory, provided that the Vcc power rail is used directly to raise the word line to a similar voltage. Since Vcc is close to 5 volts, the output driver should not be as large as in the low voltage case, otherwise noise problems may arise. Therefore, the memory is connected to two output drivers per pinout, one of which is smaller and slower than the other. When placed in a standard 5 volt Vcc condition, the non-volatile memory employs a smaller output driver, and when placed in a low voltage Vcc condition, it employs a larger, faster output driver.

To compensate for the drop in Vcc during low voltage operation, the non-volatile memory of the present invention internally raises the voltage of the word line during read operations to a value that is higher than Vcc, preferably 3.5 volts to 5.5 volts. By raising the internal word line bias (bias) to a voltage range similar to that of a standard 5cc voltage condition, the memory of the present invention not only maintains a high speed similar to that of a standard 5 volt memory, but also eliminates the misreading condition that results from programming the low voltage EPROM cells with a standard 5 volt EPROM programmer but reading the low voltage EPROM cells under low voltage conditions.

This is accomplished by employing a word line bias circuit that consists of three read voltage pumps and a read oscillator that is common to all three read voltage pumps. The three read voltage pumps operate only during read operations, and each receive control signals mutually exclusively from a common read oscillator. The frequency of the read voltage pump is controlled by a temperature sensitive current source which can keep the frequency of the read oscillator relatively stable regardless of the change of voltage and temperature, thereby reducing unnecessary increase of power consumption. To further save power, the read voltage pump, read oscillator and temperature sensitive current source are activated only during read operations and are turned off when the memory is in idle mode or when V rises above low voltage Vcc.

Two of the three read voltage pumps work in concert to respond faster to the read oscillator and begin charging the word line. The control signals from the common read oscillator to the two read voltage pumps have similar frequencies but are in opposite phases. Thus, during any half cycle of the read oscillator, one of the two read voltage pumps transfers charge into the storage capacitor. This capability reduces read access time because no time is wasted in the activation of the word line charge from the time the read command is first received.

The charging of the word line, and therefore also the speed of the non-volatile memory, is further increased by a high voltage decoder for selectively transferring voltage from two read voltage pumps working in cooperation with each other to a word line with minimal distortion. The high voltage decoder generates a plurality of outputs, each of which employs a one shot circuit. The one-shot circuit is used to precharge the high voltage decoder output to Vcc, and then transfer control to two read voltage pumps working in concert with each other, which continue to charge the decoder output to a value higher than Vcc.

Each high voltage decoder output is applied to a native pass transistor (intrinsic pass transistor) that couples the decoder output to a respective word line. The intrinsic pass transistor is an n-type device built directly on a silicon substrate and has a threshold voltage of 0 volts.

Intrinsic n-type transistors used as pass devices have one disadvantage. The voltage applied to their control gates for the unselected pass devices is 0 volts, but because the threshold voltage of the intrinsic pass device is 0 volts, the unselected devices with 0 volts at their control gates are not completely in the "OFF" state and therefore can generate undesirable leakage currents. To solve this problem, the intrinsic pass transistor is coupled through a common n-type pass transistor to ground line VS, which is held at a voltage slightly higher than 0 volts by a VS generator. Therefore, when the intrinsic path transistor is not selected, a voltage higher than the ground potential is applied to the source electrode which completely turns the intrinsic path transistor in the "off" state.

These intrinsic path devices have control gates coupled directly to the output of the third read voltage pump. The high voltage on their control gates enables the intrinsic path devices to pass the high voltage signal from the output of the decoder onto their respective word lines. In addition, the voltage values delivered are controlled by the voltage on their control gates. Thus, during a read operation, the voltage applied to the word line is limited to the voltage at the output of the third read voltage pump.

The voltage level at the output of the third read voltage pump is regulated by a feedback circuit that monitors the output voltage of the voltage pump. When the output voltage from the third read voltage pump rises above a predetermined voltage range, the feedback circuit turns off the third read voltage pump, enabling the voltage pump to initiate discharge through a leakage transistor (1 ear transistor). However, the clamp diode does not allow the third read voltage pump to discharge below Vcc. Once the voltage level falls within the predetermined voltage range, the feedback circuit again activates the third voltage pump and turns off the small leakage transistor.

According to one aspect of the present invention, there is provided a low voltage memory comprising: means for receiving a power supply signal; a memory array having rows and columns of non-volatile memory cells, each row identified by a word line, each column identified by a bit line, each of the non-volatile memory cells is addressable by one of the word lines and one of the bit lines, the bit lines being coupled to an output driver circuit through sense amplifiers, and a read voltage pump circuit responsive to a read operation and operative to generate a voltage on a high voltage lead, the high voltage lead coupled with one of the word lines, the reading voltage pump circuit comprises a first reading voltage pump and a second reading voltage pump which work in cooperation with each other, the first reading voltage pump is provided with a first output signal, and a second read voltage pump having a second output signal, said first output signal being out of phase with said second output signal, said first and second output signals being coupled to said high voltage lead.

Drawings

Fig. 1 is a block diagram of a memory according to the present invention.

FIG. 2 is an internal diagram of the read word line bias circuit shown in FIG. 1.

FIG. 3 is a schematic diagram of a word line address decoding scheme in accordance with the present invention.

FIG. 4 is a functional block diagram of a preferred circuit for converting a high voltage to a word line during a read operation in accordance with the present invention.

Fig. 5 is a block diagram of the high-voltage decoder shown in fig. 4 in accordance with the present invention.

Fig. 6 is a block diagram of an output driver according to the present invention.

Detailed Description

Referring to fig. 1, a plurality of memory cells are arranged in rows and columns to form a memory array 36. The memory cells may be addressed by word lines to select a row of memory cells, by bit lines to select a column of memory cells. The addressed memory cell is located at the intersection of a word line and a bit line. Each memory cell has a digital address divided into two groups, one group being an X address identifying a row or word line of the memory cell, and the other group being a Y address identifying a column or bit line of the memory cell. The X address line AX is fed to the X decoder 30 to select a word line, and the Y address is decoded by the Y decoder 38 to select a bit line. After the memory cell is selected, the current through the selected memory cell is compared to a reference current by sense amplifier 40. If the selected cell is identified as erased, a predetermined first logic level (high or low) is sent to a set of input/output drivers 42. If the selected cell is identified as programmed, a second logic level, opposite the first logic level, is provided to the input/output driver 42.

The present invention also includes circuitry for raising the bias level (or voltage level) applied to a particular word line to a level higher than the input power supply signal Vcc during a read operation when Vcc is set at a low voltage condition (preferably 2.7 volts to 3.6 volts). When Vcc is set at a standard 5 volt condition of 4.5 volts or higher, the circuitry included above to raise the word line bias level is turned off and the memory directly biases the word line with Vcc.

Referring to FIG. 1, a high Vcc voltage detector 11 monitors the Vcc supply rail. If Vcc is set at a low voltage condition, high Vcc voltage detector 11 will activate read word line bias circuit 12, and this circuit 12 will output two signals: a pump high voltage signal (PHV) and a read gate pump voltage signal (RGPV). Both signals PHV and RGPV have a higher voltage value than Vcc and may be made equal, but it is preferable that signal PHV have a higher voltage than signal RGPV.

In fig. 2, the word line bias circuit 12 according to the present invention comprises two independent voltage pumps; a read wordline pump 48 for generating a pump high voltage signal PHV and a read gate pump 44 for generating a read gate pump voltage signal RGPV. However, if signals PHV and RGPV once had the same value, voltage pumps 48 and 44 may be replaced with a single voltage pump. Read word line pump 48 and read gate pump 44 both receive a control input from temperature sensitive read oscillator 46, temperature sensitive read oscillator 46 controlling the charge pumping frequency of the two voltage pump.

Referring to fig. 1, signal PHV is preferably made to have a value of 7 volts and is connected directly to high voltage decoder 25 and to the output of a program pump. Although the output of program pump 23 may be higher than the output of read word line bias circuit 12, no unexpected problems arise because read word line bias circuit 12 is only activated during read operations as determined by an input pin (not shown), and program pump 23 is only activated during program operations as determined by the same input pin. Signal RGPV (preferably having a voltage value of 4.5 volts) passes through a voltage latch bank (latchbank)34 to the control inputs of a set of pass devices 35.

The X decoder 30 decodes the word line address AX into two sets of signals; the X high voltage XHV fed to the high voltage decoder 25, and the X pass device XPD passed to the voltage latch bank 34 and the pass device 35. The high voltage decoder 25 is responsive to the XHV line to divert the pumped out (pumped) high voltage line PHV to one of its output lines DV. The voltage latch bank 34 will transfer the read gate pump voltage signal RGPV to one of the outputs determined by the XPD line. Thus, pass device 35 receives the PHV signal along one of the DV lines and the RGPV signal along one of the outputs from voltage latch bank 34. Pass device 35 then couples one of the DV lines carrying signal PHV to a single wordline as determined by voltage latch bank 34 and the XPD line. However, pass devices 35 are made to limit the voltage at their outputs (word lines) to a value similar to RGPV. In this manner, the selected word line will receive a voltage value similar to RGPV of about 4.5 volts.

For proper operation of high-voltage decoder 25 and pass device 35, the voltage required for the output of VS generator 29 is slightly above ground, as described below.

In fig. 3, a preferred word line decoding scheme is shown that consists of multiple decoding stages. The X decoder 30 divides a word line address AX0-AXm into two groups. A first group of address lines AX0 and AX1 is routed to a two-to-four (two-to-four) decoder to generate XHV decoder 27 which outputs four output signals XHV0-XHV 3. The second set of address lines AX2-AXm is routed to XPD decoder 28, and the output signals XPD0-XPDn of XPD decoder 28 are fed to voltage latch bank 34 and pass device 35.

Pass device 35 couples line PHV to a word line through high voltage decoder 25, voltage latch bank 34, and XPD decoder 28. The signal XHV0-XHV3 is fed to the high-voltage decoder 25, which, as instructed by the signal XHV0-XHV3, transfers the signal PHV to one of its four outputs DV0-DV 3. Each of the four high voltage decoder outputs DV0-DV3 is selectively coupled to a set of n wordlines through pass devices PA 0-PAn. For example, line DV0 may be selectively coupled to word lines WL00-WL0n, while word line DV3 may be coupled to word lines WL30-WL3 n. Pass device 35 then groups the word lines from each DV0-DV3 group into a group of four word lines that may be collectively selected by a voltage latch (voltage latch) in voltage latch bank 34. Thus, XHV decoder 27 selects one of four sets of n wordlines coupled to one of the four high voltage decoder outputs, DV0-DV3 and XPD decoder 28 selecting one wordline from the desired set of wordlines. XPD decoder activates one of voltage latches VL0-VLn31-33 from voltage latch bank 34, respectively, and voltage latch bank 34 transfers signal RGPV to the control gate of the corresponding PA pass device, while signals XPD1-XPDn couple the remaining unselected wordlines to VS generator 29.

The PA path device in the preferred decoding scheme is comprised of an intrinsic n-type path transistor having a threshold voltage of 0 volts. As described below, PA path devices require a positive voltage to be applied to the source electrode, placing it in a fully "off" state. Therefore, VS generator 29 outputs a slightly higher VS signal than ground, which is applied to the source electrode of the PA path device through the corresponding PB path device. If the signal VS is not applied to the unselected PA path devices leading thereto, each unselected PA path device will have a small on-current or leakage current when it is desired to turn off the device and there is no current. Since many PA channel devices can be used in decoding a word line, the collective leakage current from all the unselected PA channel devices causes unacceptably high power loss.

Returning to FIG. 1, if V is set at a standard voltage condition of 4.5 volts or higher, then the high V voltage detector 11 will turn off the read word line bias circuit 12 causing PHV and RGPV to start discharging. To couple the high voltage decoder 25 and pass device 35 to the Vcc power rail during standard 5 volt voltage conditions, the clamp diodes 20 and 24 clamp the signals RGPV and PHV, respectively, to Vcc when the clamp diodes 20 and 24 discharge to a value of approximately Vcc.

Referring to FIG. 4, to simplify the discussion of the preferred method of delivering high voltage to a word line during a read operation, only a single word line WL0n-WL3n for each of the high voltage decoder outputs DV0-DV3 is shown. Here, read word line pump 48 shown in fig. 2 is replaced by two read word line pumps 17 and 18. The high Vcc voltage detector 11 monitors the voltage level of Vcc. Whenever Vcc is set within a predetermined low voltage range (preferably 2.7 volts to 3.6 volts), it will send a high low power status signal LPS, enabling the two read wordline voltage pumps 17 and 18, the read gate voltage pump 19, the read oscillator 13 and the temperature sensitive current source 15. The temperature sensitive current source 15 outputs a control signal VMIR to directly control the frequency of the read oscillator 13. If Vcc rises to within some predetermined high voltage range (preferably 4.5 volts or more), which means that the word line can be charged directly to Vcc off, then the high Vcc voltage detector 11 will send a low LPS signal and thereby turn off all three read voltage pumps 17-19, read oscillator 13 and temperature sensitive current source 15.

Signals AX0, AX1, and XPDn are part of partially pre-decoded memory cell addresses that identify corresponding wordlines for a row of memory cells. The signals AX0 and AX1 are fed to an XHV decoder which generates four decoded signals XHV0-XHV 3. Signals XHV0-XHV3 control high voltage decoder 25, and high voltage decoder 25 selectively diverts pump high voltage line PHV to one of its four output terminals DV0-DV3 and places the VS ground signal on the remaining three output terminals.

The VS ground line has a slightly higher potential than the actual ground, preferably 0.3 volts. Which is generated by VS generator 29 and is used to ensure proper operation of the intrinsic n-type transistor (e.g., intrinsic n-type pass device PAn).

Unlike conventional enhancement mode n-type transistors, which have a threshold voltage above zero volts (typically 1 volt), intrinsic n-type transistors have a threshold voltage of 0 volts. Under normal operating conditions, a conventional enhancement-mode n-type transistor with its source grounded can be placed in a fully "off" state by applying 0 volts to the control gate. Intrinsic n-type transistors with 0 volts applied to the control gate, however, are not completely "off" under the same conditions. In an n-type transistor, the majority current carriers are electrons, and when an inversion layer is present, these electrons flow from an electrode (source) having a lower potential to an electrode (drain) having a higher potential. In the case of intrinsic n-type pass device PAn, the transistor electrode connected to the output of high voltage decoder DV0-DV3 will be at a higher potential than the other electrodes. This means that the electrode connected to the output of the high voltage decoder DV0-DV3 is the drain electrode and the other electrode is the source electrode. One of the conditions required to bring a transistor fully to the "off" state is that the voltage from the control gate to the source electrode must be below the threshold voltage of the transistor. In the case of an intrinsic n-type transistor, the threshold voltage is 0 volts and, therefore, a negative voltage is required from the control gate to the source electrode. In order for there to be a negative voltage for 0 volts applied to the control gate, the voltage of the source electrode must be raised to a potential higher than 0 volts. By raising the voltage at the source electrode to the value of 0.3 volts for the VS line, a voltage drop of-0.3 volts is generated from the control gate to the source electrode. This voltage drop is below the threshold voltage of the intrinsic n-type transistor, thereby placing the intrinsic n-type pass device PAn in the desired fully "off state.

At start-up, the read oscillator 13 will maintain a relatively constant frequency regardless of what temperature changes or Vcc level changes occur. This is due to the temperature sensitive current source 15 which directly controls the frequency of the read oscillator 13. Since the frequency of the read oscillator 13 does not deviate much, the power consumption thereof does not deviate much. The read oscillator 13 generates signals OSC1-OSC3 to control the pumping of all three read voltage pumps 17-19.

Each read voltage pump 17-19 places a charge on a corresponding internal storage capacitor as long as the read voltage pump control signals OSC1-OSC3 are high. First and second read wordline voltage pumps 17 and 18 together generate a high voltage on a pump high voltage line PHV that is transferred to a wordline WL0n-WL3n through high voltage decoder 25 and pass device 35. The read gate voltage pump 19 generates a high voltage signal RGPV that is applied to the control gate of each intrinsic path device PAn through a voltage latch VLN 33.

To save energy, when the memory is not being read, the memory enters an idle mode in which the memory turns off secondary circuits, such as the read oscillator 13, the temperature sensitive current source 15 and the read voltage pump 17-19. When a system user issues a read command, the memory must open all the circuitry required for the read operation, including the read oscillator 13, temperature sensitive current source 15, and read voltage pumps 17-19 described above. The speed at which these devices are enabled will greatly affect the read access time of the memory. When the read oscillator 13 is first started, it may start from the low half of its cycle. The read voltage pumps 17-19 collect charge during the lower half of the read oscillator cycle and transfer the collected charge onto the internal storage capacitors for boosting the voltage on their outputs during the upper half of the read oscillator cycle. This means that the storage capacitor receives no charge for up to half the initial period of the read oscillator.

For this reason, the OSC1 and OSC2 control signals arriving at the read word line voltage pumps 17 and 18, respectively, from the read oscillator 13 are at similar frequencies but opposite phases. That is, OSC2 is low when OSC1 is high, and OSC1 is low when OSC2 is high. Thus, during either half of the read oscillator cycle, one of the two read wordline voltage pumps 17 or 18 transfers charge to its internal storage capacitor. Thus, one of the two read word line voltage pumps 17 or 18 will coincide with the initial start-up of the read oscillator 13. The initiation of the transfer of charge onto its output is made to help the memory respond faster to read instructions and reduce the read access time of the memory.

The outputs of the read wordline voltage pumps 17 and 18 are connected together to form a pump high voltage signal PHV which is connected to a high voltage decoder 25. When the read word line voltage pumps 17 and 18 are turned off, the signal line PHV can discharge to Vcc through the intrinsic n-type transistors that make up the clamp diode 24. A separate programming pump 23, which has its own programming oscillator (not shown) and is used only during programming operations, also has its output connected to the same PHV signal. This is very different from the prior art, where the read word line voltage and the program word line voltage take different signal paths.

As described above, the high voltage decoder 25 transfers the PHV signal to one of its four output terminals DV0-DV3 and places the VS signal on the remaining three output terminals, which are determined by the decoded input signals XHV0-XHV3 and its input VS signal. Only one of the XHV0-XHV3 signals can be high at any time, so if XHV0 is high, the PHV will be transferred to DV 0. If XHV1 is high, the PHV will be transferred to DV1, and so on until XHV 3.

As can be seen in fig. 5, the high voltage decoder 25 is comprised of four cells 51-54, each cell including a high voltage latch 37, a one shot circuit 39, an inverter 41, an enhancement n-type transistor 47 and two intrinsic n-type transistors 43 and 45. The PHV signal is connected to the drain of each high voltage latch 37 and each corresponding intrinsic n-type transistor 43. When the decode signal (e.g., XHV0) is high, it will activate the high voltage latch 37, which will pass the PHV signal onto the control gate of intrinsic n-type transistor 43.

In order to transfer the PHV signal with minimal distortion from the drain electrode to the source electrode of intrinsic n-type transistor 43, signal DV0, the same PHV signal described above, must be applied to the control gate of intrinsic n-type transistor 43. One of the requirements required to place a transistor in an active "on" state is that the voltage from the control gate to the source electrode must be equal to or greater than the threshold voltage of the transistor. In this example, the threshold voltage of the intrinsic n-type transistor 43 is 0 volts, so the control gate voltage must be at least equal to or greater than the source voltage. Thus, if the voltage output of the PHV is transferred unimpeded from the drain electrode to the source electrode, the value of the voltage on the control gate must also be equal to PHV.

The decoded signal XHV0 is also connected to the one-shot circuit 39 and the inverter 41. There is an inherent time delay from the time XHV0 first activates the high voltage latch 37 and the time when the high voltage latch 37 and intrinsic n-type transistor 43 begin to transfer the PHV signal from the drain of the n-type transistor 43 to its drain (DV0 line). Additionally, the PHV requires a set amount of time to pump its voltage up to a value higher than Vcc.

The purpose of one-shot circuit 39 and inverter 41 is to precharge the DV0 line to Vcc, and then transfer control to high voltage latch 37 and intrinsic n-type transistor 43 so that they can continue to charge the DV0 line up to some value above Vcc. The high on XHV0 causes inverter 41 to place a low signal onto transistor 47, causing it to separate DV0 from line VS. In addition, a high signal on XHV0 activates one shot circuit 39 to begin applying a high signal pulse of predetermined duration on the control gate of intrinsic n-type transistor 45. This high signal couples the DV0 line to the Vcc power conductor for the duration of the pulse, thereby charging the DV0 line to Vcc. If the high power latch 37 and intrinsic path device 43 begin to transmit a PHV signal at a higher potential than Vcc to the DV0 line during the time that the one-shot circuit has a high pulse on the transistor, then the PHV signal will also be electrically coupled to Vcc through line DV0 and transistor 45. This will prevent line PHV from charging the DV0 line to a value higher than Vcc. Therefore, the duration of the active high pulse of primary pulsing circuit 39 must be long enough to precharge the DV0 line to Vcc, but short enough to turn it off when the line PHV pump is raised to a certain value above Vcc.

On the other hand, if the decoded signal line XHV0 has a low signal, that is, if this signal line is not selected, then one shot circuit 39 will maintain a constant low signal on intrinsic n-type transistor 45 and will not initiate a high pulse. Similarly, the high voltage latch 37 will maintain a constant low signal on the intrinsic n-type transistor 43 and not pass the PHV signal to the control gate of transistor 43.

Having a low signal of 0 volts on the control gates of intrinsic n-type transistors 43 and 45 would not necessarily place them in a fully "off" state. In order to properly turn off these devices, their source electrodes must be at a higher potential than their control gates. To this end, inverter 41 applies a high signal to transistor 47 which couples line VS, carrying a voltage value of about 0.3 volts, to line DV0 and thus to the source electrodes of intrinsic n-type transistors 43 and 45.

Thus, one of the output terminals DV0-DV3 of the high voltage decoder 25 will have a voltage value similar to PHV, while the other three output terminals will have a voltage value similar to VS.

However, before lines DV0-DV3 can be transferred to word lines WL0n-WL3n, they must first pass through one of the corresponding intrinsic n-type pass devices PAn, as shown in FIG. 4. Intrinsic n-type pass devices PAn receive their control gate signals from voltage latch V1n (reference numeral 33), and voltage latch V1n receives inputs from read gate voltage pump 19 and the pre-decoded X-pass device address signal XPDn.

Like the read wordline voltage pumps 17 and 18, the read gate voltage pump 19 receives its control signal OSC3 from the read oscillator 13 and an enable signal LPS from the high Vcc voltage detector 11. However, the read gate voltage pump 19 also receives a further enable signal CLMP from the feedback controlled voltage pump 21 and places its output value on its read gate pump voltage line RGPV. Its output value RGPV reaches not only the voltage latch V1n but also the feedback controlled voltage clamp 21.

During a read operation, it is important that the voltage on word lines WL0n-WL3n, and thus also on the memory cells, not increase above 5.5 volts, otherwise the memory cells could give false data, or even change the data they store. The voltage on word lines WL0n-WL3n is made substantially similar to the voltage on RGPV lines, as described below. Therefore, the voltage level on line RGPV is regulated to a predetermined voltage range, preferably in the range of 3.5 volts to 5.5 volts, by feedback controlled voltage clamp 21, clamp diode 20, inverter 26 and leakage transistor 22.

The feedback controlled voltage clamp 21 consists of a voltage detector (not shown) and when the voltage on RGPV rises to within a preferred predetermined voltage range of 3.5 volts to 5.5 volts, the feedback controlled voltage clamp 21 issues a low signal on the CLMP line. The low CLMP signal on read gate voltage pump 19 internally overrides the OSC3 control signal and shuts down the pump so that line RGPV can begin to discharge to a low voltage through leakage transistor 22, the gate of leakage transistor 22 being controlled by the output of inverter 26, the input of which is from the CLMP line. Leakage transistor 22 accelerates the discharge of line RGPV to reduce the time that the memory cell is compromised because line RGPV is at a sufficiently high voltage. The clamp diode 20, which is comprised of an intrinsic n-type transistor, prevents the line RGPV from discharging below Vcc. When RGPV falls within its aforementioned predetermined voltage range, feedback control voltage clamp 21 restarts read gate voltage pump 19 by applying a high signal to CLMP which also turns leakage transistor 22 off. When the output of feedback controlled voltage clamp 21 rises above a predetermined value, using feedback controlled voltage pump 21 to turn off read gate voltage pump 19, instead of using an upper limit clamp diode, reduces the power consumption of the memory as in the common prior art method of clamping a voltage pump. If a ceiling clamp diode is used, the read gate pump 19 will operate constantly during read operations. Because the voltage on line RGPV is clamped at, for example, 5.5 volts, all excess charge generated by read gate pump 19 is transferred to the Vcc supply rail instead of charging line RGPV and is wasted.

The low on line XPDn causes voltage latch VLn33 to transfer the voltage on line RGPV to the control gate of intrinsic n-type pass device PAn and further turns off pass device PBn which isolates word lines WL0n-WL3n from VS generator 29. Because intrinsic n-type pass devices PAn are intrinsic n-type transistors, the voltage on their source electrodes cannot be higher than the voltage on their control gates when they are in the active "on" state, as described above. Therefore, even if the voltage lines DV0-DV3 of their drain electrodes are much higher than the voltage on their control gates, the voltage values transferred from their drain electrodes DV0-DV3 to their source electrodes WL0n-WL3n are limited to the voltage values on their control gates. In this manner, the voltage level on word lines WL0-WL3 is clamped at the same level as line RGPV.

At the same time, before the voltage on line PHV is transferred to one of lines DV0-DV3, it must wait until XHV decoder 27 decodes lines AX0 and AX1 and wait until high voltage decoder 25 selects an output, and the voltage on line RGPV is transferred directly to the control gate of intrinsic n-type pass device PAn through voltage latch VLn33 immediately after the XPDn line goes low. As a result, the line connecting the output of the voltage latch VLn to the control gate of the intrinsic n-type pass device PAn is initially at a higher potential than the DV0-DV3 line. Thus, the DV0-DV3 signals are converted into corresponding WL0n-WL3n signals more quickly.

If the XPDn line is high, the voltage latch VLn will place 0 volts on its output. In addition, the high signal on XPDn causes pass device PBn35 to couple line VS with wordlines WL0n-WL3 n. This not only lowers the voltage on lines WL0n-WL3n to the value of VS, but also necessitates proper turn-off of intrinsic n-type pass device PAn and elimination of current leakage from intrinsic n-type pass device PAn, as described above.

Because the memory according to the present invention operates at a low voltage with Vcc in the range of 2.7 volts to 3.6 volts and a standard 5 volt Vcc range of 4.5 volts or higher, there are two output drivers per output signal. Referring to fig. 6, the first OUTPUT driver 55 is made larger than the second OUTPUT driver 57, but both receive a common DATA signal DATA _ OUT (OUTPUT DATA) placed on the memory OUTPUT lines. The first and larger output driver 55 is used when the memory is operating at low voltage Vcc, and the second and smaller output driver 57 is used when the memory is operating at standard Vcc of 4.5 volts or higher. The smaller output driver 57 exhibits a slower signal response speed to rise and fall times than the larger output driver 55. This reduces the noise problem of ringing and signal jitter that occurs when using a larger output driver 55 with a faster signal response speed under the same standard Vcc conditions. To ensure that only one output driver is active at a time, both receive the same LPS start signal, but the first output driver 55 has a high start-up capability (active high enable) and the second output driver 57 has a low start-up capability (active low enable). So when LPS is high (which means the memory is in a low voltage Vcc condition), the first and larger output driver 55 is enabled and the second output driver 57 is turned off. However, when LPS is low (which means the memory is in a standard 5 volt Vcc condition), the output driver 57 is enabled and the first output driver 55 is turned off.

The invention disclosed applies to low voltage EPROM, but the invention itself is a means of connecting low voltage memory to standard 5 volt V devices through a second slower output driver corresponding to each output lead, and a means of improving read access time under low voltage Vcc conditions by flashing to raise the internal voltage level of the word line to a value higher than Vcc during read operations. Without major deviation, the person skilled in the art can apply the invention to other low voltage memories that use word lines to select memory cells and determine their state by means of a current through the corresponding bit line. For example, the present invention can be applied to a low-voltage EEPROM or a low-voltage flash EEPROM. Both types of memory share a data bit access scheme similar to that used in an EPROM, where the EPROM employs word and bit lines to enable a transistor through which the stored information is read as a function of the current on the bit line.

Claims (1)

1. A low voltage non-volatile memory, comprising:

a means for receiving a power-on signal,

a main memory core coupled to the power supply signal and configured as an array of rows and columns of non-volatile memory cells, each cell addressable by a word line and a bit line,

an output driver circuit to drive an output pin, one of the bit lines coupled to the output pin through a sense amplifier and the output driver circuit, the output driver circuit including a first output driver and a second output driver, the first and second output drivers receiving a common input signal, the first and second output drivers having an output signal connected to the output pin, the first output driver having a faster logic transition response rate than the second output driver and being enabled in response to the supply signal being below a predetermined voltage value, and the second output driver being enabled in response to the supply signal being above the predetermined voltage value.