HK1035932B - Fast acquisition, high sensitivity gps receiver - Google Patents

Description

Fast acquisition high sensitivity GPS receiver

RELATED APPLICATIONS

This application is a partial continuation of U.S. patent application 06/037,904 entitled "fast acquisition, high sensitivity GPS receiver," filed on 1997, 11/2, the same inventor as this application, is Norman f.

Technical Field

The present invention relates generally to the field of global positioning systems, and more particularly to receiving and tracking satellite signals in an integrated fast acquisition high sensitivity receiver.

Background

The most commonly used "global positioning system" (GPS) receivers employ serial correlators to acquire, track and demodulate the signals transmitted by the Navstar satellites. Each transmitted GPS signal is a direct sequence spread spectrum signal. The commercially used signal is related to Standard Positioning Service (SPS) and employs a direct sequence, two-phase spread signal with a rate of 1.023 million chips per second at a carrier frequency of 1575.42 MHz. The pseudo-random noise (PN) sequence length is 1023 chips, corresponding to a time period of 1 millisecond. Each satellite transmits a different PN code (gold code) so that signals can be transmitted from several satellites simultaneously and received by a receiver simultaneously with little interference from each other. In addition, the data superimposed on each signal is 50 baud Binary Phase Shift Keying (BPSK) data, the bit boundaries of which are aligned with the beginning of the PN frame; there are 20 PN frames within a 1 data bit period (20 milliseconds).

The primary goal of a GPS receiver is to determine the time of arrival of the PN code. This is done by comparing the locally generated PN reference signal (per received signal) to the received signal and "sliding" the local reference until aligned in time with the received signal. The two signals are compared to each other by a multiplication and integration process called a correlation process. The output is maximum when the two signals are aligned in time. A typical serial correlator used in a standard GPS receiver compares the local and received signals for a time offset at a given time. If such comparisons are made every half chip time, then 2046 comparisons (or tests) need to be done during a PN signal epoch. Such a search must be made for several satellites that are in view. In addition, errors in the frequency of the received signal often require additional searching for various hypotheses of the signal frequency. The time required to perform this search can be long, especially when the signal-to-noise ratio of the input signal is low. Conventional GPS receivers employ a plurality of such correlators and these correlators operate in parallel to speed up the acquisition process. However, the search and acquisition process is time consuming, especially when the signal-to-noise ratio of the received signal is low.

It is therefore desirable to provide a hardware architecture that improves the acquisition speed and sensitivity of current conventional GPS receivers. Such a configuration enables the receiver to operate at times when the signal-to-noise ratio of the input signal is low. In addition, it is also desirable to integrate a method of tracking these signals after the acquisition process, using hardware conformality (uniformity) in the acquisition and tracking of the received GPS signals.

Disclosure of Invention

A method and apparatus for capturing and tracking GPS signals with fast acquisition speed and high sensitivity is disclosed. In the method of the present invention, a first pseudorandom noise matched filter operation is performed for the current sampled global positioning system to provide a current matched filter result. The current matched filter result is then accumulated with a previously matched filter result obtained from a previously sampled global positioning system signal to produce an accumulated matched filter result.

In one embodiment of the invention, the matched filter and detection circuit are combined with a front detection loop integrator and a back detection loop integrator. The loop integrator enables acquisition and tracking of a plurality of data frames containing a received global positioning system signal. This results in a combination of fast capture performance and high sensitivity. The invention discloses an efficient device for realizing a matched filter.

The invention provides a method for capturing and tracking global positioning system signals, which comprises the following steps: performing a first pseudorandom noise matched filter operation on a current sample of the global positioning system signal to provide a current matched filter result; and combining a previously matched filter result from a previous sampling of the global positioning system with the currently matched filter result to produce a combined matched filter result.

The present invention provides a circuit for acquiring and tracking a global positioning system signal in a global positioning system receiver, the acquisition circuit comprising: an input signal port for receiving a global positioning system signal comprised of in-phase and quadrature components; a matched filter coupled with the input signal port to produce filtered signal peaks; a detector circuit coupled to the matched filter for detecting signal peaks contained in an output signal of the matched filter; and a first loop integrator coupled to an output of the detection circuit.

The present invention also provides a system for receiving gps signals, comprising: means for receiving a global positioning system signal comprised of in-phase and quadrature components; means for performing matched filter operations on said received gps signals; means for detecting said received GPS signal to produce a detected signal; and means for performing a first loop integration operation on the detection signal.

The present invention also provides a matched filter circuit comprising: an input of said matched filter circuit capable of receiving a sample of a GPS signal; a multiplexer having a first input coupled to the matched filter input, and the multiplexer further having an output; a shift register having an input coupled to the multiplexer output; and a multiplier coupled to an output of the shift register, and a second input of the multiplexer is coupled to an output of the shift register.

The present invention also provides a matched filter circuit comprising: an input terminal for receiving a GPS signal sample; a data shift register having a plurality of tapped delay lines, the data shift register coupled to the input; and a plurality of matched filters coupled to the plurality of tap delay outputs of the data shift register, wherein each matched filter of the plurality of matched filters performs a matched filtering operation on the GPS signal samples.

The present invention also provides a method of acquiring and global positioning system signals, comprising the steps of: receiving a sample of a global positioning system signal; sending samples of the global positioning system signal to a plurality of matched filters through a plurality of tap delay outputs of a shift register; in each of the plurality of matched filters, a first series of weighting coefficients corresponding to a pseudo-random sequence and a second series of weighting coefficients corresponding to a carrier frequency sequence are provided as matched filter weights.

The nature of the present invention will become apparent from the detailed description and the accompanying drawings.

Drawings

The present invention is now described, by way of example and not by way of limitation, with reference to the accompanying figures, in which like reference numerals refer to similar elements.

Fig. 1 is a block diagram of a prior art global positioning system correlator circuit.

Fig. 2 is a block diagram of a global positioning system acquisition circuit according to an embodiment of the present invention.

Fig. 3 illustrates waveforms of signals at various processing stages of the capture circuit of fig. 2.

Fig. 4 is a block diagram of a global positioning system acquisition circuit that also performs tracking functions, in accordance with another embodiment of the present invention.

Fig. 5 depicts signal waveforms at various processing stages of the capture circuit of fig. 4.

Fig. 6A is a block diagram of a matched filter used by the acquisition circuit of fig. 4 according to one embodiment of the invention.

Fig. 6B is a block diagram of a matched filter used by the acquisition circuit of fig. 4 to produce a subset of possible outputs per PN frame in accordance with another embodiment of the present invention.

Fig. 7 is another illustration of the most complex portion of the matched filter of fig. 6A in accordance with an embodiment of the present invention.

Fig. 8 is a more detailed diagram of some of the components of the matched filter of fig. 7 in accordance with yet another embodiment of the present invention.

Fig. 9 is a block diagram of a global positioning system implementing acquisition and tracking operations according to one embodiment of the present invention.

Fig. 10 is a block diagram of a remote global positioning system implementing an acquisition circuit in accordance with another embodiment of the present invention.

FIG. 11 is a block diagram of a global positioning system acquisition circuit with a reduced register count feature in accordance with one embodiment of the present invention.

Fig. 12 is a block diagram of a matched filter used by the acquisition circuit of fig. 11 in accordance with one embodiment of the present invention.

Detailed Description

Methods and apparatus for receiving global positioning system signals by a fast acquisition high sensitivity receiver are described below. In the following description, for purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of the present invention. It will be apparent, however, to one skilled in the art that the present invention may be practiced without these specific details. In other instances, well-known structures and devices are shown in block diagram form in order to facilitate a description.

A Global Positioning System (GPS) receiver receives GPS signals transmitted from orbiting GPS satellites and determines the time of arrival of the appropriate code by comparing the time shift between the received signal and an internally generated signal. The signal comparison is performed in a correlation process in which multiplication and integration of the received signal and the generated signal are performed. A typical prior art series correlator used in a common GPS receiver is shown in fig. 1. Correlator 100 receives an incoming GPS signal 102 and combines the received signal 102 with an internally generated PN code generated by PN generator 110 in multiplier 104. The accumulated set of combined signals is then sampled for an amplitude squaring (or other detection) operation 106. The microcontroller 108 controls the arrangement of PN chips generated by the PN generator 110. According to the system of the correlator 100, the received signal 102 is compared with the PN chip-long sequence one time shift, and thus, a long time is required to search for all offsets corresponding to one PN frame.

Capture circuit

An improved acquisition circuit for use in a GPS receiver according to an embodiment of the invention employs one or more matched filters having pre-processing and post-processing functions to achieve fast acquisition and high sensitivity of GPS signals. It is particularly noted that the post-matched filter loop integrator (also referred to as a "multi-passband filter") provides the integration necessary to achieve very high sensitivity, enabling the receiver to operate in a lower signal-to-noise environment. Fig. 2 illustrates a GPS input signal acquisition circuit 200 that includes separate acquisition circuits for multiple input channels. There is depicted a block diagram of acquisition circuitry for a single channel 201 of GPS acquisition circuitry in accordance with an aspect of the subject invention.

The input baseband signal 202 is fed in parallel into several matched filters 204 in the acquisition circuit 200. The input baseband signal 202 is composed of separate in-phase (I) and quadrature-phase (Q) components. The taps of each filter in each channel are arranged in sampled versions of the same or different PN waveforms, and the waveforms are flipped in time. Typically, the input sample rate is a multiple of the chip (chip) rate, and therefore there is typically a 1023M-tap matched filter, where M is a small integer, typically 2. If the input signal contains a transmit waveform that is matched to a given matched filter, its output will contain a narrow spike of approximately one chip duration in width. A narrow spike will occur for each frame and provide time of arrival information, modulo one PN frame period. Since the signal is represented in quadrature, the peak is effectively a complex number. The polarity of which is phase inverted at the data baud boundary according to the transmitted data stream. In addition, since the received signal carrier frequency and the locally generated frequency have a small frequency difference therebetween, the phase angle slowly advances or retards in time.

When the signal is weak, each spike may be obscured by noise, for example due to blockage by an object such as a tree or building, and therefore cannot be used directly to make a time of arrival measurement. To accumulate the energy of the spike, the output of the matched filter can be detected by a square law or other detection operation 206 to remove the changed phase angle just mentioned. The energy of one PN frame is then added to the energy of the previous frame by the delay line integrator 210. The spike of the previous frame will be delayed exactly one PN frame for the delay of one PN frame, so the energy exits the delay line 211 just as the spike of the next frame is going to enter the delay line 211. The two spikes are then added by an adder 208 to provide a stronger spike. The random parts of the noise are added incoherently (which will increase the dc level) and thus these random parts will increase with the square root of the number of frames added. The dc level associated with the noise can be determined by an averaging process at the integrator output and subtracted from the final output. This facilitates the determination of a suitable detection threshold.

As shown in fig. 2, the feedback from the loop integrator 210 is not full feedback (unity), but is 1-epsilon, where epsilon is a number less than 1. Thus, loop integrator 210 is effectively used as a "leaky" summing circuit, which in the operational sense is actually an average over several frames of about 1/ε. In another embodiment of the invention, a loop integrator 210 with full feedback may be employed, followed by a delay and subtraction circuit. At this point, the delay will be set equal to MT_f. This constitutes a "boxcar" filter which directly adds the last M frames. The memory storing the M data frames is very strict.

In another embodiment of the acquisition circuit 200, the loop integrator 210 employs full feedback and, after every M frames, screens (gating out) the feedback through the gate circuit 212, repeating the addition of the M data frames. In this way, the output of the loop integrator will have a valid output (i.e., the one representing the M frames of data) only at every mth frame. In many cases, this update frequency is acceptable for acquisition.

The delay line circuit 211 in the loop integrator 210 of the acquisition circuit 200 may be implemented using a shift register to delay the propagation of signals through the circuit. Alternatively, random access memory (single or dual port) devices may be used in place of the shift registers. The memory will be loaded and accessed in such a way that the shift register operates in an analog loop integration function.

Fig. 3 depicts signal waveforms at various processing points within a single one of the capture circuits 201 in the capture circuit 200. For purposes of illustration, fig. 3 depicts a simplified PN signal of only 7 chips per frame, rather than the 1023 case in a normal GPS signal. The range of the waveforms in fig. 3 is extended to the case of three data bits 304, 306, 308 with four PN frames 302 per bit. For simplicity, no noise is given and only the case of the signal of the in-phase channel is depicted. It is also assumed that the loop filter 210 employs full feedback.

The baseband PN signal 310 waveform depicts a representative I/Q input signal 202 (only I or Q is shown) that is input into the acquisition circuit 200. The output after the matched filter waveform 312 depicts the signal waveform after the I/Q input signal has been processed by the matched filter 204. From the matched filter 204, the signal propagates to the amplitude squaring circuit 206, which produces an output after a square waveform 314. From the magnitude squaring circuit 206, the signal propagates to the loop integrator 210, which generates an output after the loop integrates the waveform 316. The output after loop integration waveform 316 depicts the increase in signal peak waveform over time due to the operation of the square-law detector and iterative propagation through loop integrator 210. Fig. 3 also depicts the detection threshold level superimposed on the output of the loop integration waveform 316. The detection threshold level represents the threshold signal level set by threshold comparator 214 in acquisition circuit 200.

Although the baseline of the signal also rises with time, its dc component can be easily removed by averaging the outputs. The acquisition circuit 400 shown in fig. 4 is a single channel acquisition similar to that shown in fig. 2, but with additional processing elements. These additional components include a digital frequency conversion circuit 404 for compensating for doppler and LO frequency offsets, a digital resampler 406 for compensating for doppler and LO sampling rate offsets, and a pre-detection loop filter 410.

Referring now to fig. 4, a signal tracking and digital demodulation process in accordance with an aspect of the present invention is described. The digital frequency conversion circuit 404 simply multiplies the I/Q input signal 402 by the power exp (-j2 π nf_dT_s) Here, f_dIs a mixed Doppler and LO frequency offset, T_sIs the sampling period and n is the run time index. This compensation is needed so that the residual signal frequency error is much smaller than the PN frame rate (1 kHz). Otherwise, the effect of the frequency offset will reduce the amplitude of the output signal of matched filter 408 by an amount equal to | sin (π f)_dT_f)/πf_dT_sThe amount of | is given. For example, if f_d＝1/T_sThen the amplitude of the matched filter output signal will be zero.

The doppler sample rate correction signal 430 is input to the digital resampler 406, which corrects for small errors resulting from the "stretching" or "shrinking" in time of the received I/Q input signal 402 due to doppler shift. For example, a Doppler error of 2 μ sec/sec (just within the Doppler range observed by a GPS satellite) represents a time shift of two chips over a time range of 1 second. Such a time shift will limit the number of times loop integration can be performed, since the detected spikes in later time periods will not align with those in earlier time periods, and thus the processing gain will disappear (or actually decrease) with respect to the increased integration time. In addition, the correlation peak at the output of the loop integrator will widen, thereby increasing the error (or "false range") of the measured arrival time.

The digital resampler circuit 406 uses the data provided to the acquisition circuit 400 to compute data samples between the original sample points at sample instances provided by the particular sample rate correlation. For example, if the sampling rate provided to circuit 400 is 2 samples per chip and the desired sampling rate is 2-d samples per chip, then the new sampling interval is T_cV (2-d), and therefore just after the corresponding multiple (times) of the original dataA new sample is taken at some location. Therefore, the slip amount (slip) is equal to T_cI.e./2, i.e. one complete sampling period. This is handled urgently by dropping a sample clock from the circuit 400. Digital resampling is performed by a process called digital fractional interpolation. In its simplest form, a suitable interpolation algorithm, such as a polynomial or spline fit, is performed on several samples around the new sample time location of interest to calculate the signal value at the appropriate time.

In another embodiment of circuit 400, digital resampler 406 is omitted and replaced with a process that continually reloads the matched filter with new coefficients that include an added small delay timeout (over time). The digital resampler 406 can be replaced by updating the filter weights of the matched filter by delaying these filter weights. This approach requires filter coefficients larger than one bit, each for accurate implementation, thus increasing circuit complexity. However, shifting the coefficients of the matched filter one position to the left or right is another way to add or drop one sample.

The acquisition circuit 400 includes two loop integrator circuits. The front detection loop integrator circuit 410 is used before the detection operation 416 and the rear detection loop integrator circuit 420 is used after the detection operation 416. Dual loop integrator circuit 420 takes advantage of the fact that the data period is equal to 20 PN frames. Therefore, the PN signal is repeated many times when the data indicates that the polarity of the signal is reversed. So if the doppler correction is good, one can add the PN frames together coherently (coherently) before or after the matched filter operation. It is clear that only up to 20 such frames can be added together before the data polarity inversion causes performance degradation. Such coherent addition results in increased sensitivity, which is not present with non-coherent (post-detection) integration, because coherent integration establishes a signal-to-noise ratio at the spike before square-law operation 416 is performed.

Fig. 5 depicts signal waveforms at various processing points within the circuit 400. For purposes of illustration, fig. 4 depicts a simplified PN signal having only 7 chips per PN frame, rather than 1023 as in a typical GPS signal. The waveform range in fig. 4 extends to three data bits 504, 506, 508, each bit having four PN frames. For simplicity, noise is not depicted in the figure, but only the signal of the in-phase channel. It is also assumed that both the front detection loop filter 410 and the back detection loop filter 420 employ full feedback. It is assumed that the front detection loop filter 410 accumulates the last four frames in a running sense.

The baseband PN signal 510 waveform depicts the representative I/Q input signal 402 input into the acquisition circuit 400. The output after matched filter waveform 512 depicts the signal waveform after the I/Q input signal 402 has been processed by matched filter 408. From matched filter 408, the signal propagates through pre-detection loop filter 410, which produces an output after pre-detection loop filter waveform 514. The signal is then input to the squaring circuit 416, which produces an output after the squaring operation waveform 516. From the squaring circuit 416, the signal propagates to the post-detection loop integrator 420, which produces an output after the loop integration waveform 518. The output after the loop integration waveform 518 plots the increase in signal peak amplitude over time due to the operation of the square-law detector and iterative propagation through the loop integrator 420. Fig. 5 also depicts the detection threshold levels superimposed on the output after the loop integration waveform 518. The detection threshold level represents the threshold signal level set by the threshold comparator 426 in the capture circuit 400. It should be noted that the output peaks after the loop integration waveform 518 do not increase linearly, as shown in fig. 3 for a single loop integration circuit 200. However, the magnitude of each fourth peak corresponds to the pre-detection filter memory, but increases approximately linearly. As shown in FIG. 3, it should also be noted that the amplitude ratios of the waveforms shown in FIG. 5 are not necessarily proportional with respect to each other.

Analysis of the input and output signal-to-noise ratios for various parameters associated with the operation of the acquisition circuit 400 gives the following equation:

(S/N)_out＝L(S/N)_i ²×F×npostd×npred/(1(F npred)+2(S/N)_i)

in the above equation, the variables have the following values:

L＝L_dopp×L_data

L_dopp＝sinc²(freq offset×npred×0.001)

L_data＝(1-0.315×npred/20)²

in the above equation, the variables have the following meanings:

npred: number of added previous detection frames

npostd: the added independent post-detection frame number is the total frame number/npred

F: the independent number of samples per PN frame is taken as 1023

L_dopp: loss due to Doppler error

L_data: loss due to data transition of degraded coherent integration

freq offset: carrier frequency error between received signal and receiver estimate (including local oscillator and Doppler error)

In the above equation, (S/N)_outIs the peak output signal power divided by the mean square background noise power; and (S/N)_outIs the average signal power divided by the average noise power measured in a bandwidth (about 1MHz) equal to the chip rate. Note that (npred x npostd) equals the total number of PN frames grouped together. The above equation can then be used to select the parameters npostd and npred (M and L in fig. 4) in order to obtain the maximum output SNR (which should typically exceed about 15dB, or a factor of about 30, for good detection probability and low false detection rate). At a certain pointIn some cases, when the Doppler error may be large, one may slowly shift or adjust the Doppler control line output from the microcontroller 428 until detection is possible.

The capture circuit 400 shown in fig. 4 also contains a register set 418. Register set 418 is a circuit element that can receive data from either post detection loop integrator 420 or pre detection loop integrator 410. The post detection data from post detection loop integrator 420 corresponds to the capture mode. During signal tracking and demodulation, the GPS receiver must track the carrier frequency and phase, as well as the PN code phase, and demodulate the 50 baud data message. This can be done using I and Q samples from the matched filter at or near the signal peak. At this point, the pre-detection loop integrator 410 effectively coherently adds about 10 frames of data (i.e., one-half bit period) and sends the result to the register set at and near the peak. That is, a typical update rate is 100 updates per second. The microprocessor will read these results and form a carrier, code and bit tracking loop in software, sending control signals (e.g., from microcontroller 428) to maintain proper tracking. The design of such tracking loops is well known to those of ordinary skill in the art. Note that only one loop integrator may be used instead of two integrators as in fig. 4. A single loop integrator will be used for acquisition or tracking. However, in this case, pre-detection integration is not performed at the time of acquisition, and post-detection integration is not performed at the time of tracking. However, the microprocessor may perform post detection integration while tracking.

Matched filter

Fig. 6A shows a matched filter 408 in the acquisition circuit 400 according to one embodiment of the invention. Matched filter 408 employs a weighted tapped delay line structure. The filter 408 is divided into two separate parts. One section contains a chip-matched filter 604 for matching to the time waveform of a single chip. The chip-matched filter 604 is followed by a tap filter 608 that is matched to the actual waveform of the pseudo-random signal waveform. By dividing the filter in this way, the tapped filter contains taps that take only values of ± 1, and every other tap can be set to zero. In the exemplary matched filter shown in fig. 6A, it is assumed that the sampling rate of the tap filter 608 is two samples per chip, as produced by the downsampler 606.

The tap filter 608 further includes an adder tree 610 and a multiplier 612. In the system shown in FIG. 6A, the adder tree requires approximately 512 adders to complete the addition. In this example, the arithmetic capability of the adder is Q to Q +10 bits, where Q is the quantized value of the input (typically 2 to 4 bits I and Q). Adding successive outputs of the multiplier 612 using a bank of high-speed accumulators can significantly reduce complexity. For example, one accumulator may add the outputs of multipliers w1 to w16, while a second may add the outputs of multipliers w17 to 32, and so on. This is illustrated in fig. 7 and 8. The most straightforward approach to using an accumulator is to use a 16: 1 multiplier, the output of which is connected to each of the registers G1 to G16 (as shown in fig. 8), the outputs of which are selected in turn and added. In some cases, this may result in a large gate count.

Fig. 7 depicts a tap filter 608 that employs a series of 16 tap filter/accumulators 710 to provide a weighted sum of successive 16 tap groups. Similar structures 706 and 712 perform the addition of the outputs of these elements 710.

Fig. 8 depicts further details of filter/accumulator 710. The circuit shown in fig. 8 employs a series of sub-blocks, each of which contains two shift registers 802, 804 arranged in two loops for providing data to weight multipliers and accumulators. Sub-block 802 contains multiplexer 806, while sub-block 804 contains multiplexer 808. This architecture eliminates the need for a 16: 1 multiplexer to select the data, which is a gate enhancement system. The shift register is shifted to the right once and cyclically 15 times during a 2.046MHz clock cycle, thereby taking the 16 register filtering operation required to complete the data at 16 times the rate of the master clock. The shift register containing sub-block 802 and sub-block 804 corresponds to even and odd data samples. The first half of sub-block 802 is processed in one 2.046MHz period, while the second half of sub-block 804 is processed in the next 2.046MHz period. This two-block architecture takes advantage of the fact that only half of the registers in tap registers 608 are connected to adder tree 610 at any one time.

The operation of the two shift registers within circuit 800 is as follows. At even number of 2MHz f₀On the clock boundary, multiplexer 806 is in the 'A' position, and multiplexer 810 is in the 'A' position; the register G16 is multiplied by the tap weights 814 and stored in the accumulator 812, and all 'G' registers are shifted to the right. Data from register G16 is fed to register G1 for the next block. Subsequently, the multiplexer 806 is placed in the 'B' position, and the data in the tap groups 802 of registers G2 through G16 is cyclically shifted, multiplied by the tap weights 802, and accumulated in the accumulator 812. At odd number 2MHz f₀On the clock boundary, the multiplexer 808 is in the 'A' position and the multiplexer 810 is in the 'B' position, the register H16 is multiplied by the tap weights 814 and stored in the accumulator 812, and all 'H' registers are shifted to the right. Data from register H16 is fed to register H1 of the next block (not shown). The multiplexer 808 is then placed in the 'B' position, and the data in the bottom set of registers H2-H16 is cyclically shifted, multiplied by the tap weights 814 and accumulated in the accumulator 812. Subsequently, this process is repeated.

The weighted values of the taps are shifted in a pass-through shift register 814. As the weighted values shift in, they are combined with the output of multiplexer 810 in multiplier 816 before being input to accumulator 812. The weighting value is +/-1 and thus, multiplier 816 functions as a selectable inverter. The shift register is 32 stages long. Each f₀The clock period is shifted 16 times.

Referring to fig. 7, assume that the input rate of the filter is about 2.046 MHz. Due to this input rate, the accumulation rate is about 32.736MHz, which is well within the capabilities of low cost integrated circuit technology. Therefore, the tap filter 608 is the top row block 702 in fig. 7 (labeled "16 tap filter/accumulator") whose main processing is performed by 64 such accumulators, each of q +4 bits. For q-4 this corresponds to about 512 full adders, and in complexity to 16 x 16 multipliers (excluding the registers that are part of the accumulator). Thus, an I and a Q matched filter have a gate complexity of about four 16 × 16 multipliers plus a few memory bits of about 17500 size (for 4-bit I and Q quantization). This number is then multiplied by the number of matched filter channels used. Of course, if the accumulator is running at a higher rate, the number of gates required can be further reduced.

The above example the outputs of the 64 accumulators 702 shown in FIG. 7 are dumped at a rate of 2.046 MHz. These signals may be placed in a set of 64 registers, organized into four sets of 16 registers. These operations are performed by block 712. Since the dump rate is 32.736MHz, the outputs of each set of 16 registers can be accumulated (tap-add set to 1) by a structure similar to that of fig. 8. Four such accumulators are required. Followed by a four tap accumulator 706 which is similar to the 16 tap accumulator but uses one quarter of the clock rate of these devices and has a shift register of length 4 instead of 16. Therefore, it should be noted that the hardware required to complete the addition operation is only 10% larger than performing the first set of 64 filter/accumulator operations. Note that only one chip-level matched filter 604 need be employed to service all such PN-level matched filters.

In another embodiment of the present invention, the matched filter may be a circuit that performs a Fast Fourier Transform (FFT) algorithm. At this point, the tapped delay line filter 408 of the acquisition circuit 400 will perform a fast convolved FFT operation. Referring to fig. 6A, it will be appreciated that the FFT circuit replaces the tapped delay line filter 608 and that the FFT operation is performed on the signal data 602 and the weight vector 612. The two are then multiplied and the results inverted to compute a circular convolution (convolution), as is well known to those skilled in the art. This series of operations may be performed for each PN frame and the resulting data may be accumulated and detected by elements 410, 416, and 420.

In addition to circular convolution, another method may be employed to perform an "overlap-add" or "overlap-store" operation. These operations are well known to those skilled in the art and avoid the cyclic convolution which makes more complex processing. However, this alternative approach may result in improved performance. There are other fast convolution methods in the art. For example, the filtering method of the present invention can be replaced by the method discussed in "fast fourier transform and convolution algorithm" (new york, Springer-Verlag, 1982) by h.j.

In yet another embodiment of the present invention, the matched filter 408 of the acquisition circuit 400 may be interchanged with the loop 410 of the coherent integration operation. Matched filter operations and coherent integration operations are linear time invariant filter functions and it is well known that such interchanging produces the same combined function output, provided with sufficiently accurate digital accuracy. Interchanging these operations may result in a reduction in hardware (e.g., FFT matched filter with tapped delay line addition network) depending on the exact method used to implement each operation.

In yet another embodiment, the squaring operations 206 and 214 may be replaced by a square root operation or another non-linear detection operation that removes the signal phase from the accumulated signal sent to the circuit.

Reduced complexity matched filter

In the following discussion, the matched filter 408 continuously computes each sample corresponding to all PN chips (typically 2046 samples, 1023 chips at a rate of 2 samples per chip) of the GPS frame. However, the complexity of the matched filter can be reduced and still retain the advantages of the present invention.

One way to reduce the complexity of the matched filter portion is to use a matched filter that provides an output continuously, but with a length (i.e., impulse response duration) that is less than the entire PN sequence. The matched filter 408 shown in fig. 6A is simplified in structure according to one embodiment. For example, the shift register 614 may employ 127 registers instead of 2045 registers, and the weighting structure may employ 64 weights instead of all 1023 weights. This reduces the complexity of the matched filter 408 by a factor of 16. In this embodiment, the adder tree 610 may also be reduced to match the reduced size shift register and weighting structure.

A matched filter according to this method of reducing the structural complexity will reduce the sensitivity of the system because the total integration time per output data will be less than the entire PN frame. However, this ensures that one peak is generated per PN frame and has superior acquisition speed compared to other methods. It should be noted that the shift registers, the weighting structures, and the adder trees in the matched filter 408 may be reduced as appropriate, and the performance characteristics may be changed proportionally, in addition to those mentioned above.

Fig. 6B depicts a reduced complexity matched filter in accordance with one embodiment of the present invention. The matched filter system 640 produces a fraction of the possible outputs per frame, but the length of the matched filter is the same as the length of the PN frame. This corresponds, for example, to constructing a filter that produces an output for 64 consecutive ones of 2046 clock pulses per PN frame. Each output represents a potential pseudorange.

The matched filter 620 has the same sensitivity as the normal matched filter 408, and the length is equal to the length of the PN frame; however, since it produces only a portion of the total output per frame, the probability of producing a peak per frame is the ratio of the number of outputs produced divided by the length of the PN frame. Therefore, to achieve 100% capture probability, the resulting output will have to be "stepped" over the time shift range corresponding to one PN frame. For the above example, there are 64 outputs in a total of 2046 clocks per frame, so there are 2046/64 or 32 steps to cover the entire PN range. The matched filter according to the present embodiment is superior in sensitivity to the previously disclosed reduced complexity matched filter approach.

The matched filter system 640 has a matched filter 620 that produces one packet of possible output per PN frame. In particular, the depicted structure produces 32 outputs per 1023-length PN frame. For clarity of the following discussion, it is presupposed that the sampling rate is one sample per chip, i.e., 1.023 mega samples/second (for C/A codes employing standard positioning service GPS). For clarity, fig. 6B depicts a single matched filter 620, such that the filter 620 can process 32 data samples at a time. This filter may be supplemented with a loop integrator 630 to form a filter having a greater length, in particular a length 1023 filter.

The discussion below proceeds with reference to FIG. 6B, where particular, but typical, values are assigned to the shift register 622 elements and weighting structures 624 at particular times. At time 0(t ═ 0), the data samples in registers R1-R32 are x (32), x (31), …, x (1), respectively, where x (1) represents the first input data sample at that time, x (2) is the second input data sample, and so on. When t is 0, the filter structure 620 produces a result x (1) w (1023) + x (2) w (1022) + … + x (31) w (992). Similarly, at time t-1 to t-31, the filter weights 624 remain unchanged, but the data is shifted by one position and a similar calculation occurs. Then, during the first 32 clock cycles (each row representing a successive output data sample), the following data is output from the matched filter and stored in the loop integrator 630:

block 1 matched filter computation

x(1)w(1023)+x(2)w(1022)+…+x(32)w(992)

x(2)w(1023)+x(3)w(1022)+…+x(33)w(992)

·

·

·

x(32)w(1023)+x(33)w(1022)+…+x(63)w(992)

At this point, after 32 samples have been processed, the weighting value is replaced by an index 32 with an index less than the starting value (i.e., W (991) …, W (960)), and the matched filter produces the result of the next 32 samples (time t-32 to t-63):

block 2 matched filter computation

x(33)w(991)+x(34)w(990)+…+x(64)w(960)

x(34)w(991)+x(35)w(1022)+…+x(65)w(960)

·

·

·

x(64)w(991)+x(65)w(990)+…+x(95)w(960)

The effect of the loop integrator 630, however, is to sum the corresponding rows of the two arrays described above, thereby producing, in its memory register, the full result for each of the times t-32 to t-63:

block 2 loop integrator output

x(1)w(1023)+x(2)w(1022)+…+x(64)w(960)

x(2)w(1023)+x(3)w(1022)+…+x(65)w(960)

·

·

·

x(32)w(1023)+x(33)w(1022)+…+x(95)w(960)

Each row of the latter array is identical to the array generated for the length 64 matched filter corresponding to output time t 0, 1, …, 31. The loop filter therefore performs the required function so that the matched filter can function as a longer length matched filter. Similarly, after each additional 32 samples, a new set of weights is introduced, having an exponent value 32 smaller than the previous set. The same analysis applies here, where the output of the loop integrator after each additional 32 samples represents the filter output generated for the longer matched filter at time t-0 to t-31. After 32 such cycles, the data set produced by matched filter 620 is:

block 32 matched filter calculation

x(993)w(31)+x(994)w(30)+…+x(1024)w(0)

x(994)w(31)+x(995)w(30)+…+x(1025)w(0)

·

·

·

x(1024)w(31)+x(1025)w(30)+…+x(1055)w(0)

The operation is ended by adding the data to the previous data. Each time the loop integrator 630 is updated in this final block, its contents may be sent to another buffer. The next time the loop integrator 630 is updated, its initial state may be set to zero unless one wishes to integrate over several frames.

One drawback of the above example method is that there are no weights of w (0) because there are only 1023 weights per PN frame (if the sampling rate is matched to the PN length). However, if w (0) is set to be w (1023), a filter of a suitable length of 1024 can be efficiently generated. This method takes advantage of the periodicity of the PN signal.

A second disadvantage of the above example method is that the last row of block 32 starts with x (1024). However, it is better if this word is the first word for block 1 of the next PN frame, so that for each frame, the same set of matched filter outputs are calculated modulo the frame length 1023. The problem here is that 32 is not 1023. This peak alignment problem can be solved by preventing the last row of the matched filter computation block 32 from being added to the loop integrator 630. This will cause the 32 th quantity in the loop to be erroneous, so only 31 consecutive matched filter outputs are valid. In the matched filter 620, the weights w (1023), w (1022) + … + w (992) are simply loaded into the weight structure 624 at the 31 st cycle after the start of block 32 instead of the 32 nd cycle. In addition, the loop integration counter is reset at this time. Another correction is to use a matched filter of length 31 or 33, either of which is divisible by 1023.

The reduced matched filter structure 640 shown in fig. 6B may have several variations. First, matched filter 620 may be implemented using the circuit shown in FIG. 8, which employs only one multiplier/accumulator. In addition, the filter weights may be provided by a shift register. In this case, the operation sequence of the operations required by the above method is consistent with the simple weight provided in the sequences w (1023), w (1022), …, w (1).

Two or more of the filters/accumulators shown in fig. 7 may also be combined with the accumulators shown in fig. 6B to form longer (e.g., 64 or 128) length matched filters. Virtually any matched filter structure may be used in place of the direct tapped delay line structure 622 of the matched filter 620. Of course, several means may be employed to compute a set of outputs that are not adjacent to the matched filter. For example, shift register 620 of matched filter 620 may shift four times per matched filter calculation to provide each fourth matched filter output.

GPS receiver

Fig. 9 illustrates the architecture of the acquisition circuit 400 in a conventional GPS receiver 900 according to one embodiment of the invention. GPS signals are received by GPS antenna 902 and input to GPS receiver 900 through input circuit 904. The PN code in the received GPS signal is acquired and tracked in circuit 400a with external processor 910 according to the operations described above with reference to fig. 4-8. The output of the acquisition circuit 400a contains pseudorange data 908 corresponding to the signal received from each GPS satellite. Each satellite also transmits ephemeris data which is received by input circuit 904 and demodulated by circuit 400 b. Processor 910 processes the ephemeris and pseudorange data to determine the position of the receiver. The output of processor 910 drives an input/output device such as display device 912 which displays the position of the element in the form of an image or text. In this configuration, the circuit shown in FIG. 4 performs the acquisition and tracking functions with the processor 910.

Fig. 10 illustrates the structure of an acquisition circuit in a GPS receiver 1000 according to another embodiment of the present invention. The GPS receiver 1000 is a combined GPS and communication transceiver. Receiver 1000 comprises a GPS receiver stage including an acquisition circuit 400 and a communication transceiver portion 1020. The GPS signal is received by a GPS antenna 1002 and input to an acquisition circuit 400 that acquires a PN code for each reception satellite. The pseudorange data generated by acquisition circuit 400 is processed by processor 1012 and transmitted by transceiver 1020. The transceiver 1020 includes a transmit/receive switch (or duplexer) 1008 that routes communication signals (typically radio frequency signals) to and from the antenna 1004 and the receiver 1000. The received communication signals are input to the communication receiver 1010 and passed to the processor 1012 for processing. Communication signals to be transmitted from processor 1012 propagate to a modulator 1014 and a frequency converter 1016. Power amplifier 1018 increases the gain of the signal to an appropriate level for transmission to base station 1006. In the communication system of the combined GPS/receiver 100, the pseudorange data generated by the acquisition circuit 400 is transmitted over a communication link to the base station 1006. Base station 1006 then determines the position of receiver 1000 based on the pseudorange data from the remote receiver and ephemeris data received from its own GPS receiver or other such data source. The location data may then be transmitted back to the GPS receiver 100 or other remote location. The communication link between receiver 100 and base station 1006 may be implemented in several different embodiments, including a direct link or a cellular telephone link.

Method for reducing register count

The previously described examples of GPS acquisition circuits are implemented using a plurality of matched filters connected in parallel, each requiring a separate shift register to store input data (e.g., the acquisition circuit 200 shown in fig. 2). For these circuits, if there are a large number of parallel channels, e.g., eight, the number of registers is large and can account for a large fraction of the total system gate count. In addition, there is considerable power leakage associated with these large numbers of registers. In one embodiment of the present invention, the GPS acquisition circuit that holds the incoming GPS signal data employs a shift register at the input stage.

The reason multiple matched filter channels traditionally require multiple shift registers is that the requirements for doppler carrier correction and doppler time correction (i.e., sampling clock variation) are different from channel to channel. So, if the doppler carrier correction is made for the incoming data, N new data streams corresponding to N different dopplers for N channels are generated. Similarly, to track the varying chip rate of the signal, the clock fed to the register holding the data is varied as required by the doppler associated with a particular channel. This again conventionally means that separate shift registers are employed to hold the data for each channel.

One embodiment of the present invention compensates for the changing carrier by changing the matched filter weights regularly (e.g., once per PN frame, or once per millisecond), and performs carrier correction after the matched filter. Therefore, this embodiment does not need to employ a separate shift register. The method of changing the effective sampling time regularly changes the weight of the matched filter again, and resamples the data signal again after the matched filter operation.

FIG. 11 is a block diagram of reduced register GPS acquisition circuitry according to one embodiment of the present invention. In the circuit 1100, input data is fed to a single data shift register 1102. The length of the input shift register is typically 1023 or 2046, depending on the number of samples per chip. The output of the shift register 1102 is fed in parallel to N matched filter channels 1104, 1106, up to 1108. The circuit containing the first matched filter channel 1104 is shown in detail; it should be understood, however, that the N matched filter channels contain the same circuitry. Each channel includes memory for carrier coefficient values 1112 and memory for PN coefficient values 1114. The carrier coefficients are input to a carrier weighting circuit 1118. Likewise, the PN coefficient is also input to the PN weighting circuit 1120. The weighted carriers and PN coefficients are then combined in summing network 1122.

Thus, data from shift register 1102 propagates through N matched filter networks, each combining a weight of PN coefficients and frequency coefficients. The purpose of this arrangement is that if a single PN frame of the input signal is of the form s (t) ═ P (t-d) exp (j2 pi ft), and P (t) is a PN sequence of length 1023 chips, f is the remaining doppler frequency, and d is the relative delay, then the filter matched to the signal is the same impulse response as s (t), except that it varies with time. The weighting function can be divided into two parts, one corresponding to the PN sequence P (t-d) and the other corresponding to the carrier weighting function exp (j2 π ft), where t varies from 0 to the filter impulse response length (typically one millisecond). Since f and d are different from channel to channel and also change slowly over time, these weighting functions must be updated regularly. In most cases, updating every millisecond (PN frame) is not adequate because there is little carrier frequency variation (typically less than 1Hz) and little PN phase variation (less than 0.003 chips) in a one millisecond period.

The operation of the carrier weighting circuit 1118 and PN weighting circuit 1120 is depicted in greater detail in fig. 12. The combined "w" and "c" filter coefficients used in fig. 11 and 12 correspond to the filter transfer function not at baseband but at frequency f. Therefore, the data emanating from the matched filter is also not in baseband. Therefore, if successive PN frames from a matched filter (such as the delay line integrator shown in fig. 4) are to be coherently summed, the carrier frequency of the signal exiting the matched filter must be compensated so that the phase is aligned from one frame to the next. This compensation is performed by multiplier 1124 at the output of channel 1 shown in fig. 11. In the most general form, the local oscillator 1116 feeding the multiplier 1124 is exp (-2 π ft), where f is the Doppler frequency to be corrected and t is the time of successive increases. This then down-converts the signal at the filter output to a 0 frequency, enabling frame-by-frame integration.

For coherent frame-by-frame addition, the carrier phase synthesizer 1116 of circuit 1100 must be operated continuously, but one phase may be used for the entire frame. Thus, the phase must be incremented for the next frame by the amount of Doppler phase accumulated for each frame, i.e., 2 π fT_fHere, T_fIs the duration of a frame (one millisecond). This approach reduces the operating speed of the carrier phase synthesizer 116. It should be noted that adjacent samples output from the matched filter after this frequency conversion will have a slightly different phase in this case, i.e. 2 π fT_cHere, T_cIs the chip duration. Typically, a small doppler error associated with the GPS satellites (typically less than 3500Hz) would make this phase difference insignificant (less than 1 degree).

The output of the carrier phase synthesizer 1116 is fed to a digital resampling circuit 1126. The circuit acts as a variable delay line that can delay the input signal within a range of 1/2 samples. This can be done in the simplest way by a linear interpolator which simply weights two adjacent samples, which is proportional to the time difference of the sampling times relative to the number of closest two samples on either side of it. Linear interpolation results in a roll-off of the signal spectrum; however, this can be compensated by equalizing a filter placed before the spectral filter, for example as a chip matched filter as shown in fig. 12. When a delay exceeding 1/2 samples is required, this is accomplished by simply cyclic shifting the PN coefficients stored in storage unit 1114 by a "forward/retard" command, and then adjusting the fine interpolation of the resampling circuitry, as shown in fig. 11. Updating the PN coefficients in this manner is a relatively infrequent operation requiring less than three times per second due to the relatively small number of doppler shifts associated with GPS satellites (typically less than 2700 nanoseconds per second). Control of all of the above operations is performed in circuit 1100 by a conventional microcontroller or microprocessor 1110.

Fig. 12 illustrates an example of how individual weighting of PN and carrier frequencies can be performed by embodiments of the present invention. Matched filter 1200 employs a weighted tapped delay line structure. The in-phase or quadrature data input is input to a chip-matched filter 1202 matched to the time waveform of each chip. The output of the chip-matched filter 1202 is then down-sampled to two samples per chip in a down-sampler 1204. The down-sampled signal is then fed to a tapped delay line filter that is matched to the actual waveform of the pseudo-random signal waveform. The "w" coefficient 1206 tap filter is a filter corresponding to the PN coefficient, and the "c" coefficient 1208 is a filter corresponding to the carrier frequency. The outputs of the weighted signals are then combined in adder tree 1210 to produce an output from matched filter 1200. The circuit shown in fig. 12 represents a modification of the direct embodiment shown in fig. 6A. However, the weighting method of circuit 1200 may be similarly applied to the various effective matched filter structures discussed herein, as shown in fig. 6B, 7, and 8.

As can be seen, the weights of fig. 12 can be combined, i.e., the w and c weights can be combined, resulting in a weight d1 ═ w1 × c1, d2 ═ w2 × c2, and so on. Such a combination may avoid two multiplication operations. However, the arrangement of circuit 1200 has several advantages over this approach. First, in many cases, the PN forms w are real numbers, i.e., they contain no quadrature components. Therefore, in fig. 12, the w coefficients only require 1023 memory words and each output in the in-phase or quadrature points is only 1023 multiplications. The frequency coefficient c is a complex number having an in-phase component and a quadrature component. So they require as many as 2046 stored words, 4092 multiplications and 2048 additions per output for either the in-phase or quadrature points. If it is considered that the number of successive values of the c coefficient is the same, for example 16, the amount of storage of the frequency coefficient can be greatly reduced. This is possible in many cases because the doppler correction is typically small, on the order of a few kHz, with an effective separation between samples weighted by successive coefficients of about 1 MHz. Therefore, successive frequency coefficients correspond to phase changes on the order of 0.003 degrees maximum, or about 1 degree phase. If the 16 frequency coefficients in a row are the same, then the maximum phase error at this time is about 8 degrees, which will cause the loss of signal energy to be less than 0.09 dB.

In most cases, the PN weights need to be updated very rarely, since the time doppler of GPS does not exceed three chips per second. However, because doppler can vary on the order of 1Hz per second, the carrier doppler weights c need to be updated often, perhaps on the order of 100 times per second. Since the weights are assigned during the update process, the update process may produce some loss of signal energy (unless a costly double-buffer approach is employed). Since there are many doppler weights less than the PN weight (assuming the 16 doppler weights in a row are the same), the duration of the interference (i.e., loading new data into the carrier coefficient memory 1112) is minimized by splitting the weighting process as shown in fig. 12.

In some GPS receivers, there is a greater frequency and sampling rate due to the poorly controlled reference local oscillator. For example, if a 10 Parts Per Million (PPM) crystal oscillator is used, then all channels will experience a frequency error of approximately 15750Hz (ignoring more small Doppler frequency errors), and similarly will experience a sampling time error of 10 milliseconds per second. Although the circuits 1100 and 1200 shown in fig. 11 and 12 may tolerate such large errors, as can be appreciated from the foregoing discussion, such large frequency errors may negatively impact the performance and/or complexity of the system. This is especially true when several successive frequency weights are required to be identical. Such large frequency errors, which are common to all channels (i.e., common mode), can be compensated for by employing a digital frequency conversion circuit before (e.g., before or after the data shift register) the matched filter shown in fig. 11. This eliminates the need for subsequent circuitry to compensate for such large errors. The sampling time error is still rather small and therefore no separate compensation is needed in a similar way.

Although the method and apparatus of the present invention are described with reference to GPS satellites, it should be understood that these principles apply equally to positioning systems employing pseudolites or a combination of satellites and pseudolites. Pseudolites are ground-based transmitters that broadcast a PN code (similar to a GPS signal) modulated on an L-band carrier signal, and are typically synchronized with GPS time. Each transmitter may be assigned a unique PN code to allow identification by a remote receiver. Pseudolites are used in situations where GPS signals from an orbiting satellite may not be available, such as tunnels, mines, buildings or other enclosed areas. The term "satellite" as used herein includes pseudolites or the equivalent of pseudolites, and the term GPS signals as used herein includes GPS-like signals from pseudolites or the equivalent of pseudolites.

In the foregoing discussion, the present invention has been described with reference to the united states Global Positioning Satellite (GPS) system. However, it should be understood that these methods are equally applicable to similar satellite positioning systems, such as the Russian Glonass system. The term "GPS" as used also includes satellite positioning systems such as the russian Glonass system. The term "GPS signals" includes signals from other satellite positioning systems.

In the foregoing, a system has been described for receiving GPS signals via a fast acquisition, high sensitivity acquisition circuit. Although the present invention has been described with reference to specific embodiments, it will be apparent that various modifications and changes may be made to these embodiments without departing from the scope and spirit of the invention as defined in the claims. The specification and drawings are, accordingly, to be regarded in an illustrative rather than a restrictive sense.

Claims (38)

1. A matched filter circuit, comprising:

an input terminal for receiving a GPS signal sample;

a data shift register having a plurality of tapped delay outputs, the data shift register coupled to the input; and

a plurality of matched filter channels, each coupled to the plurality of tapped delay outputs of the data shift register, wherein each matched filter channel performs an independent matched filtering operation on the GPS signal samples, each matched filter channel providing an independent output,

wherein each matched filter channel further comprises a matched filter network operable to provide a first series of weighting coefficients corresponding to a pseudo-random sequence and a second series of weighting coefficients corresponding to a carrier frequency sequence as matched filter channel weights.

2. A matched filter circuit as in claim 1 wherein the length of said data shift register corresponds to the maximum length of the parallel data inputs of said plurality of matched filter channels.

3. A matched filter circuit as in claim 1 wherein the different coefficients of the second series of weighting coefficients are shorter in length than the first series of weighting coefficients.

4. A matched filter circuit as recited in claim 1, wherein each matched filter channel of said plurality of matched filter channels further comprises:

a first circuit for periodically changing one or more of the weighting coefficients of the first series; and

a second circuit for time correcting samples of the GPS signals after the matched filtering operation.

5. A matched filter circuit as recited in claim 4, wherein each of the plurality of matched filter channels further comprises:

a third circuit for periodically changing one or more of the second series of weighting coefficients; and

fourth circuitry for carrier correcting samples of the GPS signals after the matched filtering operation.

6. A matched filter circuit as recited in claim 1, wherein each of said plurality of matched filter channels further comprises:

a first circuit for periodically changing one or more of the second series of weighting coefficients; and

second circuitry for carrier correcting the GPS signal samples after the matched filter operation.

7. The matched filter circuit of claim 1, wherein at any time the tap delay outputs of the data shift register hold data words independent in time of a one chip interval of the global positioning system signal.

8. A matched filter circuit as in claim 7 further comprising a filter coupled to an input of said data shift register that matches the waveform of individual chips of said global positioning system signal.

9. A matched filter circuit as claimed in claim 1 wherein said data shift register is a multi-bit shift register capable of shifting in parallel all bits associated with a data word represented in a multi-bit arithmetic format.

10. A method of acquiring and tracking gps signals, comprising the steps of:

receiving a sample of a global positioning system signal;

providing samples of the global positioning system signal to a plurality of matched filter channels through a plurality of tap delay outputs of a shift register;

in each of the plurality of matched filter channels, a first series of weighting coefficients corresponding to a pseudo-random sequence and a second series of weighting coefficients corresponding to a carrier frequency sequence are provided as matched filter channel weights.

11. The method of claim 10, wherein a length of the shift register corresponds to a maximum length of parallel data inputs of the plurality of matched filter channels.

12. The method of claim 10, further comprising the steps of:

periodically changing one or more of the weighting coefficients of the first series; and

time correcting the GPS signal samples after providing the GPS signal samples in at least one of the plurality of matched filter channels.

13. The method of claim 12, further comprising the steps of:

periodically changing one or more of the second series of weighting coefficients; and

in at least one of the plurality of matched filter channels, after providing the GPS signal samples, carrier correcting the GPS signal samples.

14. The method of claim 10, further comprising the steps of:

periodically changing one or more of the second series of weighting coefficients; and

in at least one of the plurality of matched filter channels, after providing the GPS signal samples, carrier correcting the GPS signal samples.

15. A method of acquiring and tracking gps signals, comprising the steps of:

performing pseudo-random noise matched filter operation on a current sample set of global positioning system signals to provide a current matched filter output data block; and

linearly combining a first set of at least one previously matched block of filter output data with said currently matched block of filter output data to produce a first linearly combined block of output data, wherein the start of each block in said first set occurs at a time relative to said currently matched block of filter output equal to the duration of a plurality of frames of said global positioning system signal;

performing a non-linear operation on the first linearly combined output data block to provide a first detected data block;

performing a pseudo-random noise matched filter operation on a sample set of global positioning system signals subsequent to the current sample set to provide a subsequent matched filter output data block;

linearly combining a second set of at least one previously matched filter output data block with said subsequent matched filter output data block to produce a second linearly combined output data block, wherein the start of each block in said second set occurs at a time relative to said subsequent matched filter output block equal to the duration of a plurality of frames of said global positioning system signal;

performing a non-linear operation on the second linearly combined output data block to provide a second detected data block;

linearly combining the second detected data block with the first detected data block to provide a combined detected block; and

determining a time of arrival estimate of at least one component signal of the global positioning system signal using the combined detection block.

16. The method of claim 15 wherein said current matched filter output data block comprises at least one set of data occurring over a time interval equal to a fraction of one frame period of said global positioning system signal, said fraction exceeding 1/256.

17. The method of claim 16, further comprising storing the first block of linear combined output data at a set of predetermined locations.

18. The method of claim 16, wherein said step of linearly combining said current block of matched filter output data and said first set of at least one previous block of matched filter output data comprises linear scaling and addition operations.

19. The method of claim 16, wherein the step of linearly combining the second block of detected data with the first block of detected data is a linear scaling and addition operation.

20. The method of claim 15, wherein the first detection data block is shifted in time relative to the second detection data block by a plurality of frame durations of the global positioning system signal.

21. The method of claim 15, wherein the non-linear operation is one of a magnitude squaring operation and an envelope operation.

22. The method of claim 15 wherein said matched filter operation on a current sample set of said GPS signals further comprises a plurality of matched filter sub-operations, each of said sub-operations being performed by a separate unit, and wherein the outputs of said units are further combined to produce said current matched filter output data block.

23. The method of claim 22, wherein said sub-operations are performed on subsets of data and filter weights, and said sub-operations are the same except for the subset of data and the filter weights at which each of said plurality of sub-operations is performed.

24. The method of claim 22, wherein each sub-operation of the plurality of matched filter sub-operations employs a single weighting and accumulation unit.

25. The method of claim 15 wherein said matched filter operation on a current sample set of said GPS signals employs a matched filter whose response is matched to a portion of a full pseudorandom frame.

26. The method of claim 15 wherein said matched filter operation on a current sample set of said GPS signals employs a matched filter which is matched to a full pseudorandom frame and which provides as output a number of words less than the word corresponding to the full frame length of said global positioning system signal.

27. The method of claim 15 wherein said matched filter operation on a current sample set of said GPS signals employs a matched filter which matches a portion of an entire pseudorandom frame and which provides as output a few words whose length is less than a word corresponding to the entire frame length of said global positioning system signal.

28. A circuit for acquiring and tracking a global positioning system signal received in a global positioning system receiver, the circuit comprising:

an input signal port for receiving a global positioning system signal;

a matched filter coupled with the input signal port to generate a set of filtered data;

a first loop integrator coupled to an output of the matched filter, the first loop integrator having an output;

a non-linear operator coupled to the output of the first loop integrator, the non-linear operator having an output;

a second loop integrator coupled to an output of the non-linear operator;

wherein the first loop integrator combines a first block of filtered data from the matched filter with a subsequent block of filtered data from the matched filter, and a start of the first block of data and a start of the subsequent block of data occur separated by a plurality of frame durations of the global positioning system signal.

29. The circuit of claim 28, further comprising:

a digital frequency conversion circuit coupled to the input signal port;

a digital resampler circuit coupled to the digital frequency conversion circuit; and

a register set coupled with the first loop integrator and the second loop integrator.

30. The circuit of claim 29 wherein said circuit tracks at least one constituent signal of said received global positioning system signal.

31. The circuit of claim 30, wherein at least one of the first loop integrator and the second loop integrator implements a unity gain feedback circuit.

32. The circuit of claim 29, wherein at least one of the first loop integrator and the second loop integrator implements a feedback circuit with less than unity gain.

33. The circuit of claim 29, wherein the register bank is implemented by random access memory.

34. The circuit of claim 28, further comprising a third loop integrator coupled to an output of the matched filter and coupled to an input of the first loop integrator.

35. A system for receiving a global positioning system signal, comprising:

means for receiving a global positioning system signal;

means for performing matched filter operations on said received gps signals;

means for performing a first loop integration operation on the output of the matched filter;

means for performing a nonlinear operation on the output signal of the first loop integrator;

means for performing a second loop integration operation on the output of the nonlinear operation;

wherein the first loop integrator combines a first block of filtered data with a subsequent block of filtered data, and a start of the first block of data and a start of the subsequent block of data occur separated by a plurality of frame durations of the global positioning system signal.

36. A matched filter circuit, comprising:

an input of said matched filter circuit capable of receiving a sample of a GPS signal;

a multiplexer having a first input coupled to the matched filter input, and the multiplexer further having an output;

a shift register having an input directly connected to an output of the multiplexer;

a multiplier-accumulator combination coupled to a final output stage of the shift register, and

a second input of the multiplexer directly connected to a last output stage of the shift register.

37. A matched filter circuit as in claim 36 wherein said matched filter circuit performs a matched filtering operation on samples of said GPS signal.

38. A matched filter circuit as in claim 36 wherein said shift register is a multi-bit shift register capable of shifting all bits associated with a data word represented in a multi-bit arithmetic format in parallel.