HK1010437B - Method and apparatus for concealing bit errors and interpolations in digital sound signals - Google Patents

Description

In the case of the reproduction of an audio signal, especially a digital audio signal, there are occasional or permanent errors which cannot be corrected by a suitable data/correction system. In such a case, an interpolation is then performed which makes an estimate of the possible signal and which to a certain extent cannot be perceived by the ear. Such an interpolation is carried out, for example, in the Sony-IC CXD1167Q or Philips SAA7220 (Sony, Philips: trademarks).

FR-A-2 486 272 is a known audio signal reproducing apparatus, having an audio signal reproducing circuit, with an error-correcting stage, a counter which measures the number of errors per predefined time unit and a second counter connected to the counter which limits and/or reduces the amplitude of the audio signal frequency shares depending on an output signal of the counter. The audio signal to be reproduced is fed by a recording medium switch and a frequency characteristic characteristic, which is fed from the output signal of the error-correcting stage. The initial error-correcting signal is fed to the output signal in a direction which is determined by the frequency of the error-correcting stage. The frequency of the error-correcting stage is changed depending on the frequency of the counter.

The disadvantage of this method or of the circuit of the known apparatus is that, in the event of irreparable errors, the faulty data block is removed or replaced by data obtained from other data by an arithmetical operation.

The purpose of the invention is to render interpolations in the audio signal inaudible.

According to the invention in claim 1, this is achieved by a process for reproducing an audio signal which undergoes one or more interpolations before reproduction, whereby frequency fractions of the audio signal are limited and/or reduced in amplitude after interpolation depending on the interpolation rate.

The present invention is based on the finding that the audibility of interpolations is highly dependent on the audio frequency and that therefore the audibility of interpolations should be taken into account in interpolations. In particular, it is not the same for the perception of interpolations whether a large proportion of low or high frequencies are contained in the audio spectrum.

The disadvantage of the above-mentioned well-known devices is that they do not take into account the audibility of interpolations, which is highly dependent on the audio frequency.

Since the number of interpolations cannot be reduced easily, it is preferable to reduce and/or limit the amplitude at higher frequency ratios depending on the interpolation rate.

The following illustration illustrates the invention in more detail by means of an example of an embodiment: Figure 1 Interpolation stage diagram Figure 2 Interpolation frequency-dependent audibility limit in the reproduction of sine signals Figure 3 Block diagram of a conventional type audio-reproduction circuit Figure 4 Block diagram of an audio-reproduction circuit according to the invention Figure 5 Alternative block diagram of an audio-reproduction circuit to Figure 4Figure 6 Pulse diagram according to the circuit according to Figure 5Figure 7 Block diagram of an audio-reproduction circuit with two-stage physiological control Figure 8An alternative version of the block diagram according to Figure 4Figure 9An alternative version of the block diagram according to Figure 4.

Fig. 1 shows a basic circuit of an audio playback circuit with a linear interpolation stage 2 and an error correction circuit 1 as known from Sony IC CXD1167Q or Philips SAA 7220 (Sony, Philips: trademarks). The error correction stage 1 has two outputs, with the first output directly connected to the interpolation stage 2 of an audio channel and the second output connected to an E of a sample check circuit (sample check) 3. The first output of the error correction circuit is connected to an input of a first output value switch (n-1) 4a, which in turn is connected to an output data connected to a second output value switch (n-1) 4bb. The first output value 4a+ is connected to an output data link (a) 6a+b. The second output is connected to an output data link (a) 6a+b. The second output is connected to an output data link (a) 6a+b. The second output is connected to an output data link (a) 6a+b. The second output is connected to an output data link (a) 6a+b. The second output is connected to an output data link (a) 6a+b. The second output is connected to an output data link (a) 6a+b. The second output is connected to an output data link (a) 6a) 6a+b. The second output is connected to an output data link (a) 6a) 6a+b. The second output output is connected to an output data link (b) 6a+b. The second output is connected to an output data link (b) 6a) 6a+b. The second output is connected to an output data link (b) 6a+b. The second output is connected to a data link (b) 6a) 6a+b. The second output is connected to a data link (b) 6a) 6a+b.

The 3rd test circuit checks the test values for their defectiveness, i.e. also their incorrigibleness by the error correction stage 1, and generates a logical 1 if the test value is defective and a logical 0 if the test value is correct. These values are fed to downlinked support elements 4d, 4e and 4f. The outputs of the 4d and 4f support elements are each connected to inverters 8a and 8b, whose outputs together with the output of the 4e support element are fed to the input of a UND gate 9. The output of the UND gate 9 is fed to the output switch 5 and the control switch is connected to the output switch between the sum of the 7F and the 4th output of the UND gate 9 and is a widely interpolated output of the 9th output switch.

Figure 2 shows the experimentally determined audibility limit over the number of interpolations per second or the error rate depending on the audio frequency (logarithmically applied).

Fig. 3 shows a block diagram of a conventional type of audio reproduction circuit which has a fault correction circuit 1, an interpolation stage 2, a D/A converter 10, a circuit 11 for processing analogue audio signals and a loudspeaker 12.

Fig. 4 shows a block diagram of an audio feedback circuit according to the invention. A known error correction circuit 1 is the one that is down-switched from the interpolation circuit 2 known from Fig. 1. The data output of the interpolation circuit 2 is connected to the input of a D/A converter 10 whose output is connected to the analogue audio/signal processing circuit 11. The I-flag output of the interpolation stage 2 is connected to a sword wave rating and processing stage 13, which in turn is connected to a physiological correction and control stage 14. The physiological correction stage 14 reduces depending on whether the interpolation rate exceeds a predetermined signal, by means of a higher analogue amplitude of the frequency processing of the analogue audio wave control circuit 11.

In practical experiments it has been shown that the threshold value S should preferably be at S = 30 interpolations per second. It can, as shown in Figure 5, be determined per second by means of a counter 15 with a clock and reset input next to the I-flag input.

The pulse diagram for the device as shown in Fig. 5 is shown in Fig. 6. At the end of a predetermined time unit, here one second, the output of the meter 15 is reset to zero by the reset signal at the entrance of the meter 15. The output of the mono-flip-flop 16 activates the low pass 17 until the number of interpolations per unit of time falls below the predetermined value.

Fig. 7 shows the block diagram of an audio reproduction circuit with a two-stage physiological control. Such a circuit allows a multi-stage lowering of the higher frequencies by activating, depending on the size of the interpolation rate, the corresponding low passes 17a, 17b in the analogue audio reproduction circuit with several mono-flip flops 16a, 16b.

Fig. 8 shows a further development of the invention as shown in Fig. 4. In Fig. 8 a memory 18 is proposed for the interim storage of audio data in the digital signal pathway. This memory 18, which can also be trained as so-called shock memory, can be used to improve physiological regulation in the event of interpolations, so that the regulation is activated before the interpolation disorders begin.

So far, examples of physiological audio control have been shown on the analog side of audio playback.

Fig. 9 shows an example of physiological control of the audio signals on the digital side. This involves frequency evaluation of the data intercepted in memory 18 in the event of interpolation flags via digital filters in a digital signal processor 20 (DSP) and corresponding reduction of the amplitudes for high frequencies. The output of the digital signal processor 20 is connected to the D/A converter stage 10 which in turn is switched back to the analogue audio output stage 11.

The invention can be used in all types of digital audio and video systems, in particular in devices and circuits in the field of compact disc (CD), magneto-optic disc (MOD), digital audio broadcast (DAB), digital satellite radio (DSR), NICAM devices, digital compact cassette (DCC), mini disc (MD) and audio systems, where errors that can no longer be corrected in the corresponding data correction systems are subject to interpolation.

Claims (17)

1. Process for the reproduction of an audio signal which is subjected to an error correction before reproduction, frequency components of the audio signal being limited and/or reduced in their amplitude, characterized in that the error correction includes one or more interpolations, and frequency components of the audio signal are limited or reduced in their amplitude after the error correction as a function of the interpolation or error rate.
2. Process according to Claim 1, characterized in that, if the interpolation rate exceeds a predetermined threshold, frequency components of the audio signal are limited and/or reduced in their amplitude.
3. Process according to Claim 2, characterized in that a multi-stage lowering is carried out.
4. Process according to one of Claims 1 to 3, characterized in that only those frequency components of the audio signal in which the interpolations cause audible disturbances are limited or reduced in their amplitude.
5. Process according to Claim 4, characterized in that an audibility limit which takes into account the audibility of interpolations as a function of the audio frequency is fixed and stored.
6. Process according to one of the preceding claims, characterized in that a reduction and/or limitation of the amplitudes of higher frequency components takes place if disturbances, caused by interpolations, are audible.
7. Circuit for the reproduction of audio signals, having an error correction stage (1, 2), a counting means (13) and a second means (14), which is connected to the counting means and limits and/or reduces frequency components of the audio signal in their amplitude as a function of an output signal of the counting means (13), characterized in that the circuit has an interpolation stage (2), the counting means (13) measures the number of interpolations or errors per predetermined unit of time, and the second means (14) is arranged downstream of the error correction stage (1, 2).
8. Circuit according to Claim 7, characterized in that there are a plurality of interpolation stages (2).
9. Circuit according to either of Claims 7 and 8, characterized in that the second means has a plurality of stages (16a, 17a; 16b, 17b) which limit and/or reduce frequency components of the audio signal in their amplitude.
10. Circuit according to one of Claims 7 to 9, characterized in that the audio signal to be reproduced is a digital audio signal, in that the interpolation stage (2) is connected to a D/A converter stage (10), which for its part is in turn connected to an analogue audio processing stage (11), which has a control input which is connected to a control output of the second means (14) for limiting and/or reducing the amplitude of frequency components.
11. Circuit according to one of Claims 7 - 10, characterized in that the counting means (13) has a counter (15), which establishes the number of interpolations per predetermined unit of time, in that the counter (15) compares the number of interpolations established per unit of time with a threshold (S) stored in a memory and, dependent on the result of the comparison, switches on the second means (14).
12. Circuit according to one of Claims 7 - 11, characterized in that the second means is a low-pass filter (17, 17a, 17b), which primarily limits and/or reduces the amplitude of higher frequencies of the audio signal.
13. Circuit according to one of Claims 7 - 12, characterized in that a buffer memory (18) is provided in the digital signal path of the audio reproduction circuit, preferably between the interpolation stage (2) and the D/A converter stage (10).
14. Circuit according to one of Claims 7 - 13, characterized in that, for reducing and/or limiting the amplitudes of the high-frequency audio signal components, there is provided a digital signal processor (20), which on the one hand evaluates the digital audio signal in terms of frequency and performs the reduction and/or limitation of the amplitude for high frequencies as a function of the interpolations occurring.
15. Apparatus having a circuit for carrying out the process according to one of Claims 1 - 5.
16. Apparatus according to Claim 15 for the reproduction of digital audio signals, in particular a compact disc player (CD) or magneto-optical disc player (MOD) or digital compact cassette player (DCC) or digital audio broadcast device (DAB), characterized in that it has a circuit according to one of Claims 7-14.
17. Apparatus according to Claim 16, characterized in that the device has an indicating device for indicating the interpolation rate and/or error rate, and in that the indicating device can be connected to the counting means (13) and/or the second means (14).