GB997835A - Improvements in or relating to electrical signalling systems - Google Patents

Abstract

997,835. Multiplex pulse code signalling. BRITISH TELECOMMUNICATIONS RESEARCH Ltd. May 8, 1963 [May 16, 1962], No. 18899/62. Addition to 946,254. Heading H4L. The system of the parent Specification for interconnecting pulse communication systems subject to variations in timing in which two stores are used alternatively and provided with means for altering the storage sequence in the event of phase conflict is adapted to enable the combination of a number of low-speed pulse communication systems into a single high-speed system. Fig. 2 shows the equipment associated with one channel CH1, CH2 ... CHm indicating the remaining low-speed channels. It is assumed that the transmission speed of the incoming channels is a bits/second so that the transmission rate for n channels over the high-speed channels will be na bits/second. A clock LC for channel CH1 is operated by timing pulses on line DS and a clock HC for the high-speed system is operated by timing pulses on line SS. The capacity of each store M, M<SP>1</SP> &c., is c bits and the clock LC produces an output pulse every c timing pulses which controls a gate GA producing alternate outputs A, A<SP>1</SP>. Gates GB, GC, GD are linked to change over in synchronism with gate GA so that when gates GA, GD are providing outputs on A and D respectively, the gate GB is providing an output on B<SP>1</SP> and input C<SP>1</SP> is operative for gate GC, and vice versa. Assuming that gate GA is supplying an output on A, the incoming data signals over lead D are supplied to the store M, writing-in being controlled by timing pulses via gate GD. The clock HC also provides an output every C timing pulses but in its full cycle produces n outputs which open in turn gates GF, GG, GH &c., corresponding respectively to the low speed systems, each of these gates then closing the preceding one. When gate GF is opened high-speed timing pulses at a pulse repetition frequency na are supplied via output B<SP>1</SP> of gate GB to control the reading out of data stored in the store M<SP>1</SP> via input C<SP>1</SP> of gate GC and output terminal HS. The functions of reading and writing in the memories M, M<SP>l</SP> are reversed each time an out- - put is obtained from the clock LC and gates GA, GB, GC, GD change-over. High-speed timing pulses also pass via the gate GF to a gate GE and if the clock LC should be in the last but one position at this time a second pulse is supplied to the gate GE so that it provides an output signal RS to reset the clock LC. To minimize the error the resetting point is about halfway, C i.e. the clock is set back - bits, so that one 2 C block of - bits, may be repeated or omitted. 2