GB8900301D0 - An electronic circuit and signal processing arrangements using the electronic circuit - Google Patents
An electronic circuit and signal processing arrangements using the electronic circuitInfo
- Publication number
- GB8900301D0 GB8900301D0 GB898900301A GB8900301A GB8900301D0 GB 8900301 D0 GB8900301 D0 GB 8900301D0 GB 898900301 A GB898900301 A GB 898900301A GB 8900301 A GB8900301 A GB 8900301A GB 8900301 D0 GB8900301 D0 GB 8900301D0
- Authority
- GB
- United Kingdom
- Prior art keywords
- electronic circuit
- signal processing
- processing arrangements
- arrangements
- electronic
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
- G06F17/10—Complex mathematical operations
- G06F17/16—Matrix or vector computation, e.g. matrix-matrix or matrix-vector multiplication, matrix factorization
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
- G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
- G06F7/544—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices for evaluating functions by calculation
- G06F7/5443—Sum of products
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Computational Mathematics (AREA)
- Mathematical Physics (AREA)
- Mathematical Analysis (AREA)
- Mathematical Optimization (AREA)
- Pure & Applied Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- Computing Systems (AREA)
- Data Mining & Analysis (AREA)
- Algebra (AREA)
- Databases & Information Systems (AREA)
- Software Systems (AREA)
- Complex Calculations (AREA)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
GB8900301A GB2226899A (en) | 1989-01-06 | 1989-01-06 | An electronic circuit and signal processing arrangements using it |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
GB8900301A GB2226899A (en) | 1989-01-06 | 1989-01-06 | An electronic circuit and signal processing arrangements using it |
Publications (2)
Publication Number | Publication Date |
---|---|
GB8900301D0 true GB8900301D0 (en) | 1989-03-08 |
GB2226899A GB2226899A (en) | 1990-07-11 |
Family
ID=10649711
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
GB8900301A Withdrawn GB2226899A (en) | 1989-01-06 | 1989-01-06 | An electronic circuit and signal processing arrangements using it |
Country Status (1)
Country | Link |
---|---|
GB (1) | GB2226899A (en) |
Families Citing this family (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH04102170A (en) * | 1990-08-21 | 1992-04-03 | Fujitsu Ltd | Device and method for calculating matrix, and adaptive device |
DE4036455C1 (en) * | 1990-11-15 | 1992-04-02 | Siemens Ag, 8000 Muenchen, De | |
ZA938324B (en) * | 1992-11-24 | 1994-06-07 | Qualcomm Inc | Pilot carrier dot product circuit |
CN1107597A (en) * | 1994-02-24 | 1995-08-30 | 吴乾弥 | Pipeline type and palpitation type single-instruction multi-data-flow array processing structure and method |
Family Cites Families (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3805043A (en) * | 1972-10-11 | 1974-04-16 | Bell Telephone Labor Inc | Serial-parallel binary multiplication using pairwise addition |
US3956622A (en) * | 1974-12-20 | 1976-05-11 | Bell Telephone Laboratories, Incorporated | Two's complement pipeline multiplier |
GB2166272B (en) * | 1984-10-27 | 1988-06-29 | Stc Plc | Serial multiplier circuit |
US4809212A (en) * | 1985-06-19 | 1989-02-28 | Advanced Micro Devices, Inc. | High throughput extended-precision multiplier |
US4831577A (en) * | 1986-09-17 | 1989-05-16 | Intersil, Inc. | Digital multiplier architecture with triple array summation of partial products |
-
1989
- 1989-01-06 GB GB8900301A patent/GB2226899A/en not_active Withdrawn
Also Published As
Publication number | Publication date |
---|---|
GB2226899A (en) | 1990-07-11 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
WAP | Application withdrawn, taken to be withdrawn or refused ** after publication under section 16(1) |