GB719418A - Improvements in or relating to a pulse delaying circuit - Google Patents

Abstract

719,418. Pulse delaying circuits. INTERNATIONAL BUSINESS MACHINES CORPORATION. May 21, 1952 [July 30, 1951], No. 12835/52. Class 40 (6) Fig. 1 shows a pulse delaying circuit in which a pulse to be delayed shown at 1 in Fig. 2 is applied at an input 10 and a train of regularly recurring synchronizing pulses 2, Fig. 2, are applied at an input 11. Normally the left-hand section of valve 17 is non-conductive and since junction points 34, 35 are both normally held at a negative potential with respect to earth the latter by the application of the clamping voltage 4, Fig. 2, applied at terminal 30 and the resultant charge on capacitor 37, the right-hand section of valve 17 also has a very low conductivity. When positive pulses are present simultaneously at inputs 10 and 11 the left-hand section of valve 17 conducts, the anode potential falls, curve 3, Fig. 2, and capacitor 31 is discharged . At the approximate time when the synchronizing pulse of curve 2, Fig. 2, ends, a positive pulse passes through capacitor 31 and rectifier 26 from the anode 19 and charges capacitor 37. The right-hand section of valve 17 thus considerably increases its conductivity so that a positive output pulse curve 5, Fig. 2, appears across cathode load resistor 41 at output terminal 42 and is maintained until the next clamping pulse, curve 4, Fig. 2, is applied, or an output may be taken from terminal 35. Thus an input pulse appearing in any time interval, e.g. T1-T2 causes an output pulse to be produced in the succeeding time interval.