GB2637975A - Digital drive scheme for LCOS - Google Patents

Abstract

A display device that comprises a pulse generator 700 to generate a plurality of pulse trains b[0] to b[3], wherein each pulse train has a respective pulse frequency; a plurality of pulse lines, wherein each pulse line is arranged to transmit a respective pulse train and a plurality of pixels. Wherein each pixel 711, 712, 71N comprises: memory (memory-in-pixel) for storing an n-bit number which may represent a drive level (or pixel value e.g. grey level); a plurality of gates wherein each gate is connected to a respective pulse line and each gate corresponds to a respective bit of the n-bit number; and a pulse combiner arranged to combine the outputs of the gates to produce a combined pulse train. Wherein the outputs of the gates are interleaved in time such that the pulse trains of the different lines are non-overlapping and the frequency of each pulse train is a function of the significance of the bit of the n- bit number.

Description

DIGITAL DRIVE SCHEME FOR LCOS

FIELD

The present disclosure relates to a digital drive scheme for a display device and a method of driving a display device. The present disclosure also relates to a display device such as a spatial light modulator. More specifically, the present disclosure relates to a phase modulator such as a liquid crystal on silicon spatial light modulator. The present disclosure also relates to a memory-in-pixel or memory-on-pixel display device.

BACKGROUND AND INTRODUCTION

Light scattered from an object contains both amplitude and phase information. This amplitude and phase information can be captured on, for example, a photosensitive plate by well-known interference techniques to form a holographic recording, or "hologram", comprising interference fringes. The hologram may be reconstructed by illumination with suitable light to form a two-dimensional or three-dimensional holographic reconstruction, or replay image, representative of the original object.

Computer-generated holography may numerically simulate the interference process. A computer-generated hologram may be calculated by a technique based on a mathematical transformation such as a Fresnel or Fourier transform. These types of holograms may be referred to as Fresnel/Fourier transform holograms or simply Fresnel/Fourier holograms. A Fourier hologram may be considered a Fourier domain/plane representation of the object or a frequency domain/plane representation of the object. A computer-generated hologram may also be calculated by coherent ray tracing or a point cloud technique, for example.

A computer-generated hologram may be encoded on a spatial light modulator arranged to modulate the amplitude and/or phase of incident light. Light modulation may be achieved using electrically-addressable liquid crystals, optically-addressable liquid crystals or micro-mirrors, for example.

A spatial light modulator typically comprises a plurality of individually-addressable pixels which may also be referred to as cells or elements. The light modulation scheme may be binary, multilevel or continuous. Alternatively, the device may be continuous (i.e. is not comprised of pixels) and light modulation may therefore be continuous across the device.

The spatial light modulator may be reflective meaning that modulated light is output in reflection. The spatial light modulator may equally be transmissive meaning that modulated light is output in transmission.

A holographic projector may be provided using the system described herein. Such projectors have found application in head-up displays, "HUD", and head-mounted displays, "HMD", including near-eye devices, for example.

A spatial light modulator typically comprises a plurality of individually-addressable pixels which may also be referred to as cells or elements. A common electrode and a matrix (or, array) of pixel electrodes are provided, wherein the size of the pixel electrodes delineates the size of the pixels of the device. In Liquid Crystal on Silicon, "LCOS", spatial light modulators a liquid crystal (LC) layer is provided between the common electrode and the array of pixel electrodes.

Liquid crystal on silicon, "LCOS", spatial light modulators exploit the birefringence of liquid crystals to provide controllable phase modulation, wherein an alternating polarity of voltage can be applied to each pixel electrode, whilst keeping common electrode fixed, in order to provide respective modulation (or, "retardation", or "retardance") in each cell. The so-called "dynamic range" of the cells of a spatial light modulator is the maximum achievable retardation (e.g., at V=0) minus the minimum achievable retardation (e.g., at V=V) that the cells can provide. It is generally desirable for a spatial light modulator to have a broad dynamic range, to be a useful and flexible as possible. The ideal phase modulator would be able to provide a variable phase retardation between zero and 27. The birefringence of the liquid crystal determines the optical path length required to provide the full 22-c phase retardation. Specifically, the optical path length range for a reflective modulator should equal 27. The optical path length increases with the thickness of the liquid crystal layer (d), the birefringence of the liquid crystal (An) and the angle of incidence (0) of incident light.

In some applications, there is a desire to decrease the size of each individual pixel and to increase the number of pixels comprised within an LCOS device. This typically is of benefit when the aim is to achieve a high resolution. A drawback with this approach is, however, that each individual pixel is subjected to both a vertical and a horizontal electronic-field between adjacent electrodes. This can cause a non-uniform electric field across a single pixel, which in turn can cause distortion of the liquid crystal molecules that are driven by the non-uniform electric field. The effective phase retardation of each pixel therefore becomes different from the intended values. So-called "fringing field effect" (FFE) can result in poor optic contrast and non-uniform phase.

The inventor has addressed these problems. A holographic projector may be provided using the concepts described herein. Such projectors have found application in head-up displays, "HUD", and head-mounted displays, "HMD", including near-eye devices, for example.

SUMMARY

Aspects of the present disclosure are defined in the appended independent claims.

A first aspect of the present disclosure is a display device. The display device comprises a pulse generator, a plurality of pulse lines (connected to the pulse generator) and a plurality of pixels. The pulse generator is arranged to generate a plurality of pulse trains. Each pulse train has a respective pulse frequency. The frequency of each pulse train is substantially constant or non-varying. Each pulse line is arranged to transmit a respective pulse train. Each pixel of the plurality of pixels comprises memory, a plurality of gates and a pulse combiner (or "demultiplexer"). The memory (which may be referred to as "memory-inpixel") is arranged to store an n-bit (binary) number representative of a drive level (or pixel value e.g. grey level). Each gate is connected to a pulse line. Each gate corresponds to a bit of the n-bit number. There may be fewer pulse lines and gates than bits of the n-bit number. That is, the number of pulse trains may be less than n. In some embodiments, the number of pulse trains, and therefore number of respective gates at each pixel, is n-1.

The pulse combiner is arranged to combine the outputs of the gates to produce a combined pulse train. The outputs of the gates are interleaved in time. The pulse trains of the different lines are non-overlapping. The frequency of the pulse train is a function of the significance of the bit of the n-bit number. In some embodiments, the more significant the bit of the n-bit number, the higher the frequency of the corresponding pulse train. The frequency of the pulse train may be a linear function of the significance of the bit of the n-bit number. The pulse generator may be arranged such that the pulses of the plurality of lines are non-overlapping. The duration of every pulse of every pulse train may be substantially equal.

A first subset (e.g. first half such as lower half) of drive levels may be formed by adding the output of the gates to a zero baseline (e.g. OV) to produce the combined pulse train and the remaining drive levels (e.g. a second subset or second half such as the upper half of drive levels) may be formed by subtracting the output of the gates from a positive, non-zero (e.g. 5V) baseline to produce the combined pulse train -or vice versa. Accordingly, the number of pulse lines may be n-1, where n is the number of bits of the n-bit drive scheme.

One bit of the n-bit number (e.g. the most significant bit) may be used to determine whether the n-bit number is part of the first subset of drive levels or the remaining drive levels. For example, if said one bit is "0", the drive level may be part of the first subset. If said one bit is a "1", the drive level may be part of the second subset.

Each gate of a pixel may be independently operable in an open or closed state to reflect (or represent) the bit value of the corresponding bit of the n-bit number stored in the memory.

Each gate may be independently operable in accordance with the respective bit value for a time period necessary to drive the pixel.

The pulse generator and a first gate corresponding to the least significant bit may be coordinated. Therefore, only one pulse is transmitted by the first gate, Gl, within the time period, -Et The single pulse transmitted by the first gate, Gl, may be substantially centred, in time, within the time period.

The pulse generator and gates may be configured such that the number of pulses occurring within the time period is equal to the bit number, 1 to n.

The pattern of pulses of each individual gate, when in an open state, may be symmetric about the centre, in time, of the time period.

The pulses of each pulse train may be evenly distributed within the time period.

The combined pulse train may be a digital representation of an n-bit pixel value.

The display device may further comprise a clock. The clock may be a static clock or a spread spectrum clock.

A second aspect of the present disclosure is a method of driving pixels of a display device using a pulse modulation scheme. The method comprises a first step of generating a plurality of pulse trains. Each pulse train has a respective pulse frequency. The method comprises a second step of storing an n-bit number at each pixel of a plurality of pixels. The method comprises a third step of delivering each pulse train of the plurality of pulse trains to a respective gate of a plurality of gates of each pixel. Each gate corresponds to a respective bit of the n-bit number. The method comprises a fourth step of combining the outputs of the gates to produce a combined pulse train. The outputs of the gates are interleaved in time such that the pulse trains of the different lines are non-overlapping. The frequency of the pulse train is a function of the significance of the bit of the n-bit number.

The term "hologram" is used to refer to the recording which contains amplitude information or phase information, or some combination thereof, regarding the object. The term "holographic reconstruction" is used to refer to the optical reconstruction of the object which is formed by illuminating the hologram. The system disclosed herein is described as a "holographic projector" because the holographic reconstruction is a real image and spatially-separated from the hologram. The term "replay field" is used to refer to the 2D area within which the holographic reconstruction is formed and fully focused. If the hologram is displayed on a spatial light modulator comprising pixels, the replay field will be repeated in the form of a plurality diffracted orders wherein each diffracted order is a replica of the zeroth-order replay field. The zeroth-order replay field generally corresponds to the preferred or primary replay field because it is the brightest replay field. Unless explicitly stated otherwise, the term "replay field" should be taken as referring to the zeroth-order replay field. The term "replay plane" is used to refer to the plane in space containing all the replay fields. The terms "image", "replay image" and "image region" refer to areas of the replay field illuminated by light of the holographic reconstruction. In some embodiments, the "image" may comprise discrete spots which may be referred to as "image spots" or, for convenience only, "image pixels".

The terms "encoding", "writing" or "addressing" are used to describe the process of providing the plurality of pixels of the SLM with a respective plurality of control values which respectively determine the modulation level of each pixel. It may be said that the pixels of the SLM are configured to "display" a light modulation distribution in response to receiving the plurality of control values. Thus, the SLM may be said to "display" a hologram and the hologram may be considered an array of light modulation values or levels.

It has been found that a holographic reconstruction of acceptable quality can be formed from a "hologram" containing only phase information related to the Fourier transform of the original object. Such a holographic recording may be referred to as a phase-only hologram. Embodiments relate to a phase-only hologram but the present disclosure is equally applicable to amplitude-only holography.

The present disclosure is also equally applicable to forming a holographic reconstruction using amplitude and phase information related to the Fourier transform of the original object. In some embodiments, this is achieved by complex modulation using a so-called fully complex hologram which contains both amplitude and phase information related to the original object. Such a hologram may be referred to as a fully-complex hologram because the value (grey level) assigned to each pixel of the hologram has an amplitude and phase component. The value (grey level) assigned to each pixel may be represented as a complex number having both amplitude and phase components. In some embodiments, a fully-complex computer-generated hologram is calculated.

Reference may be made to the phase value, phase component, phase information or, simply, phase of pixels of the computer-generated hologram or the spatial light modulator as shorthand for "phase-delay". That is, any phase value described is, in fact, a number (e.g. in the range 0 to 2n) which represents the amount of phase retardation provided by that pixel. For example, a pixel of the spatial light modulator described as having a phase value of n/2 will retard the phase of received light by n/2 radians. In some embodiments, each pixel of the spatial light modulator is operable in one of a plurality of possible modulation values (e.g. phase delay values). The term "grey level" may be used to refer to the plurality of available modulation levels. For example, the term "grey level" may be used for convenience to refer to the plurality of available phase levels in a phase-only modulator even though different phase levels do not provide different shades of grey. The term "grey level" may also be used for convenience to refer to the plurality of available complex modulation levels in a complex modulator.

The hologram therefore comprises an array of grey levels -that is, an array of light modulation values such as an array of phase-delay values or complex modulation values. The hologram is also considered a diffractive pattern because it is a pattern that causes diffraction when displayed on a spatial light modulator and illuminated with light having a wavelength comparable to, generally less than, the pixel pitch of the spatial light modulator.

Reference is made herein to combining the hologram with other diffractive patterns such as diffractive patterns functioning as a lens or grating. For example, a diffractive pattern functioning as a grating may be combined with a hologram to translate the replay field on the replay plane or a diffractive pattern functioning as a lens may be combined with a hologram to focus the holographic reconstruction on a replay plane in the near field.

Although different embodiments and groups of embodiments may be disclosed separately in the detailed description which follows, any feature of any embodiment or group of embodiments may be combined with any other feature or combination of features of any embodiment or group of embodiments. That is, all possible combinations and permutations of features disclosed in the present disclosure are envisaged.

BRIEF DESCRIPTION OF THE DRAWINGS

Specific embodiments are described by way of example only with reference to the following figures: Figure 1 is a schematic showing a reflective SLM producing a holographic reconstruction on a screen; Figure 2A illustrates a first iteration of an example Gerchberg-Saxton type algorithm; Figure 2B illustrates the second and subsequent iterations of the example Gerchberg-Saxton type algorithm; Figure 2C illustrates alternative second and subsequent iterations of the example Gerchberg-Saxton type algorithm; Figure 3 is a schematic of a reflective LCOS SLM; Figures 4A and 4B show a pulse wave modulation scheme providing two different equivalent voltages; Figures 5A and 5B show a gated clock scheme and a variable pulse density scheme, respectively; Figures 6A and 6B represent the combination of plurality of pulse trains in accordance with embodiments; Figure 7 shows example pixel gating in accordance with embodiments; Figures 8A to 8C show three example pulse patterns formed in accordance with embodiments; Figures 9A to 9D show some different clock schemes in accordance with examples and embodiments; Figure 10 show reduced signal ripple in accordance with examples and embodiments; Figure 11 shows a 9-bit scheme in accordance with embodiments; Figure 12 shows a first operating mode of further embodiments; and Figure 13 shows a second operating mode of further embodiments.

The same reference numbers will be used throughout the drawings to refer to the same or like parts.

DETAILED DESCRIPTION OF EMBODIMENTS

The present invention is not restricted to the embodiments described in the following but extends to the full scope of the appended claims. That is, the present invention may be embodied in different forms and should not be construed as limited to the described embodiments, which are set out for the purpose of illustration.

Terms of a singular form may include plural forms unless specified otherwise.

A structure described as being formed at an upper portion/lower portion of another structure or on/under the other structure should be construed as including a case where the structures contact each other and, moreover, a case where a third structure is disposed there between.

In describing a time relationship -for example, when the temporal order of events is described as "after", "subsequent", "next", "before" or suchlike -the present disclosure should be taken to include continuous and non-continuous events unless otherwise specified. For example, the description should be taken to include a case which is not continuous unless wording such as "just", "immediate" or "direct" is used.

Although the terms "first", "second", etc. may be used herein to describe various elements, these elements are not to be limited by these terms. These terms are only used to distinguish one element from another. For example, a first element could be termed a second element, and, similarly, a second element could be termed a first element, without departing from the scope of the appended claims.

Features of different embodiments may be partially or overall coupled to or combined with each other, and may be variously inter-operated with each other. Some embodiments may be carried out independently from each other, or may be carried out together in codependent relationship.

Optical configuration Figure 1 shows an embodiment in which a computer-generated hologram is encoded on a single spatial light modulator. The computer-generated hologram is a Fourier transform of the object for reconstruction. It may therefore be said that the hologram is a Fourier domain or frequency domain or spectral domain representation of the object. In this embodiment, the spatial light modulator is a reflective liquid crystal on silicon, "LCOS", device. The hologram is encoded on the spatial light modulator and a holographic reconstruction is formed at a replay field, for example, a light receiving surface such as a screen or diffuser.

A light source 110, for example a laser or laser diode, is disposed to illuminate the SLM 140 via a collimating lens 111. The collimating lens causes a generally planar wavefront of light to be incident on the SLM. In Figure 1, the direction of the wavefront is off-normal (e.g. two or three degrees away from being truly orthogonal to the plane of the transparent layer).

However, in other embodiments, the generally planar wavefront is provided at normal incidence and a beam splitter arrangement is used to separate the input and output optical paths. In the embodiment shown in Figure 1, the arrangement is such that light from the light source is reflected off a mirrored rear surface of the SLM and interacts with a light-modulating layer to form an exit wavefront 112. The exit wavefront 112 is applied to optics including a Fourier transform lens 120, having its focus at a screen 125. More specifically, the Fourier transform lens 120 receives a beam of modulated light from the SLM 140 and performs a frequency-space transformation to produce a holographic reconstruction at the screen 125.

Notably, in this type of holography, each pixel of the hologram contributes to the whole reconstruction. There is not a one-to-one correlation between specific points (or image pixels) on the replay field and specific light-modulating elements (or hologram pixels). In other words, modulated light exiting the light-modulating layer is distributed across the replay field.

In these embodiments, the position of the holographic reconstruction in space is determined by the dioptric (focusing) power of the Fourier transform lens. In the embodiment shown in Figure 1, the Fourier transform lens is a physical lens. That is, the Fourier transform lens is an optical Fourier transform lens and the Fourier transform is performed optically. Any lens can act as a Fourier transform lens but the performance of the lens will limit the accuracy of the Fourier transform it performs. The skilled person understands how to use a lens to perform an optical Fourier transform.

Hologram calculation In some embodiments, the computer-generated hologram is a Fourier transform hologram, or simply a Fourier hologram or Fourier-based hologram, in which an image is reconstructed in the far field by utilising the Fourier transforming properties of a positive lens. The Fourier hologram is calculated by Fourier transforming the desired light field in the replay plane back to the lens plane. Computer-generated Fourier holograms may be calculated using Fourier transforms.

A Fourier transform hologram may be calculated using an algorithm such as the GerchbergSaxton algorithm. Furthermore, the Gerchberg-Saxton algorithm may be used to calculate a hologram in the Fourier domain (i.e. a Fourier transform hologram) from amplitude-only information in the spatial domain (such as a photograph). The phase information related to the object is effectively "retrieved" from the amplitude-only information in the spatial domain. In some embodiments, a computer-generated hologram is calculated from amplitude-only information using the Gerchberg-Saxton algorithm or a variation thereof.

The Gerchberg Saxton algorithm considers the situation when intensity cross-sections of a light beam, IA(x, y) and IB(x, y), in the planes A and B respectively, are known and IA(x, y) and IB(x, y) are related by a single Fourier transform. With the given intensity cross-sections, an approximation to the phase distribution in the planes A and B, IPA(x, y) and 11)B(x, y) respectively, is found. The Gerchberg-Saxton algorithm finds solutions to this problem by following an iterative process. More specifically, the Gerchberg-Saxton algorithm iteratively applies spatial and spectral constraints while repeatedly transferring a data set (amplitude and phase), representative of IA(x, y) and IB(x, y), between the spatial domain and the Fourier (spectral or frequency) domain. The corresponding computer-generated hologram in the spectral domain is obtained through at least one iteration of the algorithm. The algorithm is convergent and arranged to produce a hologram representing an input image.

The hologram may be an amplitude-only hologram, a phase-only hologram or a fully complex hologram.

In some embodiments, a phase-only hologram is calculated using an algorithm based on the Gerchberg-Saxton algorithm such as described in British patent 2,498,170 or 2,501,112 which are hereby incorporated in their entirety by reference. However, embodiments disclosed herein describe calculating a phase-only hologram by way of example only. In these embodiments, the Gerchberg-Saxton algorithm retrieves the phase information LP [u, v] of the Fourier transform of the data set which gives rise to a known amplitude information T[x, y], wherein the amplitude information T[x, y] is representative of a target image (e.g. a photograph). Since the magnitude and phase are intrinsically combined in the Fourier transform, the transformed magnitude and phase contain useful information about the accuracy of the calculated data set. Thus, the algorithm may be used iteratively with feedback on both the amplitude and the phase information. However, in these embodiments, only the phase information Lli[u, v] is used as the hologram to form a holographic representative of the target image at an image plane. The hologram is a data set (e.g. 2D array) of phase values.

In other embodiments, an algorithm based on the Gerchberg-Saxton algorithm is used to calculate a fully-complex hologram. A fully-complex hologram is a hologram having a magnitude component and a phase component. The hologram is a data set (e.g. 2D array) comprising an array of complex data values wherein each complex data value comprises a magnitude component and a phase component.

In some embodiments, the algorithm processes complex data and the Fourier transforms are complex Fourier transforms. Complex data may be considered as comprising (i) a real component and an imaginary component or (ii) a magnitude component and a phase component. In some embodiments, the two components of the complex data are processed differently at various stages of the algorithm.

Figure 2A illustrates the first iteration of an algorithm in accordance with some embodiments for calculating a phase-only hologram. The input to the algorithm is an input image 210 comprising a 2D array of pixels or data values, wherein each pixel or data value is a magnitude, or amplitude, value. That is, each pixel or data value of the input image 210 does not have a phase component. The input image 210 may therefore be considered a magnitude-only or amplitude-only or intensity-only distribution. An example of such an input image 210 is a photograph or one frame of video comprising a temporal sequence of frames. The first iteration of the algorithm starts with a data forming step 202A comprising assigning a random phase value to each pixel of the input image, using a random phase distribution (or random phase seed) 230, to form a starting complex data set wherein each data element of the set comprising magnitude and phase. It may be said that the starting complex data set is representative of the input image in the spatial domain.

First processing block 250 receives the starting complex data set and performs a complex Fourier transform to form a Fourier transformed complex data set. Second processing block 253 receives the Fourier transformed complex data set and outputs a hologram 280A. In some embodiments, the hologram 280A is a phase-only hologram. In these embodiments, second processing block 253 quantises each phase value and sets each amplitude value to unity in order to form hologram 280A. Each phase value is quantised in accordance with the phase-levels which may be represented on the pixels of the spatial light modulator which will be used to "display" the phase-only hologram. For example, if each pixel of the spatial light modulator provides 256 different phase levels, each phase value of the hologram is quantised into one phase level of the 256 possible phase levels. Hologram 280A is a phase-only Fourier hologram which is representative of an input image. In other embodiments, the hologram 280A is a fully complex hologram comprising an array of complex data values (each including an amplitude component and a phase component) derived from the received Fourier transformed complex data set. In some embodiments, second processing block 253 constrains each complex data value to one of a plurality of allowable complex modulation levels to form hologram 280A. The step of constraining may include setting each complex data value to the nearest allowable complex modulation level in the complex plane. It may be said that hologram 280A is representative of the input image in the spectral or Fourier or frequency domain. In some embodiments, the algorithm stops at this point.

However, in other embodiments, the algorithm continues as represented by the dotted arrow in Figure 2A. In other words, the steps which follow the dotted arrow in Figure 2A are optional (i.e. not essential to all embodiments).

Third processing block 256 receives the modified complex data set from the second processing block 253 and performs an inverse Fourier transform to form an inverse Fourier transformed complex data set. It may be said that the inverse Fourier transformed complex data set is representative of the input image in the spatial domain.

Fourth processing block 259 receives the inverse Fourier transformed complex data set and extracts the distribution of magnitude values 211A and the distribution of phase values 213A. Optionally, the fourth processing block 259 assesses the distribution of magnitude values 211A. Specifically, the fourth processing block 259 may compare the distribution of magnitude values 211A of the inverse Fourier transformed complex data set with the input image 510 which is itself, of course, a distribution of magnitude values. If the difference between the distribution of magnitude values 211A and the input image 210 is sufficiently small, the fourth processing block 259 may determine that the hologram 280A is acceptable. That is, if the difference between the distribution of magnitude values 211A and the input image 210 is sufficiently small, the fourth processing block 259 may determine that the hologram 280A is a sufficiently-accurate representative of the input image 210. In some embodiments, the distribution of phase values 213A of the inverse Fourier transformed complex data set is ignored for the purpose of the comparison. It will be appreciated that any number of different methods for comparing the distribution of magnitude values 211A and the input image 210 may be employed and the present disclosure is not limited to any particular method. In some embodiments, a mean square difference is calculated and if the mean square difference is less than a threshold value, the hologram 280A is deemed acceptable. If the fourth processing block 259 determines that the hologram 280A is not acceptable, a further iteration of the algorithm may be performed. However, this comparison step is not essential and in other embodiments, the number of iterations of the algorithm performed is predetermined or preset or user-defined.

Figure 2B represents a second iteration of the algorithm and any further iterations of the algorithm. The distribution of phase values 213A of the preceding iteration is fed-back through the processing blocks of the algorithm. The distribution of magnitude values 211A is rejected in favour of the distribution of magnitude values of the input image 210. In the first iteration, the data forming step 202A formed the first complex data set by combining distribution of magnitude values of the input image 210 with a random phase distribution 230. However, in the second and subsequent iterations, the data forming step 202B comprises forming a complex data set by combining (i) the distribution of phase values 213A from the previous iteration of the algorithm with (ii) the distribution of magnitude values of the input image 210.

The complex data set formed by the data forming step 202B of Figure 2B is then processed in the same way described with reference to Figure 2A to form second iteration hologram 280B. The explanation of the process is not therefore repeated here. The algorithm may stop when the second iteration hologram 280B has been calculated. However, any number of further iterations of the algorithm may be performed. It will be understood that the third processing block 256 is only required if the fourth processing block 259 is required or a further iteration is required. The output hologram 280B generally gets better with each iteration. However, in practice, a point is usually reached at which no measurable improvement is observed or the positive benefit of performing a further iteration is out-weighted by the negative effect of additional processing time. Hence, the algorithm is described as iterative and convergent.

Figure 2C represents an alternative embodiment of the second and subsequent iterations.

The distribution of phase values 213A of the preceding iteration is fed-back through the processing blocks of the algorithm. The distribution of magnitude values 211A is rejected in favour of an alternative distribution of magnitude values. In this alternative embodiment, the alternative distribution of magnitude values is derived from the distribution of magnitude values 211 of the previous iteration. Specifically, processing block 258 subtracts the distribution of magnitude values of the input image 210 from the distribution of magnitude values 211 of the previous iteration, scales that difference by a gain factor a and subtracts the scaled difference from the input image 210. This is expressed mathematically by the following equations, wherein the subscript text and numbers indicate the iteration number: k+1[x,Y] = P lexP(1 V, [u, v]) Y n[u,v]= ZI exp(r 71?"[x, y])} = T[x, -a(1?"[x, T[x, y]) where: F' is the inverse Fourier transform; F is the forward Fourier transform; R[x, y] is the complex data set output by the third processing block 256; T[x, y] is the input or target image; Z is the phase component; is the phase-only hologram 28013; ri is the new distribution of magnitude values 211B; and a is the gain factor.

The gain factor a may be fixed or variable. In some embodiments, the gain factor a is determined based on the size and rate of the incoming target image data. In some embodiments, the gain factor a is dependent on the iteration number. In some embodiments, the gain factor a is solely function of the iteration number.

The embodiment of Figure 2C is the same as that of Figure 2A and Figure 2B in all other respects. It may be said that the phase-only hologram 11J(u, v) comprises a phase distribution in the frequency or Fourier domain.

In some embodiments, the Fourier transform is performed using the spatial light modulator.

Specifically, the hologram data is combined with second data providing optical power. That is, the data written to the spatial light modulation comprises hologram data representing the object and lens data representative of a lens. When displayed on a spatial light modulator and illuminated with light, the lens data emulates a physical lens -that is, it brings light to a focus in the same way as the corresponding physical optic. The lens data therefore provides optical, or focusing, power. In these embodiments, the physical Fourier transform lens 120 of Figure 1 may be omitted. It is known how to calculate data representative of a lens. The data representative of a lens may be referred to as a software lens. For example, a phase-only lens may be formed by calculating the phase delay caused by each point of the lens owing to its refractive index and spatially-variant optical path length. For example, the optical path length at the centre of a convex lens is greater than the optical path length at the edges of the lens. An amplitude-only lens may be formed by a Fresnel zone plate. It is also known in the art of computer-generated holography how to combine data representative of a lens with a hologram so that a Fourier transform of the hologram can be performed without the need for a physical Fourier lens. In some embodiments, lensing data is combined with the hologram by simple addition such as simple vector addition. In some embodiments, a physical lens is used in conjunction with a software lens to perform the Fourier transform. Alternatively, in other embodiments, the Fourier transform lens is omitted altogether such that the holographic reconstruction takes place in the far-field. In further embodiments, the hologram may be combined in the same way with grating data -that is, data arranged to perform the function of a grating such as image steering. Again, it is known in the field how to calculate such data. For example, a phase-only grating may be formed by modelling the phase delay caused by each point on the surface of a blazed grating. An amplitude-only grating may be simply superimposed with an amplitude-only hologram to provide angular steering of the holographic reconstruction. The second data providing lensing and/or steering may be referred to as a light processing function or light processing pattern to distinguish from the hologram data which may be referred to as an image forming function or image forming pattern.

In some embodiments, the Fourier transform is performed jointly by a physical Fourier transform lens and a software lens. That is, some optical power which contributes to the Fourier transform is provided by a software lens and the rest of the optical power which contributes to the Fourier transform is provided by a physical optic or optics.

In some embodiments, there is provided a real-time engine arranged to receive image data and calculate holograms in real-time using the algorithm. In some embodiments, the image data is a video comprising a sequence of image frames. In other embodiments, the holograms are pre-calculated, stored in computer memory and recalled as needed for display on a SLM. That is, in some embodiments, there is provided a repository of predetermined holograms.

Embodiments relate to Fourier holography and Gerchberg-Saxton type algorithms by way of example only. The present disclosure is equally applicable to Fresnel holography and Fresnel holograms which may be calculated by a similar method. The present disclosure is also applicable to holograms calculated by other techniques such as those based on point cloud methods.

Light modulation A spatial light modulator may be used to display the diffractive pattern including the computer-generated hologram. If the hologram is a phase-only hologram, a spatial light modulator which modulates phase is required. If the hologram is a fully-complex hologram, a spatial light modulator which modulates phase and amplitude may be used or a first spatial light modulator which modulates phase and a second spatial light modulator which modulates amplitude may be used.

In some embodiments, the light-modulating elements (i.e. the pixels) of the spatial light modulator are cells containing liquid crystal. That is, in some embodiments, the spatial light modulator is a liquid crystal device in which the optically-active component is the liquid crystal. Each liquid crystal cell is configured to selectively-provide a plurality of light modulation levels. That is, each liquid crystal cell is configured at any one time to operate at one light modulation level selected from a plurality of possible light modulation levels. Each liquid crystal cell is dynamically-reconfigurable to a different light modulation level from the plurality of light modulation levels. In some embodiments, the spatial light modulator is a reflective liquid crystal on silicon (LCOS) spatial light modulator but the present disclosure is not restricted to this type of spatial light modulator.

A LCOS device provides a dense array of light modulating elements, or pixels, within a small aperture (e.g. a few centimetres in width). The pixels are typically approximately 10 microns or less which results in a diffraction angle of a few degrees meaning that the optical system can be compact. It is easier to adequately illuminate the small aperture of a LCOS SLM than it is the larger aperture of other liquid crystal devices. An LCOS device is typically reflective which means that the circuitry which drives the pixels of a LCOS SLM can be buried under the reflective surface. The results in a higher aperture ratio. In other words, the pixels are closely packed meaning there is very little dead space between the pixels. This is advantageous because it reduces the optical noise in the replay field. A LCOS SLM uses a silicon backplane which has the advantage that the pixels are optically flat. This is particularly important for a phase modulating device.

A suitable LCOS SLM is described below, by way of example only, with reference to Figure 3.

An LCOS device is formed using a single crystal silicon substrate 302. It has a 2D array of square planar aluminium electrodes 301, spaced apart by a gap 301a, arranged on the upper surface of the substrate. Each of the electrodes 301 can be addressed via circuitry 302a buried in the substrate 302. Each of the electrodes forms a respective planar mirror. An alignment layer 303 is disposed on the array of electrodes, and a liquid crystal layer 304 is disposed on the alignment layer 303. A second alignment layer 305 is disposed on the planar transparent layer 306, e.g. of glass. A single transparent electrode 307 e.g. of ITO is disposed between the transparent layer 306 and the second alignment layer 305.

Each of the square electrodes 301 defines, together with the overlying region of the transparent electrode 307 and the intervening liquid crystal material, a controllable phase-modulating element 308, often referred to as a pixel. The effective pixel area, or fill factor, is the percentage of the total pixel which is optically active, taking into account the space between pixels 301a. By control of the voltage applied to each electrode 301 with respect to the transparent electrode 307, the properties of the liquid crystal material of the respective phase modulating element may be varied, thereby to provide a variable delay to light incident thereon. The effect is to provide phase-only modulation to the wavefront, i.e. no amplitude effect occurs.

The described LCOS SLM outputs spatially modulated light in reflection. Reflective LCOS SLMs have the advantage that the signal lines, gate lines and transistors are below the mirrored surface, which results in high fill factors (typically greater than 90%) and high resolutions. Another advantage of using a reflective LCOS spatial light modulator is that the liquid crystal layer can be half the thickness than would be necessary if a transmissive device were used. This greatly improves the switching speed of the liquid crystal (a key advantage for the projection of moving video images). However, the teachings of the present disclosure may equally be implemented using a transmissive LCOS SLM.

Digital drive Broadly, two types of pixel drive in LCOS have been explored: 1/ analogue and 2/ digital. In overview, there is disclosed in the following an improved method of pulse width modulation, "PWM", digital drive that provides improved optical response. Embodiments relate to digital modulation. Some embodiments relate to the base concepts of gated clocks and variable pulse density.

Simple PWM Figures 4A and 4B represent a simple PWM modulation scheme. In this scheme, the width t of a single pulse is linearly varied within the PWM repetition time T and directly proportional to the value of DC required, where a code of all D's indicates OV DC with no positive going pulse generated, and a code of all l's indicates the full-scale voltage deflection and a pulse lasting the entirety of T. Figure 4A shows a first example comprising a first pulse 401A having a first width r1 giving rise to a first equivalent DC voltage 403k Figure 4B shows a second example comprising a second pulse 401B having a second width t2 giving rise to a second equivalent DC voltage 403B.

The value of r is modified by the digital code and quantised accordingly, with the value of T1 remaining constant. Each specific ratio oft and T1 will have a corresponding spectrum and an unwanted component whose frequency is inversely proportional to the PWM repetition time T1.

Gated clock PWM In an alternative scheme, gated clock PWM modulation is employed. In this scheme, a number of short clock pulses are output, the number of which are directly proportional to the required DC level. An example of gated clock PWM is shown in Figure 5A. In this scheme, utilising a 50:50 mark-space ratio of the pulses within the time period t, it can be seen that the duration of T will be twice that of the simple PWM scheme shown in Figure 4A.

The equivalent / output DC value is dependent on the ratio of T T and the frequency of the spectral component closest to that of the DC component related to the absolute value of the PWM repetition time T1.

Spread spectrum An alternative approach to increasing the clock frequency to shorten T, is to scale T and r for each new complete T1 period. If this scaling to the T and r is performed in a random/pseudo-random fashion, the resulting spectrum shows a spreading across frequency of the energy in the spur at the frequency 1/T and higher order terms, however, since the ratio of r / T is preserved, no change in output DC value is apparent.

Variable pulse density In addition to the PWM schemes described above, another approach to a digit pixel drive scheme uses a variable pulse density. Figure 5B shows a pulse density scheme. In this scheme, the energy in the PWM pulse is distributed along the entire period of T which is in contrast to the gated clock scheme (Figure 5A) where the short pulses are concentrated within the variable timer. The variable pulse density scheme has the same number pulses as in the gated clock scheme for any one digital value, however, being distributed over T the resulting ripple in the filtered signal can be significantly reduced.

Combining binary pulse trains of different pulse density There is disclosed herein a scheme in which a plurality of different density pulse trains are selectively combined to represent the digital drive code.

Each binary pulse train comprises pulses of equivalent width but different repetition times.

This produces spectral components for each pulse density stream weighted by the same Sinc function but with spectrally separated components. The total spectrum could be established for each required binary code by superposition.

Figure 6A shows a 4-line binary pulse density scheme. This may therefore be described as a 4-bit scheme. However, in other embodiments described below with reference to Figure 11, this may be part of a 5-bit scheme in which the fifth bit is used to determine or "switch" the logic for combining the individual pulse trains. Figure 6B shows the trace being the combination of all the individual pulse density lines. When all bits are combined -i.e. digital code 1111 -there are fifteen total pulses and within period T1 which is one pulse short of half full-scale.

In more detail, Figure 6A shows four pulse trains b[0] to b[3]. The zeroth pulse train b[0] corresponds to the least significant bit of a 4-bit scheme. The third pulse train b[3] corresponds to the most significant bit of the 4-bit scheme. The pulse frequency increases with bit significance. That is, the zeroth pulse train b[0] has the lowest pulse frequency and the third pulse train b[3] has the highest pulse frequency. In this embodiment, by way of example only, the frequency increases in multiples of two with each bit. The first pulse train b[1] has twice the pulse frequency of the zeroth pulse train b[0]. The second pulse train b[2] has twice the pulse frequency of the first pulse train b[1]. The third pulse train b[3] has twice the pulse frequency of the second pulse train b[2]. However, the present disclosure is not limited to a multiplier of two and other multipliers (such as 2", wherein n is any integer)

are suitable.

The zeroth pulse train may correspond to the least significant bit and the third pulse train may correspond to the most significant bit in a 4-bit (grey level) scheme. That is, 4-bits are used to represent each pixel value e.g. grey level. A notable feature of some embodiments is that the pulses of the plurality of pulse trains are non-overlapping. The pulse trains can therefore be selectively combined (e.g. summed to a base line or subtracted from a base line) to form a set of unique pulse patterns. Each pulse pattern is unique and unambiguous. That is, each pulse pattern cannot be formed from a different combination of pulse trains.

In this embodiment, the pulse trains are selectively combined by addition or superposition.

Figure 6B shows the combination of all pulse lines which corresponds to a pixel value of 1111. However, the pulse trains are gated at the pixel level in accordance with a respective pixel value (e.g. grey level) stored at each pixel to represent all binary numbers from 0000 to 1111.

Each pulse train is transmitted by a respective pulse line from a pulse generator to each pixel. Each pixel comprises memory for storing an n-bit number, wherein n is the number of lines (or one more than the number of lines -in accordance with further embodiments described below). Each pixel comprises a respective number of gates. Each bit of the n-bit number corresponds to a respective (pixel) gate. In this embodiment, there are therefore four gates per pixel. More generally, the number of gates per pixel is equal to the number of pulse trains that are combined.

Figure 7 shows the pixel gates in more detail. Figure 7 shows a pulse generator 700 and four pulse lines each transmitting a respective pulse train b[0] to b[3]. The zeroth pulse train b[0] corresponds to the least significant bit "L" of the n-bit scheme and the third pulse train b[3] corresponds to the most significant bit "M". Each pulse line is connected to each pixel.

Figure 7 shows three pixels 711, 712 and 71N by way of example. Each pixel comprises four gates. A first pixel 711 has memory storing the binary pixel value 1010. Each gate is operated in accordance with one bit value of the pixel value 1010. The zeroth pulse train b[0] is not transmitted by the gate because the least significant bit of the first pixel 711 value is 0. Likewise, the second pulse train b[2] is not transmitted by the gate because of the second zero in the pixel value 1010. The first pulse train and third pulse train are transmitted in accordance with the 1s of 1010. The first pulse train b[1] and third pulse train b[3] are combined (by a pulse combiner not shown) to form a combined pulse pattern that uniquely represents 1010. In Figure 7, a second pixel 712 has the value 1111 and therefore all four pulse trains are transmitted by the (second pixel) gates and combined by a pulse combiner (not shown). An nth pixel 71N has the value 0011 and so therefore only the zeroth pulse train b[0] and first pulse train b[1] are transmitted by the (nth pixel) gates and combined by a pulse combiner (not shown).

Figure 8A shows the pulse pattern corresponding to the first pixel 711 of Figure 7 formed by the summation of the first pulse train b[1] and the third pulse train b[3] in accordance with the binary number 1010. Figure 8B the pulse pattern corresponding to the second pixel 712 of Figure 7 formed by the summation of all four pulse trains b[0] to b[3] in accordance with the binary number 1111. Figure 8C shows the pulse pattern corresponding to the nth pixel 71N of Figure 7 formed by the summation of the zeroth pulse train b[0] and the first pulse train b[1] in accordance with the binary number 0011.

Implementation with static clock or spread spectrum clock The scheme of Figures 6 to 8 may be implemented with a static clock or a spread-spectrum clock as shown in Figures 9 in which the horizontal axis is time. By way of introduction, Figure 9A shows a simple PWM scheme with a static clock and Figure 9B shows a simple PWM scheme with a spread spectrum clock. In accordance with the present disclosure, Figure 9C shows a gated clock scheme with a static clock and Figure 9D shows a gated clock PWM scheme with a spread spectrum clock. Figures 9 show how the schemes of Figures 6 to 8 are equally applicable to a static clock or a spread spectrum clock.

Ripple It was found that charging a pixel over 2ms with five different PWM methods shows for low, medium and high values of phase different there is a visible ripple on the applied voltage.

Zooming in on the mid grey line shows that simple basic PWM and basic PWM with spread spectrum show increased ripple (triangular waveform). Gated clock and pulse density schemes show very flat response.

Figures 10 shows a magnified (zoomed-in) view for a mid-scale code (grey level) for different drive schemes. Lines 1001 and 1002 corresponds to a basic PWM scheme with and without spread spectrum. The ripple shown has an adverse effect on the performance of the device. Lines 1003 and 1004 correspond to the gated clock schemes and the pulse density scheme and how a similar low ripple due to the nature of spreading pulses across the period Tl.

Inversion / operating mode 1 and 2 In some embodiments, an additional (pixel value) bit is used to determine how to combine the pulse trains. In some embodiments, the value of the additional bit is used to select one mode of combination from two possible modes of combination. In some embodiments, the value of the additional bit is used to switch (e.g. invert) the mode of combination. In accordance with the embodiments of Figures 6 and 7, the additional bit would be a fifth bit. The pixel values (e.g. grey levels) are therefore represented by a 5-bit (binary) number i.e. zero (00000) to 31 (11111). That is, there are 32 allowable grey levels. The additional (e.g. inverter) bit may be the most significant bit of the 5-bit number.

By way of further example, Figure 11 shows a 9-bit scheme (512 levels) in which a value on Bus 8 is used to determine how the pulse trains of Bus 0 to Bus 7 are combined in accordance with the pixel value. A further advancement is described below with reference to Figures 12 and 13. Figures 12 and 13 corresponds to the section 1150 of Figure 11 and therefore all pulses are not therefore visible.

For pixel values below 256 (case 1 / Figure 12), each pulse density bus line is added to the output if the corresponding bit in memory is 1. In Figure 12, all bits are 1 except for bit 1 which is 0. This bit does not get gated to the pulse density output stream and there is therefore a gap 1220 in the output pulse pattern.

For all values 256 and above (case 2 / Figure 13), the output stream is high in the absence of a gated pules. The SRAM gating control is also inverted. A 0 SRAM bit value results in the bus line driving the Output low for the duration of its pulses. A 1 SRAM Bit results in the bus line leaving the Output bit stream high for its duration. For an SRAM Value of 512 (binary, 111111111), the output would be constant high as there are no lines driving the bus low.

The low / gap 1220 of Figure 12 is therefore filled by a high / pulse 1320 in Figure 13.

Notably, the scheme requires only 8 lines and 9 (e.g. SRAM) bits (memory in pixel) to operate. That is, for a n-bit scheme, only (n-1) pulse trains are required. This is a significant technical advantage of these embodiments. In short, the most significant bit is used to determine whether to combine the pulse trains by addition (to a base line of zero) or subtraction (from a baseline of 1). It may be said that the device has a first operating mode and a second operating mode that determines how the pulse trains are combined in accordance with (e.g. based on) the binary grey level.

Missing pulse One issue is that the scheme always results in 11_513 (least significant bit) penultimate pulse missing in the output stream. Figure 8B shows this missing pulse 850. In an embodiment, a 9th Bus line is added which has just the single pulse needed to fill in the gap.

However, in a more advanced embodiment, the number of bus lines which need to be distributed is reduced. In this embodiment, simple logic encodes a value on the bus lines. Two or more bus lines could have encoded values. For example, if Bus line 0 and 1 are both set to 1, then this is interpreted as bus no. 9 signal.

This scheme could be extended further at the cost of some decoding logic under the pixel 4 bus lines could have 16 bits of information. A trade-off between silicon area, power and speed would need to be made in the silicon design.

Additional features In some embodiments, when the improved spatial light modulator is comprised within an optical arrangement that includes a light source, the light source is a laser such as a laser 20 diode.

The methods and processes described herein may be embodied on a computer-readable medium. The term "computer-readable medium" includes a medium arranged to store data temporarily or permanently such as random-access memory (RAM), read-only memory (ROM), buffer memory, flash memory, and cache memory. The term "computer-readable medium" shall also be taken to include any medium, or combination of multiple media, that is capable of storing instructions for execution by a machine such that the instructions, when executed by one or more processors, cause the machine to perform any one or more of the methodologies described herein, in whole or in part.

The term "computer-readable medium" also encompasses cloud-based storage systems. The term "computer-readable medium" includes, but is not limited to, one or more tangible and non-transitory data repositories (e.g., data volumes) in the example form of a solid-state memory chip, an optical disc, a magnetic disc, or any suitable combination thereof. In some example embodiments, the instructions for execution may be communicated by a carrier medium. Examples of such a carrier medium include a transient medium (e.g., a propagating signal that communicates instructions).

It will be apparent to those skilled in the art that various modifications and variations can be made without departing from the scope of the appended claims. The present disclosure covers all modifications and variations within the scope of the appended claims and their equivalents.

Claims (17)

1. CLAIMS1. A display device comprising: a pulse generator arranged to generate a plurality of pulse trains, wherein each pulse train has a respective pulse frequency; a plurality of pulse lines, wherein each pulse line is arranged to transmit a respective pulse train; a plurality of pixels, wherein each pixel comprises: memory for storing an n-bit number; a plurality of gates wherein each gate is connected to a respective pulse line and each gate corresponds to a respective bit of the n-bit number; and a pulse combiner arranged to combine the outputs of the gates to produce a combined pulse train, wherein the outputs of the gates are interleaved in time such that the pulse trains of the different lines are non-overlapping, wherein the frequency of each pulse train is a function of the significance of the bit of the n-bit number.
2. 2. A display device as claimed in claim 1 wherein the more significant the bit of the n-bit number, the higher the frequency of the pulse train.
3. 3. A display device as claimed in any preceding claim wherein the frequency of the pulse train is a linear function of the significance of the bit of the n-bit number.
4. 4. A display device as claimed in any preceding claim wherein the pulse generator is arranged such that all pulses of the plurality of pulse lines are non-overlapping.
5. 5. A display device as claimed in any preceding claim, wherein a first subset of drive levels is formed by adding the output of the gates to a zero baseline to produce the combined pulse train and the remaining drive levels are formed by subtracting the output of the gates from a positive, non-zero baseline to produce the combined pulse train.
6. 6. A display device as claimed in claim 5 wherein one bit of the n-bit number is used to determine whether the n-bit number is part of the first subset of drive levels or the remaining drive levels.
7. 7. A display device as claimed in any preceding claim wherein the duration of every pulse of every pulse train is substantially equal.
8. 8. A display device as claimed in any preceding claim wherein each gate of a pixel is independently operable in an open or closed state in accordance with the bit value of the corresponding bit of the n-bit number stored in the memory.
9. 9. A display device as claimed in claim 8 wherein each gate is independently operable in accordance with the respective bit value for a time period, t1, necessary to drive the pixel.
10. 10. A display device as claimed in claim 9 wherein the pulse generator and a first gate, G1, corresponding to the least significant bit are coordinated such that only one pulse is transmitted by the first gate, G1, within the time period, t1.
11. 11. A display device as claimed in claim 10 wherein the only one pulse transmitted by the first gate, G1, is substantially centred within the time period, t1.
12. 12. A display device as claimed in any preceding claim wherein the pulse generator and gates, G(1) to G(n), are configured such that the number of pulses occurring within the time period, t1, is equal to 2"1.
13. 13. A display device as claimed in any preceding claim wherein the pattern of pulses of each individual pulse line is symmetric about the centre of the time period, t1.
14. 14. A display device as claimed in any preceding claim wherein the pulses of each pulse train are evenly distributed within the time period, t1.
15. 15. A display device as claimed in any preceding claim wherein the combined pulse train is a digital representation of an n-bit pixel value.
16. 16. A display device as claimed in any preceding claim further comprising a clock, wherein the clock is a static clock or a spread spectrum clock.
17. 17. A method of driving pixels of a display device using a pulse modulation scheme, the method comprising: generating a plurality of pulse trains, wherein each pulse train has a respective pulse 10 frequency; storing an n-bit number at each pixel of a plurality of pixels, delivering each pulse train of the plurality of pulse trains to a respective gate of a plurality of gates of each pixel, wherein each gate corresponds to a respective bit of the n-bit number; and combining the outputs of the dates to produce a combined pulse train, wherein the outputs of the gates are interleaved in time such that the pulse trains of the different lines are non-overlapping, wherein the frequency of the pulse train is a function of the significance of the bit of the n-bit number.