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GB2614071B - Cache systems - Google Patents

Cache systems Download PDF

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Publication number
GB2614071B
GB2614071B GB2118626.7A GB202118626A GB2614071B GB 2614071 B GB2614071 B GB 2614071B GB 202118626 A GB202118626 A GB 202118626A GB 2614071 B GB2614071 B GB 2614071B
Authority
GB
United Kingdom
Prior art keywords
cache systems
cache
systems
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
GB2118626.7A
Other versions
GB2614071A (en
Inventor
Henrik Uhrenholt Olof
Fielding Edvard
Henrik Jahren Ole
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
ARM Ltd
Original Assignee
ARM Ltd
Advanced Risc Machines Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by ARM Ltd, Advanced Risc Machines Ltd filed Critical ARM Ltd
Priority to GB2118626.7A priority Critical patent/GB2614071B/en
Priority to CN202211457453.8A priority patent/CN116303134A/en
Priority to US18/064,044 priority patent/US12135651B2/en
Priority to US18/064,020 priority patent/US12314182B2/en
Priority to KR1020220176018A priority patent/KR20230094998A/en
Priority to US18/067,180 priority patent/US12443538B2/en
Publication of GB2614071A publication Critical patent/GB2614071A/en
Application granted granted Critical
Publication of GB2614071B publication Critical patent/GB2614071B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0815—Cache consistency protocols
    • G06F12/0817—Cache consistency protocols using directory methods
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0811—Multiuser, multiprocessor or multiprocessing cache systems with multilevel cache hierarchies
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0815—Cache consistency protocols
    • G06F12/0817—Cache consistency protocols using directory methods
    • G06F12/0826—Limited pointers directories; State-only directories without pointers
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0877—Cache access modes
    • G06F12/0886—Variable-length word access
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
    • G06T1/00—General purpose image data processing
    • G06T1/60—Memory management
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
    • G06T15/00—3D [Three Dimensional] image rendering
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/10—Providing a specific technical effect
    • G06F2212/1016—Performance improvement
    • G06F2212/1024—Latency reduction
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/30—Providing cache or TLB in specific location of a processing system
    • G06F2212/302—In image processor or graphics adapter
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/40—Specific encoding of data in memory or cache
    • G06F2212/401—Compressed data
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/45—Caching of specific data in cache memory
    • G06F2212/455—Image or video data

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • Computer Graphics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
GB2118626.7A 2021-12-21 2021-12-21 Cache systems Active GB2614071B (en)

Priority Applications (6)

Application Number Priority Date Filing Date Title
GB2118626.7A GB2614071B (en) 2021-12-21 2021-12-21 Cache systems
CN202211457453.8A CN116303134A (en) 2021-12-21 2022-11-21 cache system
US18/064,044 US12135651B2 (en) 2021-12-21 2022-12-09 Cache systems with different address domains
US18/064,020 US12314182B2 (en) 2021-12-21 2022-12-09 Updating related data in multi-cache systems
KR1020220176018A KR20230094998A (en) 2021-12-21 2022-12-15 Cache systems
US18/067,180 US12443538B2 (en) 2021-12-21 2022-12-16 Cache systems

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
GB2118626.7A GB2614071B (en) 2021-12-21 2021-12-21 Cache systems

Publications (2)

Publication Number Publication Date
GB2614071A GB2614071A (en) 2023-06-28
GB2614071B true GB2614071B (en) 2024-07-17

Family

ID=79601957

Family Applications (1)

Application Number Title Priority Date Filing Date
GB2118626.7A Active GB2614071B (en) 2021-12-21 2021-12-21 Cache systems

Country Status (1)

Country Link
GB (1) GB2614071B (en)

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20160154739A1 (en) * 2014-12-01 2016-06-02 Samsung Electronics Co., Ltd. Display driving apparatus and cache managing method thereof
EP3486784A1 (en) * 2017-11-20 2019-05-22 Samsung Electronics Co., Ltd. Systems and methods for efficient compressed cache line storage and handling
US20200159664A1 (en) * 2018-11-19 2020-05-21 Ati Technologies Ulc Low latency dirty ram for cache invalidation speed improvement
US20200210343A1 (en) * 2018-12-26 2020-07-02 Advanced Micro Devices, Inc. Compressing Data for Storage in Cache Memories in a Hierarchy of Cache Memories
US20210011646A1 (en) * 2019-07-12 2021-01-14 Arm Limited Methods and apparatus for storing data in memory in data processing systems

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8990518B2 (en) 2011-08-04 2015-03-24 Arm Limited Methods of and apparatus for storing data in memory in data processing systems
US9116790B2 (en) 2011-08-04 2015-08-25 Arm Limited Methods of and apparatus for storing data in memory in data processing systems
GB2579568B (en) 2018-12-03 2022-04-27 Advanced Risc Mach Ltd Encoding data arrays

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20160154739A1 (en) * 2014-12-01 2016-06-02 Samsung Electronics Co., Ltd. Display driving apparatus and cache managing method thereof
EP3486784A1 (en) * 2017-11-20 2019-05-22 Samsung Electronics Co., Ltd. Systems and methods for efficient compressed cache line storage and handling
US20200159664A1 (en) * 2018-11-19 2020-05-21 Ati Technologies Ulc Low latency dirty ram for cache invalidation speed improvement
US20200210343A1 (en) * 2018-12-26 2020-07-02 Advanced Micro Devices, Inc. Compressing Data for Storage in Cache Memories in a Hierarchy of Cache Memories
US20210011646A1 (en) * 2019-07-12 2021-01-14 Arm Limited Methods and apparatus for storing data in memory in data processing systems

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
ACM SIGARCH COMPTER ARCHITECTURE NEWS, vol 32, 2004, ALAA R ALAMELDEEN ET AL, "Adaptive Cache Compression for High-Performance Processors", page 212 *
ACM TRANSACTIONS ON DESIGN AUTOMATION OF ELECTRONIC SYSTEMS, vol 22, 2017, JAEHYUN PARK ET AL, "HoPE: Hot-Cacheline Prediction for Dynamic Early Decompression in Compressed LLCs", pages 1-25 *

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Publication number Publication date
GB2614071A (en) 2023-06-28

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