GB2604121A - A single ended memory sensing scheme - Google Patents

Abstract

Memory unit 100 & method of sensing data in a single ended read port memory cell, comprising read bit line 20, common (global) bit line node 30, output circuit 70 having read sense node 50, a single ended memory cell 10 to include a buffered read port 12 and cell output node 14 (e.g SRAM cell fig 1) connected to read bitline 20; an NMOS bitline select transistor 22 having first point 24 connected to read bit line, and second point 26 connected to common bit line, the NMOS select transistor having voltage threshold VVT1 whereby conduction between first and second connection points 24, 26 occurs; first precharge circuit (Mpcb PMOS 40) to charge read bit line via NMOS bitline select transistor by connection of power supply line VDD to common bitline node; a second precharge circuit 60 (Mpcs PMOS) pre-charges the output circuit 70 (read sense node), by connecting supply line VDD to the read sense node 50; and an NMOS cascode barrier transistor 80 having first connection point 82 at common bit line node & a second connection point 84 at read sense node, and which has a conduction voltage threshold VVT2; wherein the voltage threshold value VVT2 of the NMOS cascode barrier transistor 80 is greater than the Voltage Threshold value VVT1 of the NMOS bit line select transistor 22 (e.g by at least 60mV). The cascoded barrier (buffer) transistor may either be a high voltage threshold HVT NMOSFET device or may have a gate voltage potential lower than the supply line (Vg <VDD). The select transistor and cascode barrier transistors cooperate to limit the maximum voltage on read bitline, but maximize voltage swing on read sense node. The output circuit may comprise a gated latch.

Description

A SINGLE ENDED MEMORY SENSING SCHEME

FIELD

The present invention relates to a memory unit for providing digital data storage. More particularly, the present invention relates to an apparatus and method for providing a sensing scheme in a memory unit, employing storage cells with single-ended read ports.

BACKGROUND

Data storage is an essential requirement for virtually all modern digital electronic systems. Memory units of various types comprise a major part of that function, being relatively easy to integrate into a semiconductor device together with large amounts of logic. With the advent of deep sub-micron (DSM) geometry silicon processing, the task of implementing reliable storage whilst simultaneously maintaining low power consumption becomes increasingly problematic. With the proliferation of battery-powered electronic gadgets requiring progressively larger memories conversely the requirement for low power consumption becomes more important. In addition to being sensitive to power consumption battery-powered devices present the additional issue of a variable power supply voltage. The challenge being to maintain stable function at lower and lower voltages.

Buffered Read Port Memory Cells are known. An example of the relevant type of storage cell is an 8 transistor memory cell incorporating a buffered read port shown in Figure 1, wherein the read port comprises two series NMOS transistors MRB1 and MRB2. MRB1 functions as a data dependent pull down whose conductive state is determined by the voltage on data node qb, which defines the data state of the memory cell as 0 or 1. When MRB2 is turned ON by driving the read word line signal RWL high, if data node qb is high the cell will form a conductive path from the read bit line RBL to the zero volt rail VSS or ground, whereas if the data node qb is low transistor MRB1 will be OFF thereby preventing conduction from RBL to VSS. Where high and low refer to the logic value of the voltage of a component. High normally refers to the supply voltage Vdd and low to the lowest voltage seen on a circuit Vss, in this case ground or OV.

The scheme of the current invention describes circuitry to efficiently discriminate between when the data node qb is high or low or when the memory cell has a data value of 0 or 1, in order to determine the value of stored data.

Conventionally the cell of Figure 1 is deployed in an array in which the operative read bit line RBL is precharged to VDD using a PMOS transistor whilst the read word line RWL is held low to ensure MRB2 is turned off. To perform a sense operation, the precharge is then turned off and RWL driven high whereupon the voltage on RBL will either discharge towards zero volts (due to the voltage on qb being high and MRB1 turned ON) or alternatively will stay high around the VDD level if MRB1 is turned OFF (due to the voltage on qb being low). After waiting sufficiently long the voltage on RBL will either be notionally high (-VDD) or notionally low (-VSS) which is readily compatible with subsequent digital logic circuitry to detect the memory bit cell's state.

Whilst this approach has the advantage of simplicity, it is inefficient in energy since the bit line undergoes a full rail-to-rail swing from Vss to Vdd and from Vdd to Vss, and is also slow, due to the need for the read bit line to swing essentially the full voltage of the rail between Vss and Vdd and from Vdd to Vss.

One approach to alleviate these limitations is to use a current-mode single-ended sense amplifier, a conventional design of such is shown in Figure 2. In this illustration, devices M3, M4, M5 and INV1 form a precharge circuit to drive the bit line selected by transistor M7 to a voltage level at which the bit cell state will be sensed. When the bit line voltage level has had time to settle, the precharge circuit is turned off, and the current drawn from the cell is mirrored via devices M1 and M2 whereupon it is compared with a reference current and amplified by a pair of inverter stages to provide a full rail output.

The current-mode sense amp scheme does reduce the voltage swing on the bit line (thus saving some power) but the added complexity and the need for a current reference negates that saving. In addition, the use of the current mirror limits its ability to operate at reduced power supply voltage levels as the current mirror requires substantial headroom or difference between the working voltage and the supply voltage Vdd. Therefore, the ability of the current-mode sense amp scheme to save power is limited.

Accordingly, the current invention pertains to a means for implementing read circuitry for memory designs comprising storage cells with buffered read ports. The scheme offers, improved simplicity, faster read speeds, lower power consumption and in particular stable operation at a lower voltage compared with previous approaches disclosed in the prior art.

The scheme of the current invention is hereafter referred to as the "Cascode Barrier Sense" scheme, CBS.

SUMMARY OF INVENTION

Aspects of the current embodiment seek to provide a memory unit including a scheme for efficient and stable sense operations at a variety of supply voltage levels.

According to a first aspect, there is provided a memory unit comprising: a read bit line; a common bit line node; an output circuit having a read sense node; a voltage input line for supplying a voltage (Vdd) to the memory unit from an external power supply; a single ended memory cell, including a buffered read port and a cell output node connected to the read bitline; an NMOS bitline select transistor, the NMOS bitline select transistor having a first connection point connected to the read bit line, a second connection point connected to the common bit line node, a gate and a voltage threshold value (Vv-ri) at which the NMOS transistor will conduct between the first and second connection points; a first precharge circuit operable to charge the read bit line via the NMOS bitline select transistor, the first precharge circuit having an input connected to the voltage input line and an output connected to the common read bitline node; a second precharge circuit, operable to precharge the output circuit, the second precharge circuit having an input connected to the voltage input line and an output connected to the read sense node; An NMOS barrier transistor having a first connection point connected to the common bit line node, a second connection point connected to the read sense node and a Voltage Threshold value (Vv-12) at which the NMOS transistor will conduct between the first and second connection points; wherein the voltage threshold value (Vv-r2) of the NMOS barrier transistor is greater than the Voltage Threshold value (Vv-ri) of the NMOS bit line select transistor.

Preferably, the NMOS buffer transistor is a High Voltage Threshold (HVT) NMOS transistor.

Preferably, wherein the first precharge circuit and the second precharge circuit are operable under a common precharge signal to precharge the read bitline and the output circuit respectively.

Preferably, the first precharge circuit and the second precharge circuit each include a PMOS transistor operable to connect the first bitline node and the second read sense node to the voltage input line.

Preferably, the memory unit further includes a plurality of single ended memory cells connected to the read bit line.

Preferably, the memory unit further includes a plurality of read bit lines each connected to a plurality of single ended memory cells. Each bit line may include an NMOS bitline selection transistor and a mux controller operably connected to the gates of the NMOS bit line select transistors. Preferably, the plurality of NMOS bit line selection transistors are operable to connect one of the plurality of read bit lines to the first bitline node on receipt of a signal from the mux controller.

Preferably, the output circuit comprises a gated latch.

Preferably, the gated latch comprises a plurality of NOR gates and an inverter.

Preferably, the NMOS barrier transistor has a Voltage Threshold value at least 60mV higher than the NMOS bitline select transistor.

Preferably, the single ended memory cell comprises a memory node, a NMOS memory transistor having a first connection point connected to ground a second connection point and gate connected to the memory node; a NMOS buffer transistor having a first connection point connected to the second connection point of the memory transistor, a second connection point connected to the memory cell node and a gate connected to a read word line. The NMOS memory transistor may be operable to conduct between the first connection point and the second connection point depending on the voltage of the memory node, the NMOS buffer transistor may be operable to connect the memory NMOS transistor to the cell output node depending on the read wordline voltage of the read wordline.

According to a second aspect of the current invention a method for reading a data value stored in a single ended memory cell, that is part of a memory unit is provided.

The method comprising a first bit line select NMOS transistor selecting a read bit line in response to a read bit line signal; precharging the read bit line using a first precharge circuit via the bit line select NMOS transistor; precharging a read sense node using a second precharge circuit; after precharge is complete maintaining a voltage difference between the read sense node and the read bit line across an NMOS buffer transistor having a higher Voltage Threshold value Vvr2 than the voltage threshold value Vv-i of the NMOS bit line select transistor; thereafter connecting the memory cell to the read bit line 20 in response to a read wordline signal, and the memory cell either maintaining the precharge voltage in the read bit line and the output circuit or discharging the read bit line and the output circuit to ground depending on the data value of the memory cell.

Preferably, the memory unit of the method is the memory unit described in the first aspect Preferably, the read sense node is charged to a voltage Vdd supplied by an external power supply and the read bit line is precharge to Vdd-Vv-ri, wherein Vvri is the threshold voltage value at which the NMOS bitline transistor will conduct.

Preferably, if the data value is 1 the voltage in a memory node applied to a gate of the memory NMOS transistor is low and the read bit line is maintained at the precharge voltage, and if the data value is 0, the voltage in the memory node applied to a gate of the memory NMOS transistor is high causing the Memory NMOS transistor to connect the read bit line to ground causing it to discharge.

BRIEF DESCRIPTION OF DRAWINGS

Embodiments will now be described, by way of example only and with reference to the accompanying drawings having like-reference numerals, in which: Figure 1 shows a known 8 transistor memory unit incorporating a buffered read port or the prior art; Figure 2 shows a known single ended, current mode, sense amplifier of the prior art; Figure 3 shows a schematic view of a memory unit according to the cascode barrier sense scheme of the current invention; Figure 4 shows a suitable gated latch circuit for use in a memory unit of the current invention; Figure 5 shows a waveform diagram including the voltage levels for the inputs, output, and nodes of a cascode barrier sense memory unit over time when reading a memory cell with a data value of 1; and Figure 6 shows a waveform diagram including the voltage levels for the inputs, output, and nodes of a cascode barrier sense memory unit over time when reading a memory cell with a data value of 0.

SPECIFIC DESCRIPTION

Referring to Figure 3, a preferred embodiment will now be described.

The memory unit 100 includes read precharge circuitry 40, 60, sense amp circuitry 2, one or more memory cells 10 connected to one or more read bit lines 20 and a voltage input line 8 connected to an external power supply 1 for supplying a voltage Vdd to the memory unit.

Each read bit line 20 includes an NMOS bit line select transistor 22 for connecting the bit line 20 to a common bit line node 30. The NMOS bit line select transistor 22 includes a first connection point 24 connected to the bit line 20, a second connection point 26 connected to a common bit line node 30 and a gate 28 and is operable to connect the first and second connection points 22, 24 depending on a read bit line signal 200 received at the gate 28. The gate 28 of the NMOS bit line transistor 22 may be connected to a bit line controller 90 or in the case of a plurality of read bit lines 20 a multiplex controller 90 from which bit line signal 200 is received. The NMOS bit line select transistor 22 has a voltage threshold value Vvm at which the NMOS transistor will conduct between the first and second connection points 24, 26.

Each single ended memory cell 10, has a buffered read port 12, a memory node 17, a data value dictated by the voltage of said memory node 17 and is connected to the read bit line at a memory cell output node 14 and to ground 15. Each memory cell 10 further includes a NMOS memory transistor 16 and a NMOS buffer transistor 18 having respective first connection points 16a, 18a, second connection points 16b, 18b, and gates 16c, 18c. The first connection point 16a of the NMOS memory transistor 16 connected to ground 15, the second connection point 16b of the NMOS memory transistor 16 may be connected to the first connection point 18a of the NMOS buffer transistor 18 and the gate 16c connected to the memory node 17. The second connection point 18b of the NMOS buffer transistor may be connected to the memory cell node 14 and the gate 18c may be connected to a read word line 19. The buffer NMOS transistor 18 is operable to connect the memory cell 10 to its respective bit line 20 on receipt of a read word line signal 220, a voltage on the read word line 19. The memory NMOS transistor 16 is operable to conduct between the first connection point 16a and the second connection point 16b depending on the voltage of the memory node 17. The buffer NMOS transistor 18 may be operable to connect the memory NMOS transistor 16 to the cell output node 14 depending on the read wordline voltage 220 of the read wordline 19.

The sense amp circuitry 2 includes an NMOS barrier transistor 80 and an output circuit 70 that includes a read sense node 50, and a gated latch circuit 72. Any gated latch circuit 72 will be effective in the current invention but a preferable arrangement includes a plurality of NOR gates 74 and an inverter 76 as shown in figure 4. An inverter is also known as a NOT gate.

The NMOS barrier transistor 80 has a first connection 82 and a second connection point 84 and a gate 86. The first connection 82 is connected to the common bit line node 30 and the second connection point 84 is connected to the read sense node 50. The NMOS barrier transistor is operable to connect the first connection point 82 with the second connection point 84 dependent on a Voltage Threshold value Vv-r2.

The threshold voltages Vv-r1 of the NMOS bit line select transistors 22 and VvT2 of the NMOS barrier transistor 80, together Vv-r, govern when each NMOS transistor will conduct between its first connection point 24, 82 and its second connection point 26, 84. The threshold voltage Vv-r is the excess voltage above the lower of the two channels connected to the first and second connection points and the supply voltage Vdd, needed to establish a conducting path through the respective NMOS device. The lower of the two channels may be the first connection point 24, 82. Thus when the lower of the two channels increases to approach Vdd-Vv-r the respective NMOS transistor will cease to conduct. Conversely said NMOS transistor will conduct more as the difference between the reference voltage Vdd and the voltage seen by the lower of the two channels increases beyond Vv-r. The point of conduction is more gradual than an abrupt threshold implies. Note the read bit line voltage (rbl) shown in the graphs of figures 5 and 6. As the read bit line 20 is charged via the NMOS bit line select transistor 22 during precharge the rate of increase of rbl voltage decreases as the voltage approaches Vdd-Vv-ri shown by the line VDD-Vtn on the graph.

In the CBS the voltage threshold value Vv-r2 of the NMOS barrier Transistor 80 must be greater than the voltage threshold value Vvri of the NMOS bit line select transistor 22. Preferably, due to the gradual threshold described above VvT2 is at least 60mV greater than VvTi and most preferably VvT2 is at least 80mV greater than VvTi. To provide this higher voltage threshold the NMOS barrier transistor 80 may be an HVT transistor possessing a higher voltage threshold than a standard NMOS transistor or this may be achieved by the memory unit supplying the gate 86 of the NMOS barrier transistor 80 with a voltage lower than Vdd.

The precharge circuitry 40, 60 comprises a first precharge circuit 40 and a second precharge circuit 60. Each precharge circuit 40, 60 includes an input 42, 62, an output 44, 64, and a PMOS transistor 46, 66. The output 44 of the first precharge circuit 40 is connected to the common bit line node 30 and the output 64 of the second precharge circuit 60 is connected to the read sense node 50. The input 42, 62 of each precharge circuit 40, 60 is connected to the voltage input line 8. Each PMOS precharge transistor 46, 66 is connected to the input 42, 62 and the output 44, 62 of their respective precharge circuits 40, 60. The PMOS precharge transistors 46, 66 are analogous to a switch in this particular installation. The PMOS precharge transistors 46, 66 are operable to connect the respective input 42, 62 to the respective output 44, 64 of the first precharge circuit 40 and second precharge circuit 60 on receipt of a precharge signal 210. This precharge signal 210 may be a common precharge signal 210 supplied on a common line, pc_bar.

The first precharge circuit 40 is operable to supply voltage Vdd from the voltage input line 8 to the common bit line node 30 and therefore via an NMOS bit line select transistor 22 to the selected bit line. The second precharge circuit 60 is operable to supply voltage Vdd from the voltage input line 8 to the read sense node 50.

The memory unit 100 discussed above may include a single bit line 20 or a plurality of bit lines 20. Each bit line 20 may be connected to a plurality of single ended memory cells 10.

Each bit line 20 of the plurality of bit lines 20 will be connected to the common bit line node by an NMOS bit line select transistor 22. The memory unit 100 may also include a Mux or Multiplex controller 90 operably connected to the gates 28 of the one or more NMOS bit line select transistors 22.

The waveform diagrams in figures 5 and 6 show the precharge signal 210, pc_bar being driven low to activate the precharge circuitry 40, 60. The read bit line voltage (rbl on the graphs) increases during precharge as the read bit line 20 is charged via the NMOS transistors 46, 66 of the precharge circuitry 40, 60. During precharge the rate of increase of rbl voltage decreases as the voltage approaches Vdd-Vvri shown by the line VDD-Vtn on the graph.

As rbl voltage rises on the selected read bit line 20 the difference between the reference voltage Vdd and rbl voltage reduces. As this difference approaches Vvfi the transistor will cease to conduct and limit the voltage supplied to the selected read bit line 20. Thus, if precharge continued the voltage of the read bit line 20 would tend to Vdd-Vv-ri as the precharge voltage is being supplied by the first precharge circuit 40 to the read bit line 20 via the NMOS read bit line select transistor 22. Precharge ends before the voltage of rbl reaches Vdd-Vvri as the full voltage is not required and to reach Vdd-Vvm would slow the sense process. During precharge the common bit line node is 30 or mux common node 30 shown as mcn on the graphs of figures 5 and 6 is pulled to Vdd by the first precharge circuit 40. Once precharge is complete and the common bit line node 30 and thus the read bit line 20 are disconnected from the voltage input line 8 the voltage of the common bit line node 30 falls to reach equilibrium with the voltage rbl of the read bit line 20.

During precharge the output circuitry 70 including the read sense node 50 is precharged to the supply voltage Vdd by the second precharge circuit 60 connecting the output circuitry 70 to the voltage input line 8. Both the first precharge circuit 40 and the second precharge circuit 60 are preferably active simultaneously under the control of a common precharge signal 210.

After precharge the NMOS barrier transistor 80 therefore has a first connection point 82 connected to the common bit line node 30 at a voltage tending to Vdd-Vvri and a second connection point 84 connected to the read sense node at Vdd. The difference between the voltage lower of the two channels of the NMOS barrier transistor 80, that of the common bit line node 30 (mcn), and Vdd is less than VvT2, because the NMOS barrier transistor 80 has a voltage threshold Vv-r2 greater than the voltage threshold Vvri of the NMOS bit line select transistor 20, the NMOS barrier transistor 80 will not conduct and the voltage difference between the read bit line 20 and the read sense node of the output circuit 70 is maintained.

The memory unit 1 is thus prepared to output the data value of one of the one or more single ended memory cells 10. A single ended memory cell 10 of the one or more memory cells 10 may be connected to the selected read bit line 20 of the one or more read bit lines 20 is activated by a read word line voltage or read signal 200 supplied on the read word line 19 to the gate 18c of the NMOS buffer transistor 18, of the particular memory cell 10 being read..

In figure 5 the result of a data value of 1 can be seen. If the single ended memory cell 10 holds a data value of 1 the memory node 17 or qb will be low or have a value tending to OV. Therefore, the NMOS memory transistor 16 will not conduct and the equilibrium will be maintained in the read bit line 20 and the voltage differential will be maintained across the NMOS barrier transistor. Therefore, the output circuit will remain high or near Vdd and the sense operation will output a data value of 1.

In figure 6 the result of a data value of 0 can be seen. If the single ended memory cell 10 holds a data value of 0 the memory node 17 or qb will be charged or have a value tending to Vdd. Therefore, the NMOS memory transistor 16 will conduct and the equilibrium in the read bit line 20 will be lost as the NMOS memory transistor 16 is operable to connect the read bit line 20 to ground 15 and therefore pull the read bit line low or to OV. The low voltage on the read bit line 20 connected to the first connection point 24 of the NMOS bit line select transistor 22 allows the NMOS bit line select transistor 22 to conduct and pull the common bit line node 30 low. The common bit line node 30 is connected to the first connection point of the NMOS barrier transistor 80. Therefore, the lower of the two channels connected to the NMOS barrier transistor 80 is reduced to lower than Vdd-Vvr2 and the NMOS barrier transistor 80 is moved to conduct. The charge in the output circuit 70 and thus the read sense node 50 is conducted to ground through the NMOS barrier transistor 80, the NMOS bit line select transistor 22 and the memory cell 10. Thus, the output circuit 70 is pulled low or to ground and the sense operation will output a data value of 0.

IN USE

The target read bit line 20 is first selected via a NMOS bit line select device 22 according to the muxs select signals 200 also called read bit line signal 200, only one of the gates 28 of the NMOS bit line select device 22 is driven high by a column decoder 92 of the mux controller 90.

The precharge operation is then performed by driving pc_bar low to provide the precharge signal 210, which turns on PMOS devices 46, 66 Mpcb and Mpcs of the first and second precharge circuits 40, 60, thereby pulling both the mux common node (men) or bit line common node 30 and read sense node 50 high to Vdd.

The high level on the common bit line node 30 will also supply charge to pull up the selected read bit line 20 (e.g. rb1[0] via device Mns0), assuming that it was previously at a low voltage level. If it was already precharged by virtue of a previous read operation, then the only consequence is that less energy will be used during this operation further increasing the efficiency of the memory unit 100.

Since the NMOS bit line select transistor 22 is an NMOS transistor this is an NMOS pull-up.

Therefore, the rate of charging will progressively weaken as the read bit line voltage approaches Vdd-Vvm, i.e. the NMOS threshold voltage of the NMOS bit line select transistor 22 below the voltage Vdd of the voltage input line 8 also known as the positive rail 8.

This weakening of the pull-up drive is the reason why most memory designs instead utilise PMOS to charge their read bit lines. With an NMOS-only bit line select, if the precharge operation is curtailed before the charging current has dropped to an insignificant level, once the pull-up on mcn 30 is released, its voltage will drop to equilibrate with the bit line voltage, thus immediately losing the high level required to output a clear binary state allowing a successful sense operation. The only way to avoid that voltage collapse is to wait an inordinate length of time for the precharge to get to a level where the current has decayed sufficiently to safely turn off Mpcb, the PMOS transistor 46 of the first precharge circuit 40.

The approach taken by the current invention is to tolerate that collapse of mcn voltage by the inclusion of an NMOS barrier device 80 (Mcas) to act as a potential barrier between the mcn node 30 and rsn node 50. Crucially the Mcas transistor 80 is a device with a higher threshold voltage Vv-r2 than the threshold voltage Vvri of the bit line select transistor 20. Such HVT device options are very common in silicon processes, typically for today's technologies having a threshold voltage Vv-r2 or Vthvtn in the region of 80mV higher than the standard devices.

Because Mcas 80 has a higher threshold voltage, the drop of mcn 30 voltage will not disrupt the voltage on the rsn 50 side of the Mcas device 80 as long as the read bit line 20 and mcn 30 voltage has reached at least VDD-VthVtn which of course it will have done when there was still at least 60-80mV of effective drive on the muxs device.

Once the precharge is over, the read word line 19 is turned on whereupon the rsn node 50 will either be left in its high precharge state (if the cell 10 is at a data value of '1' and qb is low), or if the cell is at a data value of '0' (qb is high), the read bit line 20 will be discharged, pulling both mcn 30 and rsn 50 low. Since the read bit line only has to discharge from around VDD-VthVtn rather than full supply voltage Vdd, the read operation is faster and uses less power than a scheme operating with full rail swing on the bit lines: the read bit line 20 voltage swing is effectively amplified via cascode behaviour of the Mcas device 80.

So, depending on the state of the data stored in the target bit cell 10, the voltage level of rsn 50 will develop into two well-defined binary levels which can readily be detected and latched using a simple logic circuit 72. An example of a suitable circuit based on NOR gates is shown in Figure 4, though it's not an essential part of the invention. The only requirement for this logic circuit 72 is that it should be tolerant of the input voltage being undetermined once the sense operation has completed, as the rsn node 50 is allowed to float when a read/sense operation is not active. The circuit 72 of Figure 4 is a gated latch circuit 72 and meets that criterion since the freeze signal is high by default thereby forcing the state of the sensing NOR gates safely low with no risk of excess leakage currents.

Any system feature as described herein may also be provided as a method feature, and vice versa. As used herein, means plus function features may be expressed alternatively in terms of their corresponding structure.

Any feature in one aspect may be applied to other aspects, in any appropriate combination. In particular, method aspects may be applied to system aspects, and vice versa.

Furthermore, any, some and/or all features in one aspect can be applied to any, some and/or all features in any other aspect, in any appropriate combination.

It should also be appreciated that particular combinations of the various features described and defined in any aspects can be implemented and/or supplied and/or used independently.

Claims (14)

1. CLAIMSA memory unit (100) comprising: a read bit line (20); a common bit line node (30); an output circuit (70) having a read sense node (50); a voltage input line (8) for supplying a voltage (Vdd) to the memory unit from an external power supply (1); a single ended memory cell (10), including a buffered read port (12) and a cell io output node (14) connected to the read bitline (20); an NMOS bitline select transistor (22), the NMOS bitline select transistor having a first connection point (24) connected to the read bit line (20), a second connection point (26) connected to the common bit line node (30), a gate (28) and a voltage threshold value (VvTi) at which the NMOS transistor will conduct between the first and second connection points (24, 26); a first precharge circuit (40) operable to charge the read bit line (20) via the NMOS bitline select transistor (22), the first precharge circuit (40) having an input (42) connected to the voltage input line (8) and an output (44) connected to the common read bitline node (30); a second precharge circuit (60), operable to precharge the output circuit (70), the second precharge circuit (60) having an input (62) connected to the voltage input line (8) and an output (64) connected to the read sense node (50); An NMOS barrier transistor (80) having a first connection point (82) connected to the common bit line node (30), a second connection point (84) connected to the read sense node (50) and a Voltage Threshold value (VvT2) at which the NMOS transistor will conduct between the first and second connection points (82, 84); wherein the voltage threshold value (VvT2) of the NMOS barrier transistor (80) is greater than the Voltage Threshold value (VvTi) of the NMOS bit line select transistor (22).
2. 2. A memory unit (100) according to claim 1 wherein the NMOS buffer transistor (80) is a High Voltage Threshold (HVT) NMOS transistor (80).
3. 3. A memory unit (100) according to any preceding claim wherein the first precharge circuit (40) and the second precharge circuit (60) are operable under a common precharge signal (210) to precharge the read bitline (20) and the output circuit (70) respectively.
4. 4. A memory unit (100) according to any preceding claim wherein the first precharge circuit (40) and the second precharge circuit (60) each including a PMOS transistor (46, 66) operable to connect the first bitline node (30) and the second read sense node (50) to the voltage input line (8).
5. A memory unit (100) according to any preceding claim further including plurality of single ended memory cells (10) connected to the read bit line (12).
6. 6. A memory unit (100) according to any preceding claim including; a plurality of read bit lines (20) each connected to a plurality of single ended memory cells (10), each bit line including an NMOS bitline selection transistor (22); a mux controller (90) operably connected to the gates (28) of the NMOS bit line select transistors (22); wherein the plurality of NMOS bit line selection transistors (22) are operable to connect one of the plurality of read bit lines (20) to the first bitline node (30) on receipt of a signal from the mux controller (90).
7. 7. A memory unit (100) according to any preceding claim wherein the output circuit (70) comprises a gated latch (72).
8. 8. A memory unit (100) according to any preceding claim wherein the gated latch (72) comprises a plurality of NOR gates (74) and an inverter (76).
9. A memory unit (100) according to any preceding claim wherein the NMOS barrier transistor (80) has a Voltage Threshold value VvT2 at least 60mV higher than the voltage threshold value Vv-ri of the NMOS bitline select transistor (22).
10. 10. A memory unit (100) according to any preceding claim wherein the single ended memory cell (10) comprises a memory node (17), a NMOS memory transistor (16) having a first connection point (16a) connected to ground (15) a second connection point (16b) and gate (16c) connected to the memory node (17); a NMOS buffer transistor (18) having a first connection point (18a) connected to the second connection point (16b) of the memory transistor (16), a second connection point (18b) connected to the memory cell node (14) and a gate (18c) connected to a read word line (19); the NMOS memory transistor (16) operable to conduct between the first connection point (16a) and the second connection point (16b) depending on the voltage of the memory node (17), the NMOS buffer transistor (18) operable to connect the memory NMOS transistor (16) to the cell output node (14) depending on the read wordline voltage (220) of the read wordline (19).
11. 11. A method for reading a data value stored in a single ended memory cell (10), that is part of a memory unit (100); The method comprising: a first bit line select NMOS transistor (22) selecting a read bit line (20) in response to a read bit line signal (200); precharging the read bit line (20) using a first precharge circuit (40) via the bit line select NMOS transistor (22); precharging a read sense node (50) using a second precharge circuit (40); after precharge is complete maintaining a voltage difference between the read sense node (50) and the read bit line (20) across an NMOS buffer transistor (80) having a higher Voltage Threshold value VvT2 than the voltage threshold value Vvri of the NMOS bit line select transistor (22); thereafter connecting the memory cell (10) to the read bit line 20 in response to a read wordline signal (220), and the memory cell (10) either maintaining the precharge voltage in the read bit line (20) and the output circuit (70) or discharging the read bit line (20) and the output circuit (70) to ground depending on the data value of the memory cell (10).
12. 12. The method of claim 11 wherein the memory unit (100) is the memory unit of any io one of claims 1 to 10.
13. 13. The method of claim 11 or 12 wherein the read sense node (50) is charged to a voltage Vdd supplied by an external power supply and the read bit line (20) is precharge to Vdd-Vvri, wherein Vvri is the threshold voltage value at which the NMOS bitline transistor (22) will conduct.
14. 14. The method of any one of claims 11 to 13 wherein if the data value is 1 the voltage in a memory node (17) applied to a gate (16c) of the memory NMOS transistor (16) is low and the read bit line (20) is maintained at the precharge voltage, and if the data value is 0, the voltage in the memory node (17) applied to a gate (16c) of the memory NMOS transistor (16) is high causing the Memory NMOS transistor (16) to connect the read bit line (20) to ground causing it to discharge.30 35 40