GB2563841A

GB2563841A - Data processing

Info

Publication number: GB2563841A
Application number: GB1710163.5A
Authority: GB
Inventors: Pankaj Bangdiwala Rohan
Original assignee: Sony Interactive Entertainment Europe Ltd
Current assignee: Sony Interactive Entertainment Europe Ltd
Priority date: 2017-06-26
Filing date: 2017-06-26
Publication date: 2019-01-02
Also published as: WO2019002835A1; GB201710163D0

Abstract

A method and apparatus for configuring a logic circuit for the execution of legacy code wherein a data package containing program data and configuration data is accessed 400 and a logic circuit is configured in accordance with the configuration data so that the program data can be executed on the logic circuit 490. The configuration step may comprise configuring at least a set of programmable interconnection between logic blocks of the logic circuit. The configuration data may be a reference to one of a group of two or more sets of information and configuring the circuit in accordance with one of the sets 440-470. The configuration data may comprise configuration information which may be stored in a configuration information store associated and accessed by the circuit. The program may be executed by a CPU/processor separate to the circuit if no configuration data is detected 410-430.

Description

DATA PROCESSING

Field of the Disclosure

This disclosure relates to data processing.

Description of the Related Art

The “background” description provided herein is for the purpose of generally presenting the context of the disclosure. Work of the presently named inventors, to the extent it is described in this background section, as well as aspects of the description which may not otherwise qualify as prior art at the time of filing, are neither expressly nor implicitly admitted as prior art against the present disclosure.

Data processing apparatus, such as (for example) a computer games machine, provide a data processor or CPU to execute program code (for example to allow a user to play a computer game).

The program code is generally specific to a type of data processor.

It can be useful to allow different program code, which is to say, program code intended (for example, compiled) for a different data processor, to be executed by the apparatus. For example, it may be desirable to allow so-called legacy computer games to be played using a more modern machine, even though the legacy program code of the earlier game is not compatible with the data processor in the more modern machine.

One option is to provide emulation of the earlier processor, which is to say, to provide a program to be run on the modern processor to emulate processing operations of the earlier processor. Emulation can be processor-intensive, however.

Another option is to recompile the earlier program code. This however involves distributing a replacement version of the earlier program code, and also means that functionality of the earlier data processor must be mapped to (potentially different) functionality of the more modern data processor. A further example, used in some models of the Sony ® PlayStation3 ® games machine, is to provide a separate instance of the legacy data processor to execute legacy program code. Summary

This disclosure provides a data processing method comprising: accessing a data package comprising program code, executable by code-executing functions of a code-specific processor, and configuration data defining a particular configuration of a logic circuit having a programmable configuration; and configuring the logic circuit in accordance with the configuration data to provide a configured logic circuit to perform the code-executing functions of the code-specific processor.

This disclosure also provides computer software which, when executed by a computer, causes the computer to perform the method defined above.

This disclosure also provides data processing apparatus comprising: a logic circuit having a programmable configuration; a data interface to access a data package comprising program code, executable by code-executing functions of a code-specific processor, and configuration data defining a particular configuration of the logic circuit; and configuration circuitry to configure the logic circuit in accordance with the configuration data to provide a configured logic circuit to perform the code-executing functions of the codespecific processor.

This disclosure also provides a data package comprising program code, executable by code-executing functions of a code-specific processor; and configuration data defining a particular configuration of a logic circuit having a programmable configuration, the particular configuration ofthe logic circuit being a configuration which provides the code-executing functions of the code-specific processor.

It is to be understood that both the foregoing general description and the following detailed description are exemplary, but not restrictive of, the present disclosure.

Brief Description of the Drawings A more complete appreciation of the disclosure and many of the attendant advantages thereof will be readily obtained as the same becomes better understood by reference to the following detailed description of embodiments, when considered in connection with the accompanying drawings, in which:

Figure 1 schematically illustrates a data processing apparatus;

Figure 2 schematically illustrates a so-called tile forming part of an example FPGA logic circuit;

Figure 3 illustrates a portion of an FPGA logic circuit;

Figure 4 is a schematic flowchart illustrating a data processing method;

Figures 5 to 8 schematically illustrate example formats of a data package;

Figure 9 is a schematic flow chart illustrating the generation of a data package;

Figure 10 is a flowchart schematically illustrates a data processing method;

Figure 11 schematically illustrates a part of the operation of a server device forming a repository of configuration data; and

Figure 12 schematically illustrates a portion of storage in the data processing apparatus of Figure 1.

Description of the Embodiments

Figure 1 schematically illustrates a data processing apparatus. The data processing apparatus 100 is configured to execute program code provided as at least a part of a data package 110, and accessed using a data interface 120. An example of the provision of the data package 110 is via a non-volatile machine-readable storage medium such as a Blu-Ray® disk, with the data interface 120 being a Blu-Ray disk reader. However, other techniques can be used to provide the data package, such as via a different type of storage medium (such as a memory card or the like), in which case the data interface 120 could be the appropriate reader for such a storage medium, or via a network download such as an internet download, in which case the data interface could be an internet interface.

The data interface 120 is connected to a bus 122. A package loader 124, connected to the bus 122, carries out processing to retrieve the data package 110 from its providing medium and store the data contained in the data package (which will be discussed below) in the appropriate memory of the apparatus 100.

Non-volatile storage 126, such as a flash memory and/or hard disk storage device, input/output (I/O) interfaces 128 and an input/output (I/O) bridge 130 are also connected to the bus 122. The I/O interfaces provide interface arrangements with other devices such as peripheral devices, user interface devices and network connections.

The I/O bridge 130 provides a data connection between the bus 122 and a bus 132 to which a central processing unit (CPU) 134, a graphics processing unit (GPU) 136 and a random access memory (RAM) 138 are connected. The CPU and GPU 134, 136 provide respective examples of a processing unit separate to the logic circuit (an FPGA - see below) and are configured to execute code stored in the RAM 138, for example in response to user interface inputs received via the I/O interfaces 128, and to generate user outputs such as display images, sound etc. to be output via the I/O interfaces 128. A field programmable gate array (FPGA) arrangement comprising an FPGA logic circuit 140 and an FPGA memory 142 are connected to the bus 122. This forms an example of a logic circuit having a programmable configuration. The FPGA memory provides an example of a data store to store the set of configuration information in a configuration information store associated with the logic circuit; in which the logic circuit is configured to access the set of configuration information stored in the configuration information store, to define a current configuration ofthe logic circuit.

Operations of the apparatus of Figure 1, to be discussed in more detail below, are carried out by the data interface 120 accessing a data package 110 comprising program code, executable by code-executing functions of a code-specific processor, and configuration data defining a particular configuration of the logic circuit 140; and configuration circuitry (implemented in this example as the package loader 124) configuring the logic circuit in accordance with the configuration data to provide a configured logic circuit to perform the codeexecuting functions of the code-specific processor.

Figure 2 schematically illustrates a so-called tile 200 forming part of an example FPGA logic circuit. In a full FPGA logic circuit, fabricated as a semiconductor device, an array of such tiles 200 is provided, connected between sets of row 210 and column 220 bus lines. In this example, each tile 200 comprises a programmable logic element 202 (sometimes referred to as a configurable logic block or CLB), a programmable connection-right 204, a programmable connection-down 206 and a switch element 208 intersecting a row and column, and including an SRAM memory 209. FPGAs can be configured to carry out particular functionality after manufacturing. This can distinguish FPGAs from Application Specific Integrated Circuits (ASICs), which are fabricated to carry out a specific function.

Various types of FPGA include those with non-volatile memory cells (for example, based on flash memory technology), and those with volatile memory cells (such as SRAM-based elements as in the example of Figure 2). FPGAs with volatile memories generally use an external non-volatile memory to hold their configuration information. The configuration information is transferred serially into the SRAM-based memories upon initialisation.

The example discussed here makes use of an external memory, the FPGA memory 142, and SRAM-based cells. However, the present techniques are also applicable to nonvolatile programmable logic elements, in which case operations to be described below which relate to writing configuration information into the FPGA memory 142 would be performed by writing configuration information to the non-volatile memory cells.

Other programmable devices are also envisaged within the scope of the present disclosure, such as so-called Complex Programmable Logic Devices (CPLDs).

The generation of the configuration information involves producing a design layout of the required logical circuitry to be implemented by the configured FPGA or other programmable device. This can be specified using a visual design program (such as a computer aided design program) or as a so-called hardware descriptor language (HDL) such as Verilog or VHDL. Design software is then used to implement or map this circuit design onto a physical layout of the programmable functions and interconnections of the device. The physical layout is then tested, using simulation software, for signal timing, crosstalk, efficiency of routing and other functionality, possibly being refined or varied as a result, before being translated into configuration information (a binary programming file of the appropriate format) to be provided to the device itself in order to configure the device.

In example embodiments, the FPGA can be configured to act as, say, an earlier or different processing element. For example, in a games or other data processing machine of a current generation, such an FPGA can be used to provide the functionality of a previous generation machine or even a different type of machine so as to allow compatibility with legacy or different software.

More than one configurable logic device of the type described here can be provided.

For example, if two such devices are provided, the system could be responsive to one instance of configuration information in a data package to configure and use just one of the devices, for example an arbitrary one, whereas if two instances of configuration information are provided, both devices would be configured by respective instances.

Returning to Figure 2, the tile 200 receives programming information via the lines 220, 210 and at least some of the programming information is stored locally in the SRAM 209 of the switch element 208. Under control of the programming information, a logic function or a set of functions carried out by the programmable logic element 202 is configured, connections to the adjacent tile to the right (in the array) are established by the programmable connection-right 204, and connections to the next tile down in the array are established by the programmable connection-down 206.

The tiles 200 of the array provide an example of the logic circuit comprising a plurality of logic blocks (the tiles themselves, and/or the elements 202) and at least a set of programmable interconnections between the logic blocks (provided by the programmable connections 204, 206).

Figure 3 illustrates a portion of an FPGA logic circuit comprising an array of such tiles 200 with associated row and column bus lines 210, 220, such that each tile lays in the intersection of a row line and a column line, allowing each tile to be addressed individually (by enabling that row and that column line) during a programming phase. Programming logic 300 associated with the rows and columns provides programming information to the SRAM 209 and to the programmable logic element 202 the programmable connection-right 204 and the programmable connection-down 206. The FPGA circuitry operates under the control of a clock signal 310.

Figure 4 is a schematic flowchart illustrating a data processing method carried out, for example, by the apparatus of Figure 1. At a step 400, the data interface 120 accesses the data package 110 as discussed above.

Subsequent steps of a loading method are carried out by the data interface and/or the package loader 124. These are described by way of example, but it will be appreciated that corresponding and equivalent steps in a different order, or carried out in parallel, may be performed.

At a step 410, the package loader detects whether the data package data 110 contains configuration data or a reference to configuration data. A reference to configuration data may comprise an indication of a location, for example in the RAM 138 and/or in the non-volatile storage 126 at which the configuration data may be found. Alternatively, a reference to configuration data may be a reference to a location on an external server device at which configuration data may be found.

If the outcome of the detection at the step 410 is “no” then control passes to a step 420 at which executable code forming the data package 110 is loaded by the package loader to the RAM 138. As far as the data package loading process is concerned that is the completion of such a process, but as a subsequence optional (all be it usual) step, the executable code is executed using the CPU 134 and/or the GPU 136 at a step 430. This step is shown in a broken outline to indicate that it does not necessarily form part of the package loading process.

The route of the “no” outcome of the step 410, the step 420 and the step 430 provides an example of detecting whether a data package provides configuration data; and when a data package is detected not to provide configuration data, executing program code provided by that data package using a processing unit such as the CPU 134 and/or the GPU 136 separate to the logic circuit.

Returning to the “yes” outcome of the step 410, at a step 440, the package loader 124 detects whether actual configuration data forms part of the data package 110. If the answer is “no” then control passes to a step 450. Here, because of the “yes” outcome of the step 410 and the “no” outcome of the step 440 the assumption is that the data package contains a reference to configuration data, and therefore at the step 450 the package loader 124 obtains the reference to the configuration data from the data package and, at a step 460, retrieves the configuration data referenced or pointed to by the reference obtained at the step 450. This may involve retrieving the configuration data from, for example, the non-volatile storage 126 and/or the RAM 138 or forming a network connection to a remote server to obtain the configuration data from that server.

After the step 460, or as a “yes” outcome of the step 440, the configuration data (either from the data package itself or retrieved at the step 460) is verified and loaded to the FPGA memory 142 at a step 470. Then, at a step 480 the configuration data is transferred from the FPGA memory 142 to the FPGA, thereby configuring at least a set of programmable interconnections between logic blocks of the logic circuit. This provides an example of storing the set of configuration information in a configuration information store associated with the logic circuit; and the logic circuit accessing the set of configuration information stored in the configuration information store, to define a current configuration of the logic circuit.

The step 450 provides an example of detecting configuration data defining a reference to a selected one of a group of two or more sets of configuration information, so that subsequently (the step 480) the logic circuit is configured in accordance with the selected set of configuration information.

Under the “yes” outcome of the step 440, it is detected that the configuration data comprises a set of configuration information, so that subsequently (the step 480) the logic circuit is configured in accordance with the set of configuration information.

In either instance, the package loader 124 provides an example of a detector to make such a detection.

Again, this forms the end of the package loading process, but as an optional (though usual) step, shown in broken line, the executable code forming part of the data package is executed using, at least in part, the FPGA at a step 490. The phrase “at least in part” indicates that some or all, but not necessarily all, of the program code may be executed by the configured FPGA, and/or that some or all, but not necessarily all, of the functionality of executing the program code may be provided by the configured FPGA. For example, the configured FPGA could provide the functionality of a co-processor or the like. Or the configured FPGA could provide the functionality of a separate processor. This provides an example of executing the program code using the configured logic circuit.

The package loader, the CPU or another device can be responsible for routing the executable code for execution by the CPU, GPU and/or FPGA in accordance with the configuration data forming part of the data package.

The loading process, which is to say the steps 400 to 420 or 480, can be carried out using hardware, software-controlled hardware or a combination of the two. In examples in which these steps are carried out, at least in part, by software-controlled hardware, it will be appreciated that the disclosure encompasses computer software which, when executed by a computer, causes the computer to perform such a method. The hardware could be embodied by a second CPU or similar processor. The software could be provided by a machine-readable non-transitory storage medium such as the non-volatile storage 126.

Figures 5 to 8 schematically illustrate example formats of the data package 110.

Referring to Figure 5, the data package 110 simply contains executable code 500, although it is noted that this term may include ancillary data associated with the executable codes such as libraries, images, audio samples and the like. The term “executable code” in this context therefore refers to code and data for execution by the CPU 134 and/or GPU 136 to provide the required functionality of the apparatus. An example of such functionality is the execution of a computer game program. Therefore, the significant feature of the data package of Figure 5 is that it does not contain FPGA configuration data or a reference to FPGA configuration data, nor does it contain code to be executed by or using the FPGA. Therefore, the data package shown in Figure 5 would result in the “no” outcome of the step 410 in Figure 4.

In Figure 6, the data package 600 comprises executable code 610 (as discussed above) along with a reference 620 to configuration data. As discussed above, the reference may be a reference to a position within storage forming part of the apparatus or to a location external to the apparatus, for example a location at an external server device. The data package 600 of Figure 6 would result in the “no” outcome of the step 440 of Figure 4 being taken.

Figure 7 schematically illustrates a data package 700 comprising executable code 710 as discussed above and FPGA configuration data 720 such that the configuration data can be verified and loaded at the step 470 as the “yes” outcome of the step 440 of Figure 4.

Finally, as an alternative format to that of Figure 5, Figure 8 schematically illustrates a data package 800 comprising executable code 810 of the type discussed above and a null reference 820. This null reference 820 is a data item which positively affirms that a reference (such as the reference 620) is not provided in the data package. The null reference 820 can therefore force the “no” outcome of the step 410 in Figure 4.

Figures 6 and 7 therefore provide example of a data package comprising program code, executable by code-executing functions of a code-specific processor; and configuration data defining a particular configuration of a logic circuit having a programmable configuration, the particular configuration ofthe logic circuit being a configuration which provides the codeexecuting functions of the code-specific processor.

In Figure 6, the configuration data comprises data defining a selected one of a group of two or more sets of configuration data.

In Figure 7, the configuration data provides at least a configuration of a set of programmable interconnections between logic blocks of the logic circuit.

Figure 9 is a schematic flow chart illustrating the generation of a data package such as the data package 600 or the data package 700 discussed above. At a step 900, executable code for execution, at least in part, by the FPGA logic circuit 140 when appropriately configured is prepared by a compilation and assembly process. At a step 910, configuration data is accessed, for example from a repository of configuration data or a remote server device. Then at a step 920, the data package 600, 700 is generated so as to include the prepared executable code and either the configuration data or a reference to the configuration data.

Figure 10 is a flowchart schematically illustrates a data processing method comprising accessing (at a step 1000) a data package comprising program code, executable by codeexecuting functions of a code-specific processor, and configuration data defining a particular configuration of a logic circuit having a programmable configuration. As discussed above, this may be carried out by the package loader 124 via the bus 122 and the data interface 120.

Then, at a step 1010 the package loader 124 configures the FPGA logic circuit 140 in accordance with the configuration data to provide a configured logic circuit to perform the codeexecuting functions of the code-specific processor.

This can be carried out, for example, by the steps of clearing the FPGA memory 142 at a step 1012, initializing the FPGA memory 142 at a step 1014 loading the configuration data into the FPGA memory 142 at a step 1016 and starting operation of the FPGA logic circuit 140 at a step 1018.

Figure 11 schematically illustrates a part of the operation of a server device forming a repository of configuration data.

The server device 1100 comprises an interface 1110 which communicates via a data communication path 1120 with an apparatus to generate a data package and/or with the data processing apparatus of Figure 1. The interface 1110 is associated with a selector 1130 which, in response to the selection of an instance of configuration data indicated by an instruction or reference received via the data link 1120, initiates the transfer of that instance of configuration data from a set of instances 1140 of configuration data to the interface 1110 from where it can be provided, via the data link 1120 to the requesting device.

Figure 12 schematically illustrates a portion 1200 of storage in the non-volatile storage 126 and/or the RAM 138 of Figure 1, in which one or more instances 1210 of configuration data are stored and which can be references a reference included in a data package indicating a storage location.

In so far as embodiments of the disclosure have been described as being implemented, at least in part, by software-controlled data processing apparatus, it will be appreciated that a non-transitory machine-readable medium carrying such software, such as an optical disk, a magnetic disk, semiconductor memory or the like, is also considered to represent an embodiment of the present disclosure.

It will be apparent that numerous modifications and variations of the present disclosure are possible in light of the above teachings. It is therefore to be understood that within the scope of the appended claims, the technology may be practised otherwise than as specifically described herein.

Claims

1. A data processing method comprising: accessing a data package comprising program code, executable by code-executing functions of a code-specific processor, and configuration data defining a particular configuration of a logic circuit having a programmable configuration; and configuring the logic circuit in accordance with the configuration data to provide a configured logic circuit to perform the code-executing functions of the code-specific processor.

2. A method according to claim 1, in which the configuring step comprises configuring at least a set of programmable interconnections between logic blocks of the logic circuit.

3. A method according to claim 1 or claim 2, in which the configuring step comprises: detecting configuration data defining a reference to a selected one of a group of two or more sets of configuration information, and configuring the logic circuit in accordance with the selected set of configuration information.

4. A method according to claim 1 or claim 2, in which the configuration data comprises a set of configuration information, the method comprising configuring the logic circuit in accordance with the set of configuration information.

5. A method according to claim 3 or claim 4, comprising: storing the set of configuration information in a configuration information store associated with the logic circuit; and the logic circuit accessing the set of configuration information stored in the configuration information store, to define a current configuration ofthe logic circuit.

6. A method according to any of the preceding claims, comprising executing the program code using the configured logic circuit.

7. A method according to any one of the preceding claims, comprising: detecting whether a data package provides configuration data; and when a data package is detected not to provide configuration data, executing program code provided by that data package using a processing unit separate to the logic circuit.

8. Computer software which, when executed by a computer, causes the computer to perform the method of any one of claims 1 to 5.

9. Data processing apparatus comprising: a logic circuit having a programmable configuration; a data interface to access a data package comprising program code, executable by code-executing functions of a code-specific processor, and configuration data defining a particular configuration of the logic circuit; and configuration circuitry to configure the logic circuit in accordance with the configuration data to provide a configured logic circuit to perform the code-executing functions of the codespecific processor.

10. Apparatus according to claim 9, in which the logic circuit comprises a plurality of logic blocks and at least a set of programmable interconnections between the logic blocks.

11. Apparatus according to claim 9 or claim 10, in which the configuration circuitry comprises a detector to detect configuration data defining a selected one of a group of two or more sets of configuration information, and circuitry to configure the logic circuit in accordance with the selected set of configuration information.

12. Apparatus according to claim 9 or claim 10, in which the configuration circuitry comprises a detector to detect, from the configuration data, a set of configuration information, and circuitry to configure the logic circuit in accordance with the set of configuration information.

13. Apparatus according to claim 11 or claim 12, comprising: a data store to store the set of configuration information in a configuration information store associated with the logic circuit; in which the logic circuit is configured to access the set of configuration information stored in the configuration information store, to define a current configuration of the logic circuit.

14. Apparatus according to any of the preceding claims, in which the logic circuit is configured to execute the program code.

15. Apparatus according to any one of the preceding claims, comprising: a processing unit separate to the logic circuit; in which: the data interface is configured to detect whether a data package provides configuration data; and when a data package is detected not to provide configuration data, the processing unit is configured to execute program code provided by that data package.

16. A data package comprising program code, executable by code-executing functions of a code-specific processor; and configuration data defining a particular configuration of a logic circuit having a programmable configuration, the particular configuration ofthe logic circuit being a configuration which provides the code-executing functions of the code-specific processor.

17. A data package according to claim 16, in which the configuration data provides at least a configuration of a set of programmable interconnections between logic blocks of the logic circuit.

18. A data package according to claim 16 or claim 17, in which the configuration data comprises data defining a selected one of a group of two or more sets of configuration data.