GB2538965A - Clock system - Google Patents

Abstract

A DC powered clock system 10 for powering and controlling a plurality of clocks 12 includes a control arrangement 20 which can send a signal along the DC power connection 16 to each clock 12 to control the clock 12. The control arrangement may include a Real Time Clock and Calendar (RTCC) chip.

Description

Clock System This invention concerns a clock system, and particularly a system for controlling a plurality of synchronised clocks.

In many buildings and locations, a plurality of clocks are provided. It is often required that these clocks should be synchronised with each other and thus centrally controlled. Conventionally this has been achieved using a two wire network of electrical supply to the clocks, wherein the plurality of positive and negative connections are periodically switched, causing all clocks connected to the network to move forward by one step. Alternatively a wireless connection system may be used, but this is not possible in all situations and may not always operate reliably.

According to the present invention there is provided a clock system, the system comprising a plurality of clocks, a power connection to each clock, and a control arrangement which can send a signal along the power connection to each clock to control the clock.

The control arrangement may be configured such that different signals can be sent to respective clocks, and the clocks may be configured such that respective clocks may display different times, and may display the time in different time zones.

Each clock may have a unique address to which the clock arrangement can communicate.

The control arrangement may be connectable to a GPS to provide accurate time data.

The control arrangement may include a Real Time Clock and Calendar (RTCC) chip.

A signal decoder may be provided for each clock.

In one configuration a DC power supply is provided. The control arrangement may be configured to produce a clock control signal which is converted to a voltage which can be combined with the power supply to the clocks.

The signal decoder may include a low pass filter to only allow low 10 frequency signals to pass to power the clock. The signal decoder may include a high pass filter to only allow high frequency signals to pass to control the clock.

The signal decoder may split an incoming current with part going to the low pass filter and part to the high pass filter.

An envelope filter may be provided to convert the high frequency voltage into a control signal for a clock, and the envelope filter may be located downstream of the high pass filter.

In a further configuration an AC power supply is provided.

The control arrangement may be configured such that an alteration may be made to the AC power signal to provide a control signal. The alteration may relate to any of the amplitude, frequency or phase of the AC power signal.

The signal decoder may include a rectifier to produce a DC supply to power the respective clock. A shift keying demodulator may be provided 30 which removes the alteration from the AC power to provide a signal to control the clock.

The signal decoder may split an incoming current with part going to the rectifier and part going to the shift keying demodulator.

Embodiments of the present invention will now be described by way of example only and with reference to the accompanying drawings, in which:-Fig. 1 is a diagrammatic representation of a first system according to the invention; Fig. 2 is a diagrammatic representation of part of the system of Fig. 1; Fig. 3 is a diagrammatic representation of a second system according to the invention; and Fig. 4 is a diagrammatic representation of part of the system of Fig. 3.

Figs. 1 and 2 show a DC powered clock system 10 for powering and controlling a plurality of clocks 12 which are shown diagrammatically in Fig. 1. The system 10 has a DC power supply 14 producing a potential difference of VCC. This passes to a connection 16 via a high frequency blocking filter 18.

The system 10 includes a control arrangement with a micro controller 20. The micro controller 20 is connectable to a GPS 22, and also an RTCC chip 24. The micro controller 20 can produce a data stream 26 which connects to an oscillator 28 to provide a pulsed control voltage 30, with pulses occurring when the oscillator 28 is turned on. The data stream 26 includes a signal to control the clocks 12, and may include an identifier to indicate to which clocks 12 each signal applies. The oscillator 28 is connected to the connection 16, and the connection 16 is connected to the clocks 12. Each of the clocks 12 includes a signal demodulator 32, one of which is shown in Fig. 2.

The signal demodulator 32 has a divide 34 in the signal coming from the connection 16 into upper and lower branches. The upper branch extends to a high pass filter 36, onto an envelope filter 38 and connects to a respective clock 12. The lower branch passes through a low pass filter 40 to provide a power supply to the respective clock 12.

In use the DC power supply 14 provides a DC voltage as shown at 42 to power the clocks 12. The micro controller 20 produces a data stream 26 to control the clocks 12. The data stream 26 activates the oscillator 28 to provide the pulsed voltage 30. The pulsed voltage 30 is combined with the voltage 42 at the connection 16 to provide a pulsed combined voltage as shown at 44. The high frequency blocking filter 18 prevents the high frequency oscillations of the pulsed control voltage 30 being absorbed by the power supply 14.

The pulsed combined voltage 44 is divided at 34 and in the upper branch the high pass filter 36 only allows through the pulsed control voltage 30. In the envelope filter 38 the pulsed voltage is converted back into the data stream 26 which passes to the clock 12 to control same. In the lower branch the low pass filter 40 removes the pulsed voltage just leaving the power voltage 42 to power the clock 12.

This therefore means that using a conventional two wire system a unique signal for each clock can be provided to control the clocks, with the respective signal indicating to which clock or clocks a signal applies. The system can be provided in new arrangements, or could be retrofitted to existing systems.

Figs. 3 and 4 show an AC system 50. Here an AC power supply 52 produces an AC power signal 54. Again a micro controller 56 is provided connectable to a GPS 58 and connected to an RTCC chip 60. The micro controller 56 provides a data stream 62 which passes to a shift keying module 64 where the data stream 62 is combined with the power signal 54 to provide an altered signal. The signal may be altered by amplitude as shown by 66, by frequency as shown by 68, or by phase as shown by 70. The altered signal is connected to a plurality of clocks 72.

Each clock 72 again has a signal demodulator 74 as shown in Fig. 4. The demodulator 74 divides the altered signal at 76, with an upper pass passing to a shift keying demodulator 78. The demodulator 78 converts the altered signal 66, 68, 70 back to the data stream 62 to control the respective clock 72. The lower pass has a bridge rectifier 80 which converts the altered signal 66, 68, 70 to a DC control voltage 82 to power the respective clock 72.

The system 50 operates by the power signal data stream 62 being combined with the power signal 54 to provide an altered signal 66, 68, 70 which as shown is divided such that the shift keying demodulator 78 extracts the data signal 62 from the altered signal to control the clock 72. The rectifier 80 produces a DC current 82 to provide power to the clock 72.

This therefore provides individual control for clocks and systems where 20 AC power is used, for instance where due to long distances or other reasons AC power is appropriate rather than DC power.

It is to be realised that a range of modifications may be made without departing from the scope of the invention. For instance, different signals may be applied, or converted or combined in different ways.

Whilst endeavouring in the foregoing specification to draw attention to those features of the invention believed to be of particular importance it should be understood that the Applicant claims protection in respect of any patentable feature or combination of features hereinbefore referred to and/or shown in the drawings whether or not particular emphasis has been placed thereon.

Claims (23)

1. CLAIMS1. A clock system, the system comprising a plurality of clocks, a power connection to each clock, and a control arrangement which can send a signal along the power connection to each clock to control the clock.
2. 2. A clock system according to claim 1, in which the control arrangement is configured such that different signals can be sent to respective clocks.
3. 3. A clock system according to claim 2, in which the control arrangement is configured such that the clocks are configured such that respective clocks may display different times, and may display the time in different time zones.L.0
4. 4. A clock system according to claims 2 or 3, in which each clock has a unique address to which the clock arrangement can communicate.

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5. 5. A clock system according to any of the preceding claims, in which the CO control arrangement is connectable to a GPS to provide accurate time data.O
6. 6. A clock system according to any of the preceding claims, in which the control arrangement includes a Real Time Clock and Calendar (RTCC) chip.
7. 7. A clock system according to any of the preceding claims, in which a signal decoder is provided for each clock.
8. 8. A clock system according to any of the preceding claims, in which a DC power supply is provided.
9. 9. A clock system according to claim 8, in which the control arrangement is configured to produce a clock control signal which is converted to a voltage which can be combined with the power supply to the clocks.
10. 10. A clock system according to claims 8 or 9 when dependent on claim 7, in which the signal decoder includes a low pass filter to only allow low frequency signals to pass to power the clock.
11. 11. A clock system according to any of claims 8 to 10 when dependent on claim 7, in which the signal decoder includes a high pass filter to only allow high frequency signals to pass to control the clock.
12. 12. A clock system according to claims 10 and 11, in which the signal decoder splits an incoming current with part going to the low pass filter and pad to the high pass filter.
13. 13. A clock system according to claims 11 or 12, in which an envelope filter is provided to convert the high frequency voltage into a control signal for a r 15 clock.
14. 14. A clock system according to claim 13, in which the envelope filter is CO located downstream of the high pass filter.
15. 15. A clock system according to any of claims 1 to 7, in which an AC power supply is provided.
16. 16. A clock system according to claim 15, in which the control arrangement is configured such that an alteration may be made to the AC power signal to provide a control signal.
17. 17. A clock system according to claim 16, in which the alteration relates to any of the amplitude, frequency or phase of the AC power signal.
18. 18. A clock system according to any of claims 15 to 17 when dependent on claim 7, in which the signal decoder includes a rectifier to produce a DC supply to power the respective clock.
19. 19. A clock system according to any of claims 15 to 18, in which a shift keying demodulator is provided which removes the alteration from the AC power to provide a signal to control the clock.
20. 20. A clock system according to claims 18 and 19, in which the signal decoder splits an incoming current with part going to the rectifier and part going to the shift keying demodulator.
21. 21. A clock system substantially as hereinbefore described and with reference to Figs. 1 and 2 of the accompanying drawings.
22. 22. A clock system substantially as hereinbefore described and with reference to Figs. 3 and 4 of the accompanying drawings. T 15
23. 23. Any novel subject matter or combination including novel subject matter disclosed herein, whether or not within the scope of or relating to the same CO invention as any of the preceding claims.