GB2530833A

GB2530833A - Optoelectronic switch

Info

Publication number: GB2530833A
Application number: GB1506729.1A
Authority: GB
Inventors: Andrew Rickman; Nathan Farrington
Original assignee: Rockley Photonics Ltd
Current assignee: Rockley Photonics Ltd
Priority date: 2014-09-30
Filing date: 2015-04-21
Publication date: 2016-04-06
Anticipated expiration: 2035-04-21
Also published as: GB201506729D0; GB2530833B

Abstract

An optoelectronic switch comprising: N switch modules; and an optical full-mesh interconnect (C5); each switch module comprising: M client facing input ports, and M output facing ports; a pre-mesh Array Waveguide (AWG) (C4) having M inputs and N outputs, each of the N outputs connected to a respective input on the optical full-mesh interconnect (C5); a post-mesh AWG (C6) having N inputs and M outputs, each of the N inputs connected to a respective output of the optical full-mesh interconnect (C5) and each of the M outputs for communicating a signal to one or more of the M outputs (0P1, OP2, OPM) of the switch module; and a first array of Detector Remodulators (DRMs) (C3) located before the pre-mesh AWG, each DRM of the first array configured to receive a signal from an input of the switch module (IP1, IP2, IPM) and to regenerate and/or change the wavelength of the received signal to produce a DRM output, the DRM output forming an input at a respective port of the pre-mesh AWG.

Description

OPTOELECTRONIC SWITCH

Field of the Invention

The present invention relates to an optoelectronic switch, particularly to an optoelectronic switch comprising a plurality of switch modules and an optical full-mesh interconnect, each switch module comprising a plurality of array waveguide gratings (AWGs) and at least one array of Detector Remodulators DRM5.

Background of the Invention

It is known that switching systems can be constructed from a combination of AWGs and tunable wavelength convertors (TWCs) and the potential for the cyclic AWG in optical switching has been recognized in recent years. Ye et al (IEEE/ACM Transactions on Networking, VOL PP, Issue 99, Page 1, Feb 2014) describe the use of AWGs in Cbs-type optical switches and other architectures and Ngo et al (Proceedings 23rd Conference of IEEE Communications Soc, 2004) have illustrated AWG switch architectures that are rearrangeably non-blocking and strictly non-blocking. Lucerna et al (AWG-Based architecture for optical interconnection in asynchronous systems in 2011 IEEE 12th International Conf on High Performance Switching and Routing) have discussed the problem of cross-talk in high port count AWGs and proposed a method of overcoming this by scheduling packets. In all such systems there must be an efficient means of optical wavelength conversion and the wavelength must be tunable. Pallavi and Lakshmi (I. J. Information Technology and Computer Science, 2013, 04, 30-39) have discussed optical packet switches constructed with AWGs where there is central control over the whole packet switch. US 8,792,787 describes optical packet switches involving TWCs and AWGs combined in layers and in 2 or more stages.

Summary of the Invention

The present invention provides, according to a first aspect, an optoelectronic switch comprising: N switch modules, where N is an integer; and an optical full-mesh interconnect; each switch module comprising: M client facing input ports, and M output facing ports, M being an integer which is either equal to or not equal to N; a pre-mesh Arrayed Waveguide Grating (AWG), the pre-mesh AWG having M inputs and N outputs, each of the N outputs connected to a respective input on the optical full-mesh interconnect; a post-mesh AWG, the post-mesh AWG having N inputs and M outputs, each of the N inputs connected to a respective output of the optical full-mesh interconnect and each of the M outputs for communicating a signal to one or more of the M outputs of the switch module; and a first array of Detector Remodulators (DRMs) located before the pre-mesh AWG, each DRM of the first array configured to receive a signal from an input of the switch module and to regenerate and/or change the wavelength of the received signal to produce a DRM output, the DRM output forming an input at a respective port of the pre-mesh AWG.

In this way, the pre-mesh and post-mesh AWGs are used both for wavelength division multiplexing/demultiplexing as well as wavelength routing.

Preferably, all of the AWGs are cyclic AWGs. It is envisaged that one or more of the AWGs of any of the embodiments described herein could be replaced by alternative wavelength dependent optical components such as an Echelle grating.

For the purpose of this invention a DRM should be understood to be an example of a type of tunable wavelength converter (TWC). It is envisaged that one or more of the DRM5 of any of the embodiments described herein could be replaced by alternative TWCs.

In more detail, a Detector Remodulator is a device used to convert a first optical signal to a second optical signal. For the purpose of the present invention, the first optical signal will have a first wavelength and the second optical signal may have a second wavelength different to the first wavelength so that each of the DRM5 function as a wavelength converter.

The DRM includes a photodetection stage (e.g. a photodiode) where the first optical signal (modulated) is detected and converted into an electrical signal. The photodetection stage is followed by a modulation stage (i.e. a modulator) configured to receive the electrical signal from the photodetection stage and also to receive an unmodulated light input having a tunable wavelength. The unmodulated light input is modulated by the modulated electrical signal produced at the photodetection stage. The modulated optical signal that is created at the modulation stage will therefore have a wavelength that corresponds to that of the unmodulated light signal. Wiilst in the electrical domain, the signal may advantageously be processed, for example by one or more of: amplification, reshaping, re-timing, and filtering before being applied to the second wavelength/channel. Each DRM may therefore include a CMOS chip for carrying out one or more of these functions, the CMOS chip connecting the photodetector of the DRM to the modulator of the DRM.

In our GB 1403191.8, the complete disclosure of which is herein incorporated by reference, we describe a number of examples of Detector Remodulators (DRMs) that could form one or more of the DRM5 of the present invention.

One example of a Detector Remodulator may comprise a silicon on insulator (SOI) waveguide platform including: a detector coupled to a first input waveguide (for receiving the first optical signal); a modulator coupled to a second input waveguide (for receiving the tunable wavelength input) and an output waveguide; and an electrical circuit connecting the detector to the modulator; wherein the detector, modulator, second input waveguide and output waveguide may be arranged within the same horizontal plane as one another; and wherein the modulator includes a modulation waveguide region at which a semiconductor junction is set horizontally across the waveguide. The modulation region may be a phase modulation region or an amplitude modulation region. However, it should be understood that any suitable DRM configured to act as a wavelength converter could be used. Tunable lasers are usually continuously tunable over a given range of wavelengths. However, also included in the definition of a tunable laser is one that may not be tunable across the whole of a wavelength band but where pre-set wavelengths may be selected across that wavelength band.

When constructing AWG-based switches using traditional TWCs, the number of switch stages, and the maximum size of the switch, are limited by the amount of insertion loss of the AWGs. Using DRM5 instead of traditional TWCs removes the problem of insertion loss by regenerating the signal when needed to allow for larger switches. DRMs can use different techniques for performing regeneration, such as optical-electrical-optical (OEO) conversion.

A DRM can be used to implement a circuit switch. A DRM with OEO functionality can also contain electronic buffers and can be used to buffer data to implement a burst switch, packet switch, or cell switch.

The development of the Detector Remodulator (DRM) as described herein enables packet switching in a flexible and scalable manner. DRM5 may be made with varying functionality and thus enable a variety of optical switch architectures which were hitherto impracticable.

In this invention, we thereby disclose how to construct an incrementally deployable scalable switching system by using a novel combination of DRM5 and AWG5.

The signal from each input of the switch module may be provided to the first array of DRMs directly or indirectly. \Mien applied indirectly, a signal from an input of the switch module may reach an input of one of DRM5 or the first array of DRMs via other components as explained in more detail below.

The close photonic/electronic integration of the present invention reduces power consumption. Switching in optical domain bypasses electronics speed and size bottleneck.

Furthermore, the innovative network architecture increases scalability and reduces hardware required.

A full mesh interconnect (also referred to as a fully connected network) is a network topology in which there is a direct link between all possible pairs of nodes. For example, in a full mesh interconnect having n nodes, there are n(n-1)/2 direct links. Such interconnects advantageously provide a high degree of reliability because a large number of redundant links exist between nodes. The optoelectronic switch may have any one of or, to the extent that they are compatible, any combination of the following optional features.

The optoelectronic switch may further comprise a second array of Detector Remodulators (DRMs) located after the post-mesh AWG, each DRM of the second array configured to regenerate and/or convert the wavelength of a signal from a respective output pod of the post-mesh AWG for communication to an output port of the switch module.

This communication to an output port of the switch module may be a direct connection or may be an indirect communication involving extra components which may act on the signal, for example to change its wavelength and ultimately the final output port.

The optoelectronic switch may further comprise a rearrangement AWG located after the second array of DRMS the rearrangement AWG having M input ports and M output ports, each of the M input ports connected to an output of a respective DRM of the second array of DRMs; and each output port of the rearrangement AWG connected to an output of the switch module.

The presence of a rearrangement AWG after the post-mesh AWG means that communication of a signal from the post-mesh AWG to the output ports of the switch module includes an extra rearrangement step. In this way, overall bandwidth of the switch can be increased.

The optoelectronic switch may further comprise a final array of DRMs after the rearrangement AWG such that the connection between each of the output ports of the rearrangement AWG and an output port of the switch module is achieved via one of the DRM5 of the final array.

In this way, the flnal array of DRM5 provides a mechanism for choosing the actual output port of the switch module irrespective of the path that a signal takes through the rearrangement AWG.

The optoelectronic switch may further comprise a rearrangement AWG located before the first array of DRM5, the rearrangement AWG having M input ports and M output ports, each of the M input ports connected to an output of a respective DRM of the second array of DRM5; and each output port of the rearrangement AWG connected to an output of the switch module.

The presence of a rearrangement AWG after the post-mesh AWG means that communication of a signal from an input port of the switch module to a respective input port of the pre-mesh AWG includes an extra rearrangement step. In this way, overall bandwidth of the switch can be increased.

The optoelectronic switch may further comprise an array of rearrangement Detector Remodulators (DRM5) located before the pre-mesh AWG, each DRM of the first array configured to receive a signal from an input of the switch module and to regenerate and/or change the wavelength of the received signal to produce a DRM output, the DRM output forming an input at a respective port of the rearrangement AWG Each array of DRM5 may take the form of one or more optical chips and one or more electronic components (for example CMOS chips). Preferably an array of DRM5 consists of a plurality of photodectectors, a plurality of tunable laser inputs, a plurality of optical modulators and a single CMOS chip. More preferably the array of DRM5 is fabricated on a single optical chip intimately connected to a single CMOS chip. Even more preferably the optical chip is a silicon chip.

Optionally, N!=M.

Optionally, N>M.

Optionally, NcM.

Optionally, N=M.

Optionally, the optical full-mesh interconnect is an optical backplane.

Optionally, the optoelectronic switch may be configured to act as a circuit switch. Circuit-switch connections require dedicated point-to-point connections during data transfer. This simplifies the design of the DRM as less functionality is required.

Optionally, the optoelectronic switch may be configured to act as a packet switch. A packet switch embodiment will differ from a circuit switch embodiment in that the DRMs of the switch module contain additional circuitry. In particular, a packet processor is required to determine which output port each packet should be sent to, based on the contents of each packet. A scheduler would also be present to control the overall timing of each packet through the switch by way of control of the tunable laser inputs for each DRM.

Optionally, the optoelectronic switch may be configured to act as a cell switch. In this way, the DRMs are configured in a similar way to that of the packet switch but uses fixed length cells. Scheduling the transfer of packets therefore requires the extra step of segmenting the data into fixed length cells (segments).

Optionally, the optoelectronic switch may be configured to act as a burst switch. In this way, the DRMs are configured to send multiple packets from the same source to the same destination consecutively.

Optionally, the optical full-mesh interconnect may have a "folded configuration" which forms a fold in the optoelectronic switch module, wherein for each optoelectronic switch module: the pre-mesh AWG is located before the fold; and the post-mesh AWG located after the fold.

The "folded configuration" of the optical full-mesh may be understood to mean that the inputs of the mesh are located on the same side of the mesh as the outputs of the mesh.

A switch module for connection to such a mesh will also have a "folded configuration" which results in the inputs of the switch module being located on the same side of the switch module as the outputs of the switch module.

For the purpose of the present invention, the "folded configuration" means that on a switch module, a single component of the switch module may be built to incorporate both pre-mesh and post-mesh components. In this way, the single component will be configured to process not only pre-mesh signals (i.e. those signals transmitted to the mesh), but also post-mesh signals (i.e. those signals received from the mesh).

Optionally, the input and output ports of each optoelectronic switch module are all arranged on a single external panel.

Preferably, the optoelectronic switch is constructed from silicon photonics. The combination of a silicon photonics platform and the structure of the architecture enables easy scaling to higher radix. Furthermore, the silicon photonics platform is highly manufacturable at low cost.

According to a second aspect of the present invention, there is provided, an optoelectronic switch module for use with an optical full-mesh interconnect, the optoelectronic switch module comprising: M client facing input ports, and M output facing ports, where M is an integer; a pre-mesh AWG, the pre-mesh AWG having M inputs and N outputs where N is an integer which is either equal to or not equal to M, each of the N outputs connected to a respective input on the optical full-mesh interconnect; a post-mesh AWG the post-mesh AWG having N inputs and M outputs, each of the N inputs connected to a respective output of the optical full-mesh interconnect and each of the M outputs for communicating a signal to one or more of the M outputs of the switch module; and a first array of Detector Remodulators (DRMs) located before the pre-mesh AWG, each DRM of the first array configured to receive a signal from an input of the switch module and to regenerate and/or change the wavelength of the received signal to produce a DRM output, the DRM output forming an input at a respective port of the pre-mesh AWG.

It is understood that each of the optional features described above in relation to the optoelectronic switch of the first aspect are equally applicable to the optoelectronic switch module of the second aspect.

Further optional features of the invention are set out below.

Brief Description of the Drawings

Embodiments of the invention will now be described by way of example with reference to the accompanying drawings in which: Figure 1 shows an optoelectronic switch comprising an array of up to N switch modules and a common optical full-mesh fabric (optical full-mesh interconnect); Figure 2 shows a schematic diagram of one of the optoelectronic switch modules of Figure 1, the optoelectronic switch module having a folded configuration; and Figure 3 shows a schematic diagram of an alternative optoelectronic switch module, the optoelectronic switch module having a flat configuration.

Detailed Description and Further Optional Features of the Invention Figure 1 shows an optoelectronic switch organized as an array of up to N switch modules and a common optical full-mesh fabric (optical full-mesh interconnect (05)).

Each switch module has M client facing input ports and M client facing output ports which could take the form of M bidirectional client-facing ports with two fibers per port. In addition, each switch module has N bidirectional fabric-facing ports with two fibers per port. The optical full-mesh fabric contains N times N fibers and connects each module to each other module with two fibers, one fiber for each direction of communication. Switch modules can either be integrated with the optical full-mesh fabric or separated with connectors to allow for incremental deployment and ease of maintenance.

The switch is capable of operating with fewer than N switch modules in place. It can therefore be scaled according to requirements.

Figures 2 and 3 show constructions of an optoelectronic switch module from Figure 1. The configuration of Figure 3 differs from that of Figure 2 only in that Figure 2 has a folded configuration, and Figure 3 has a flat configuration. The M client-facing input ports are connected to M optical fibers, which connect to the inputs of Cl, an array of M DRM5. The DRM5 regenerate the signals and convert the wavelengths such that each output of each DRM in the array is carried on one of M wavelengths, not necessarily unique. The M outputs of Cl connect to the M inputs of 02, an MxM AWG, with M optical fibers. The choice of wavelength at Cl determines the output port of 02. The purpose of Cl and 02 collectively is to rearrange the signals received by the switch module onto the set of output fibers of 02 in preparation for the later stages of DRM5 and AWGs.

The outputs of 02 connect to the inputs of C3, an array of DRM5, using M optical fibers. Like Cl, the DRM5 regenerate the signals and convert the wavelengths such that each output of each DRM in the array is carried on one of N wavelengths, not necessarily unique. The M outputs of 03 connect to the M inputs of 04, an MxN AWG, using M optical fibers. The choice of wavelength at 03 determines the output port of 04. The purpose of 03 and 04 collectively is to rearrange and multiplex signals to specific output fibers of 04, where specific fibers determine the destination switch module.

The outputs of 04 connect to the inputs of C5, a common optical full-mesh fabric, using N optical fibers. Each switch module connects to every switch module, including itself, using a single optical fiber per connection, for a total of NxN optical fibers in 05. Whereas C2 was used only for wavelength routing, C4 is used for both wavelength routing and wavelength division multiplexing (WOM). Up to M switch inputs can connect to another switch module by using M different wavelengths, all carried over the same single optical fiber in 05. 05 can be integrated with the switch modules, or separated with connectors to allow for ease of maintenance and incremental deployment.

The N outputs of CS connect to the N inputs of 06, an NxM AWG, using N optical fibers. The M outputs of 06 connect to the M inputs of 07, an array of M DRM5, using M optical fibers.

Like Cl, the DRM5 regenerate the signals and convert the wavelengths such that each output of each ORM in the array is carried on one of M wavelengths, not necessarily unique.

The M outputs of 07 connect to the M inputs of 08, an MxM AWG, using M optical fibers.

The choice of wavelength at 07 determines the output port of 08. The purpose of 06 is to demultiplex and route the signals received from 05. The purpose of 07 and 08 collectively is to rearrange signals from the M output fibers of C6 to arbitrary output fibers of C8.

The M outputs of 08 connect directly to the M client-facing output ports using M optical fibers. Optionally, as shown in Figure 2, the M outputs of CS connect to 09, an array of M DRMs, using M optical fibers. The M outputs of 09 connect to the M client-facing output ports using M optical fibers. The purpose of 09 is to convert the wavelength and protocol used for internal routing to a wavelength and protocol compatible with the 3rd-party equipment connected to the switch module output ports.

The choice of M and N is unconstrained in this architecture, although could be constrained by other factors such as the construction of the AWGs and DRMs. In particular, we note that the embodiments described herein all depict single connections between a given switch module and each other module (i.e. the number of possible outputs of the pre-mesh AWG (04) corresponds directly to the total number of switch modules as in Figure 2). It is envisaged that each single connection could be replaced by parallel connections.

Each DRM in the switch module has a 3rd port, not shown in Figure 2, for control. This control port, when connected to the appropriate electronic controller, allows the optoelectronic switch to act as a circuit switch, burst switch, packet switch, or cell switch.

The differences in these four types of switches depend on how data is buffered and transmitted, and on the timescales used for establishing and breaking circuits (paths) in the switch. A circuit is established along the path of 01 through 04 on a source switch module, 05, and 06 through 08 (or optionally 09) on a destination switch module. Note that the source and destination switch modules may be the same module.

A circuit switch establishes a long-lived circuit. Data travels over this long-lived circuit without further processing. A burst switch buffers packets in a DRM, establishes a short-lived circuit, and then transmits all packets destined for a specific switch output port in a single burst. A packet switch buffers a single packet in a DRM, establishes a short-lived circuit, and then transmits a single packet destined for a specific switch output port. A cell switch buffers a single packet in a DRM, establishes a short-lived circuit, divides the packet into smaller cells, and then transmits a single cell destined for a specific switch output port. A later-stage DRM then reassembles the cells belonging to a single packet.

The AWGs in 02, 04, 06, and 08, may be equivalent assemblies of smaller AWGs providing the same function as a single larger AWG, as long as the worst-case insertion loss is less than the optical link margin between stages of DRM5.

An additional embodiment is envisaged which corresponds to either of the embodiments of Figures 2 or Figure 3 but with the initial array of DRM5 Cl and final array of DRM5 09 removed. The purpose of Cl is to accept an input signal, in this case an optical input signal, with any format, and convert it to an optical signal with a format compatible with transmission through the switch invention. It is possible that an external transmitter could directly transmit a compatible optical signal and then Cl would not be needed. The purpose of 09 is to accept an internal optical signal with the format specific for transmission through the switch, and convert it into a format compatible with the 3rd-party receiver. It is possible that the receiver could directly use the internal optical signal.

An additional embodiment is envisaged which corresponds to either of the embodiments of Figures 2 or Figure 3 wherein the initial array of DRM5 Cl includes additional functionality for the switch. For example, the DRMs of Cl may be configured to include buffer modules which carry out electronic buffering. This would enable the switch invention to act as a packet switch.

For any of the embodiments described herein, it is envisaged that the optoelectronic switch may include a central control component that is configured to control switching of each and every optical signal by tuning each of the wavelengths of all of the tunable laser inputs present in the system (i.e. the tunable lasers that provide the unmodulated tunable inputs for each of Cl, C3, 07 and 09).

While the invention has been described in conjunction with the exemplary embodiments described above, many equivalent modifications and variations will be apparent to those skilled in the art when given this disclosure. Accordingly, the exemplary embodiments of the invention set forth above are considered to be illustrative and not limiting. Various changes to the described embodiments may be made without departing from the spirit and scope of the invention.

All references referred to above are hereby incorporated by reference.

Claims

CLAIMS1. An optoelectronic switch comprising: N switch modules, where N is an integer; and an optical full-mesh interconnect (05); Each switch module comprising: M client facing input ports, and M output facing ports, M being an integer which is either equal to or not equal to N; a pre-mesh AWG (04), the pre-mesh AWG having M inputs and N outputs, each of the N outputs connected to a respective input on the optical full-mesh interconnect (05); a post-mesh AWG (C6), the post-mesh AWG having N inputs and M outputs, each of the N inputs connected to a respective output of the optical full-mesh interconnect (05) and each of the M outputs for communicating a signal to one or more of the M outputs (OP1, 0P2, OPM) of the switch module; and a first array of Detector Remodulators (DRM5) (C3) located before the pre-mesh AWG, each DRM of the first array configured to receive a signal from an input of the switch module (IP1, 1P2, 1PM) and to regenerate and/or change the wavelength of the received signal to produce a DRM output, the DRM output forming an input at a respective port of the pre-mesh AWG.
2. The optoelectronic switch of claim 1, further comprising a second array of Detector Remodulators (DRM5) (07) located after the post-mesh AWG, each DRM of the second array configured to regenerate and/or convert the wavelength of a signal from a respective output port of the post-mesh AWG for communication to an output port (OP1, 0P2, OPM) of the switch module.
3. The optoelectronic switch of claim 2, further comprising a rearrangement AWG (C8) located after the second array of DRM5 (07), the rearrangement AWG having M input ports and M output ports, each of the M input ports connected to an output of a respective DRM of the second array of DRM5; and each output port of the rearrangement AWG connected to an output of the switch module.
4. The optoelectronic switch of claim 3, further comprising a final array of DRMs (09) after the rearrangement AWG (08) such that the connection between each of the output ports of the rearrangement AWG (08) and an output port of the switch module is via one of the DRM5 of the final array.
5. The optoelectronic switch of any one of the preceding claims, further comprising a rearrangement AWG (02) located before the first array of DRM5 (03), the rearrangement AWG having M input ports and M output ports, each of the M input ports connected to an output of a respective DRM of the second array of DRM5; and each output port of the rearrangement AWG connected to an output of the switch module.
6. The optoelectronic switch of claim 5, further comprising an array of rearrangement Detector Remodulators (DRM5) (Cl) located before the pre-mesh AWG, each DRM of the first array configured to receive a signal from an input of the switch module (IP1, 1P2, 1PM) and to regenerate and/or change the wavelength of the received signal to produce a DRM output, the DRM output forming an input at a respective port of the rearrangement AWG (02).
7. The optoelectronic switch of any one of the preceding claims, wherein N>M.
8. The optoelectronic switch of any one of the preceding claims, wherein N<M.
9. The optoelectronic switch of any one of the preceding claims, wherein N=M.
10. The optoelectronic switch of claim 1, wherein the optical full-mesh interconnect is an optical backplane.
11. The optoelectronic switch of any one of the preceding claims configured to act as a circuit switch.
12. The optoelectronic switch of any one of the preceding claims configured to act as a burst switch
13. The optoelectronic switch of any one of the preceding claims configured to act as a packet switch
14. The optoelectronic switch of any one of the preceding claims configured to act as a cell switch
15. The optoelectronic switch of any one of the preceding claims, wherein the optical full-mesh interconnect has a folded configuration which forms a fold in the optoelectronic switch module, wherein for each optoelectronic switch module: the pre-mesh AWG is located before the fold; and the post-mesh AWG located after the fold.
16. The optoelectronic switch of claim 15, wherein the input and output ports of each optoelectronic switch module are all arranged on a single external panel.
17. The optoelectronic switch of any one of the preceding claims; wherein the optoelectronic switch is constructed from silicon photonics.
18. An optoelectronic switch module for use with an optical full-mesh interconnect, the optoelectronic switch module comprising: M client facing input ports, and M output facing ports, where M is an integer; a pre-mesh AWG (C4), the pre-mesh AWG having M inputs and N outputs where N is an integer which is either equal to or not equal to M, each of the N outputs connected to a respective input on the optical full-mesh interconnect (05); a post-mesh AWG (06), the post-mesh AWG having N inputs and M outputs, each of the N inputs connected to a respective output of the optical full-mesh interconnect (05) and each of the M outputs for communicating a signal to one or more of the M outputs of the switch module; and a first array of Detector Remodulators (DRMs) (03) located before the pre-mesh AWG, each DRM of the first array configured to receive a signal from an input of the switch module (IP1, 1P2, 1PM) and to regenerate and/or change the wavelength of the received signal to produce a DRM output, the DRM output forming an input at a respective port of the pre-mesh AWG.
19. An optoelectronic switch comprising: N switch modules, where N is an integer; and an optical full-mesh interconnect (CS); Each switch module comprising: M client facing input pods, and M output facing pods, M being an integer which is either equal to or not equal to N; a pre-mesh AWG (04), the pre-mesh AWG having M inputs and N outputs, each of the N outputs connected to a respective input on the optical full-mesh interconnect (C5); a post-mesh AWG (C6), the post-mesh AWG having N inputs and M outputs, each of the N inputs connected to a respective output of the optical full-mesh interconnect (05) and each of the M outputs for communicating a signal to one or more of the M outputs (OP1, 0P2, OPM) of the switch module; and a first array of Detector Remodulators (DRM5) (03) located before the pre-mesh AWG, each DRM of the first array configured to receive a signal from an input of the switch module (IP1, 1P2, 1PM) and to regenerate and/or change the wavelength of the received signal to produce a DRM output, the DRM output forming an input at a respective pod of the pre-mesh AWG; a second array of Detector Remodulators (DRM5) (07) located after the post-mesh AWG, each DRM of the second array configured to regenerate and/or conved the wavelength of a signal from a respective output pod of the post-mesh AWG for communication to an output port (OP1, 0P2, OPM) of the switch module; a rearrangement AWG (08) located after the second array of DRM5 (07), the rearrangement AWG having M input pods and M output ports, each of the M input pods connected to an output of a respective DRM of the second array of DRM5; and each output pod of the rearrangement AWG connected to an output of the switch module; and a rearrangement AWG (02) located before the first array of DRMs (03), the rearrangement AWG having M input ports and M output ports, each of the M input ports connected to an output of a respective DRM of the second array of DRMs; and each output pod of the rearrangement AWG connected to an output of the switch module.
20. An optoelectronic switch comprising: N switch modules, where N is an integer; and an optical full-mesh interconnect (05); Each switch module comprising: M client facing input pods, and M output facing pods, M being an integer which is either equal to or not equal to N; a pre-mesh AWG (C4), the pre-mesh AWG having M inputs and N outputs, each of the N outputs connected to a respective input on the optical full-mesh interconnect (C5); a post-mesh AWG (C6), the post-mesh AWG having N inputs and M outputs, each of the N inputs connected to a respective output of the optical full-mesh interconnect (05) and each of the M outputs for communicating a signal to one or more of the M outputs (OP1, 0P2, OPM) of the switch module; and a first array of Detector Remodulators (DRM5) (03) located before the pre-mesh AWG, each DRM of the first array configured to receive a signal from an input of the switch module (IP1, 1P2, 1PM) and to regenerate and/or change the wavelength of the received signal to produce a DRM output, the DRM output forming an input at a respective pod of the pre-mesh AWG; a second array of Detector Remodulators (DRM5) (07) located after the post-mesh AWG, each DRM of the second array configured to regenerate and/or conved the wavelength of a signal from a respective output pod of the post-mesh AWG for communication to an output pod (OP1, 0P2, OPM) of the switch module; a rearrangement AWG (08) located after the second array of DRM5 (07), the rearrangement AWG having M input pods and M output ports, each of the M input pods connected to an output of a respective DRM of the second array of DRMs; and each output pod of the rearrangement AWG connected to an output of the switch module; a rearrangement AWG (02) located before the first array of DRM5 (C3), the rearrangement AWG having M input pods and M output pods, each of the M input pods connected to an output of a respective DRM of the second array of DRMs; and each output pod of the rearrangement AWG connected to an output of the switch module; comprising an additional array of rearrangement Detector Remodulators (DRMs) (Cl) located before the pre-mesh AWG, each DRM of the additional array configured to receive a signal from an input of the switch module (IP1, 1P2, 1PM) and to regenerate and/or change the wavelength of the received signal to produce a DRM output, the DRM output forming an input at a respective port of the rearrangement AWG (02); and comprising a final array of DRM5 (09) after the rearrangement AWG (08) such that the connection between each of the output ports of the rearrangement AWG (CS) and an output port of the switch module is via one of the DRM5 of the final array.Amendments to the claims have been made as follows:CLAIMS1. An optoelectronic switch comprising: N switch modules, where N is an integer; and an optical full-mesh interconnect (05); Each switch module comprising: M client facing input ports, and M output facing ports; a pre-mesh Arrayed Waveguide Grating (AWG) (04), the pre-mesh AWG having M inputs and N outputs, each of the N outputs connected to a respective input on the optical full-mesh interconnect (05); a post-mesh Arrayed Waveguide Grating (AWG) (C6), the post-mesh AWG having N inputs and M outputs, each of the N inputs connected to a respective output of the optical (0 full-mesh interconnect (05) and each of the M outputs for communicating a signal to one or more of the M outputs (OP1, 0P2, OPM) of the switch module; and (4 O a first array of Detector Remodulators (DRM5) (C3) located before the pre-mesh 0) AWG, each DRM of the first array configured to receive a signal from an input of the switch module (IP1, 1P2, 1PM) and to regenerate and/or change the wavelength of the received signal to produce a DRM output, the DRM output forming an input at a respective port of the pre-mesh AWG.2. The optoelectronic switch of claim 1, further comprising a second array of Detector Remodulators (DRM5) (07) located after the post-mesh AWG, each DRM of the second array configured to regenerate and/or convert the wavelength of a signal from a respective output port of the post-mesh AWG for communication to an output port (OP1, 0P2, OPM) of the switch module.3. The optoelectronic switch of claim 2, further comprising a rearrangement Arrayed Waveguide Grating (AWG) (08) located after the second array of DRM5 (07), the rearrangement AWG having M input ports and M output ports, each of the M input ports connected to an output of a respective DRM of the second array of DRM5; and each output port of the rearrangement AWG connected to an output of the switch module.4. The optoelectronic switch of claim 3, further comprising a final array of DRMs (09) after the rearrangement AWG (08) such that the connection between each of the output ports of the rearrangement AWG (08) and an output port of the switch module is via one of the DRM5 of the final array.5. The optoelectronic switch of any one of the preceding claims, further comprising a rearrangement Arrayed Waveguide Grating (AWG) (02) located before the first array of DRM5 (C3), the rearrangement AWG having M input ports and M output ports, each of the M input ports connected to an output of a respective DRM of the second array of DRM5; and each output port of the rearrangement AWG connected to an output of the switch module.6. The optoelectronic switch of claim 5, further comprising an array of rearrangement Detector Remodulators (DRM5) (Cl) located before the pre-mesh AWG, each DRM of the first array configured to receive a signal from an input of the switch module (IP1, 1P2, 1PM) and to regenerate and/or change the wavelength of the received signal to produce a DRM output, the DRM output forming an input at a respective port of the rearrangement AWG (02).C'J 7. The optoelectronic switch of any one of the preceding claims, wherein N>M.8. The optoelectronic switch of any one of claims ito 6, wherein N<M. r.9. The optoelectronic switch of any one of claims 1 to 6, wherein N=M.iO. The optoelectronic switch of claim 1, wherein the optical full-mesh interconnect is an optical backplane.ii. The optoelectronic switch of any one of the preceding claims configured to act as a circuit switch.12. The optoelectronic switch of any one of the preceding claims configured to act as a burst switch i3. The optoelectronic switch of any one of the preceding claims configured to act as a packet switch 14. The optoelectronic switch of any one of the preceding claims configured to act as a cell switch 15. The optoelectronic switch of any one of the preceding claims, wherein the optical full-mesh interconnect has a folded configuration which forms a fold in the optoelectronic switch module, wherein for each optoelectronic switch module: the pre-mesh AWG is located before the fold; and the post-mesh AWG located after the fold.16. The optoelectronic switch of claim 15, wherein the input and output ports of each optoelectronic switch module are all arranged on a single external panel.17. The optoelectronic switch of any one of the preceding claims; wherein the optoelectronic switch is constructed from silicon photonics.18. An optoelectronic switch module for use with an optical full-mesh interconnect, the optoelectronic switch module comprising: M client facing input ports, and M output facing ports, where M is an integer; a pre-mesh Arrayed Waveguide Grating (AWG) (C4), the pre-mesh AWG having M o inputs and N outputs where N is an integer which is either equal to or not equal to M, each of the N outputs connected to a respective input on the optical full-mesh interconnect (05); a post-mesh Arrayed Waveguide Grating (AWG) (06), the post-mesh AWG having N inputs and M outputs, each of the N inputs connected to a respective output of the optical full-mesh interconnect (CS) and each of the M outputs for communicating a signal to one or more of the M outputs of the switch module; and a first array of Detector Remodulators (DRMs) (C3) located before the pre-mesh AWG, each DRM of the first array configured to receive a signal from an input of the switch module (IP1, 1P2, 1PM) and to regenerate and/or change the wavelength of the received signal to produce a DRM output, the DRM output forming an input at a respective port of the pre-mesh AWG.