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GB2520275B - A method of generating a layout of an integrated circuit comprising both standard cells and at least one memory instance - Google Patents

A method of generating a layout of an integrated circuit comprising both standard cells and at least one memory instance Download PDF

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Publication number
GB2520275B
GB2520275B GB1320029.0A GB201320029A GB2520275B GB 2520275 B GB2520275 B GB 2520275B GB 201320029 A GB201320029 A GB 201320029A GB 2520275 B GB2520275 B GB 2520275B
Authority
GB
United Kingdom
Prior art keywords
layout
generating
integrated circuit
standard cells
memory instance
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
GB1320029.0A
Other versions
GB2520275A8 (en
GB2520275A (en
GB201320029D0 (en
Inventor
Yeung Gus
Jay Kinkade Martin
Wayne Frederick Marlin Jr
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
ARM Ltd
Original Assignee
ARM Ltd
Advanced Risc Machines Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by ARM Ltd, Advanced Risc Machines Ltd filed Critical ARM Ltd
Priority to GB1320029.0A priority Critical patent/GB2520275B/en
Publication of GB201320029D0 publication Critical patent/GB201320029D0/en
Publication of GB2520275A publication Critical patent/GB2520275A/en
Publication of GB2520275A8 publication Critical patent/GB2520275A8/en
Application granted granted Critical
Publication of GB2520275B publication Critical patent/GB2520275B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/39—Circuit design at the physical level
    • G06F30/392—Floor-planning or layout, e.g. partitioning or placement
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/39—Circuit design at the physical level
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/39—Circuit design at the physical level
    • G06F30/394—Routing
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/02—Disposition of storage elements, e.g. in the form of a matrix array
    • G11C5/025—Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2111/00—Details relating to CAD techniques
    • G06F2111/20—Configuration CAD, e.g. designing by assembling or positioning modules selected from libraries of predesigned modules

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Evolutionary Computation (AREA)
  • Geometry (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Architecture (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
GB1320029.0A 2013-11-13 2013-11-13 A method of generating a layout of an integrated circuit comprising both standard cells and at least one memory instance Active GB2520275B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
GB1320029.0A GB2520275B (en) 2013-11-13 2013-11-13 A method of generating a layout of an integrated circuit comprising both standard cells and at least one memory instance

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
GB1320029.0A GB2520275B (en) 2013-11-13 2013-11-13 A method of generating a layout of an integrated circuit comprising both standard cells and at least one memory instance

Publications (4)

Publication Number Publication Date
GB201320029D0 GB201320029D0 (en) 2013-12-25
GB2520275A GB2520275A (en) 2015-05-20
GB2520275A8 GB2520275A8 (en) 2015-07-22
GB2520275B true GB2520275B (en) 2020-03-18

Family

ID=49818560

Family Applications (1)

Application Number Title Priority Date Filing Date
GB1320029.0A Active GB2520275B (en) 2013-11-13 2013-11-13 A method of generating a layout of an integrated circuit comprising both standard cells and at least one memory instance

Country Status (1)

Country Link
GB (1) GB2520275B (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2022266956A1 (en) * 2021-06-24 2022-12-29 华为技术有限公司 Chip layout method and apparatus

Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5210701A (en) * 1989-05-15 1993-05-11 Cascade Design Automation Corporation Apparatus and method for designing integrated circuit modules
WO2006052738A2 (en) * 2004-11-04 2006-05-18 Fabbrix, Inc. A method and process for design of integrated circuits using regular geometry patterns to obtain geometrically consistent component features
US20060243955A1 (en) * 2005-04-19 2006-11-02 Yukihiro Fujimoto Semiconductor integrated circuit device
US20080028351A1 (en) * 2006-07-26 2008-01-31 Taiwan Semiconductor Manufacturing Co., Ltd. Memory macro with irregular edge cells
US20100155783A1 (en) * 2008-12-18 2010-06-24 Law Oscar M K Standard Cell Architecture and Methods with Variable Design Rules
US20110041109A1 (en) * 2009-08-12 2011-02-17 Taiwan Semiconductor Manufacturing Company, Ltd. Memory building blocks and memory design using automatic design tools
US20120209888A1 (en) * 2011-02-15 2012-08-16 Chung Shine C Circuit and Method of a Memory Compiler Based on Subtraction Approach
US20120254817A1 (en) * 2011-03-30 2012-10-04 Synopsys, Inc. Cell Architecture for Increasing Transistor Size

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5210701A (en) * 1989-05-15 1993-05-11 Cascade Design Automation Corporation Apparatus and method for designing integrated circuit modules
WO2006052738A2 (en) * 2004-11-04 2006-05-18 Fabbrix, Inc. A method and process for design of integrated circuits using regular geometry patterns to obtain geometrically consistent component features
US20060243955A1 (en) * 2005-04-19 2006-11-02 Yukihiro Fujimoto Semiconductor integrated circuit device
US20080028351A1 (en) * 2006-07-26 2008-01-31 Taiwan Semiconductor Manufacturing Co., Ltd. Memory macro with irregular edge cells
US20100155783A1 (en) * 2008-12-18 2010-06-24 Law Oscar M K Standard Cell Architecture and Methods with Variable Design Rules
US20110041109A1 (en) * 2009-08-12 2011-02-17 Taiwan Semiconductor Manufacturing Company, Ltd. Memory building blocks and memory design using automatic design tools
US20120209888A1 (en) * 2011-02-15 2012-08-16 Chung Shine C Circuit and Method of a Memory Compiler Based on Subtraction Approach
US20120254817A1 (en) * 2011-03-30 2012-10-04 Synopsys, Inc. Cell Architecture for Increasing Transistor Size

Also Published As

Publication number Publication date
GB2520275A8 (en) 2015-07-22
GB2520275A (en) 2015-05-20
GB201320029D0 (en) 2013-12-25

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