GB2512641A - SRAM array comprising multiple cell cores - Google Patents

Abstract

An SRAM array 100 comprising multiple cell cores 102, 104, 106, 108 to store and retrieve data, each cell core comprising a plurality of SRAM cells 112, and wherein at least two corresponding cell cores 102, 104 and 106, 108 build a cell core row 122. A word decoder 110 configured to decode incoming address signals 116 representing a storage address into a single word line 114, so that one storage word is activated. The word decoder 110 comprises, a cell core select unit (306, figure 3) configured to generate a cell core row select signal (402, figure 4) from a combination of a first part (412) of the incoming address signals 116 and a received clock signal (308, figure 4), a decoding element (302, 304, figure 4) for each cell core row 122, the decoding element comprising a first decoding block (404, figure 4) for decoding a second part (414, figure 4) of the incoming address signals 116 for building an upper portion (408) of word line select signals (422) and a second decoding block (406 figure 4) for decoding a third part (416) of the incoming address signals 116 for building a lower portion (410, figure 4) of word line select signals (422), a word line driver (418, 420) for each cell core row (122) configured to combine the upper portion (408) of the word line select signal (422) from the first decoding block (404) and the lower portion (410) of the word line select signal (422) from the second decoding block (406) to form a unique word line signal 114 per storage address.

Description

DESCRIPTION

SHAM ARRAY COMPRISING MULTIPLE CELL CORES

FIELD OF THE INVENTION

The invention relates generally to an SRAN array oomprising multiple cell cores. The invention relates further to a method for operating an SRAM array.

BACKGROUND OF THE INVENTION

Static random access memory (SRAM) cells are currently used in many application scenarios to store data. Speed of access is a critical parameter for such SRAM cells. When designing a multi GHz SRA}4, power consumption is a critical aspect without sacrificing performance in terms of frequency, width, i.e., word size and depth, i.e., word count.

A strong contributor to power consumption is a word decoder allowing to access single words based on an incoming word address. The word decoder decodes a binary address into single Physically, SRAMs usually get partitioned into multiple SRAM cell core regions to cope with the physical wiring length of the word lines as well as with the physical wiring length of the bit lines on the memory chip. Bit lines are used to read-out stored data and write data into the SRAM cells. Both may not exceed a certain physical length due to physical implications.

Today's decoders will send all their pre-decoded signals to the last decoding stage, in particular a word line driver, located at each ccre region. This means that all pre-decoded signals may be toggling at all word line drivers even if only one of them may be aotivated. Typically, this may result in unnecessary power consumption.

As power density inoreases with eaoh CMOS technology node and logic demands for larger high frequency SRAMs continue to grow, this decoding scheme may no longer be suitable. It may result in reliability issues due to power supply, lifetime problems because of electro migration and performance impacts due to the high amount of capacitance (load) reguired to drive the lines.

There are several disclosures related to an SRAM array comprising multiple cell cores.

Document US813O588A1 discloses a semiconductor memory device inoluding a memory cell array arranged in rows and columns, a row decoder and a control circuit. The control circuit generates the internal clock signal so that the row decoder does not operate for a predetermined time in response to the chip select signal.

Document US 2012/0285664A1 discloses a system and method for adjusting timing of memory access operations to a memory block.

A controller may be adapted to adjust timing of a memory access operation to the memory block by extending a portion of a clock pulse to compensate for delay associated with the memory block.

However, there may be a further need to overcome the speed issues of SHAM cells combined with power consumption limitations. The industry has clearly a need for even high 0Hz CRAM cells requiring less power and thus, a need for an increased lifetime of those CRAM cells.

SUMMARY CF THE INVENT ION

This need may be addressed by an SHAM array comprising multiple cell cores, and a method for operating an SRAM array according to the independent claims.

According to one embodiment, an SRAI4 array comprising multiple cell cores may be provided. The multiple cell cores may be used to store and retrieve data. Each oell core may comprise a plurality of SRAM cells, wherein at least two corresponding cell cores may build a cell core row. A word decoder may be configured to decode incoming address signals -which may represent a storage address -into a single word line so that one storage word may be activated.

The word decoder may comprise a cell core select unit which may be configured to generate a cell core row select signal from a combination of a first part, in particular the MSB (most significant bit) of the incoming address signals and a received clock signal. A decoding element for each cell core row may comprise a first decoding block for decoding a second part -in particular F4SBs apart from first part of the address -of the incoming address signals for building an upper portion -in particular, an MSB part -of word line select signals -in particular the MSB portion -and a second decoding block for decoding a third part -in particular the least significant bits (USE) -of the incoming address signals for building a lower portion -in particular the IJSB portion -of word line select signals. In particular, both portions may not have to be equal in data signal line numbers.

A word line driver for each cell core row as part of the word decoder may be configured to combine the upper portion of the word line select signal from the first decoding block and the lower portion of the word line seleot signal from the second decoding block to form a unique word line signal per storage address -in particular, the word line driver may "decode and drive" the word lines in a combined function.

According to another embodiment, a method for operating an SRAM array may be provided. The method may comprise storing and retrieving data using multiple cell cores, wherein each cell core may comprise a plurality of SRAM cells. At least two corresponding cell cores may build a cell core row. The method may also comprise configuring a word decoder to decode incoming address signals representing a storage address into a single word line so that one storage word may be activated.

The word decoder may comprise generating a cell core row select signal ising a cell core select unit from a combination of a first part of the incoming address signals and a received clock signal.

The method may further comprise deploying a decoding element for each cell core row. The decoding element may comprise using a first decoding block for decoding a second part of the incoming address signals for building an upper portion of word line select signals and using a second decoding block for decoding a third part of the incoming address signals for building a lower upper portion of word line select signals.

Furthermore, the method may comprise configuring a word line driver for each cell core row to combine the upper portion of the word line select signal from the first decoding block and the lower portion of the word line select signal from the second decoding block to form a unique word line signal per unique storage address.

DETAILED DESCRTPTION

In the context of this description, the following conventions, terms and/or expressions may be used: The term "SEAM array" may denote an array of static random access memory cells. The array may be organized in sub-arrays which may only comprise subgroups of SEAM cells crganized in rows and columns. Such a subgroup may denote a cell core. Such cell cores of SEAM cells may also be organized in rows and columns. Thus, several cell cores may build a "cell core row".

The term "store and retrieve data" may denote writing data in memory cells and reading the once stored information as it may be known by a skilled person.

A "storage word" may be a combination of a series of bits organized as one storage word for a combined access to all bits of such storage word. Typical storage word lengths may be equal to the power of 2. However, modern computing chips may have any storage word length.

The term "word decoder" may denote an electronic circuit adapted to select individual storage words. Once a storage word may have been selected, information may be written into the word or read from the storage word. In order to select a storage word, the word decoder needs input signals in form of address signals.

The term "address signals" may denote a combination of signals on different physical lines to uniquely identify a memory cell.

Each signal combination on the address lines may be decodable into a single storage word address or storage address.

The term "bit line" may denote a line combining input ("write") and output ("read") signals from corresponding bits of different storage bits in a storage word. However, if only one word may be addressed at a time, the bit lines may have the logical statuses of the bits of the addressed storage word. The same number of bit lines may be required as the word may have bits in order to read out or write to a storage word. The bits per word may be spread over several cell cores.

In oontrast, the term "word line" may denote a line required to activate all cells of a storage word for access, i.e., read or write.

The term "storage word" may denote a series of storage bits building one storage word.

The term "cell core select unit" may denote an electronic circuit adapted to activate individual cell cores. It may be required to activate several cell cores of SRAN sub-arrays in order to activate a complete storage word.

The term "cell core row select signal" may denote a signal adapted to activate all cell cores building one cell core row.

Typically, all cell cores of such a cell core row may be reguired in order to read a storage word.

The term "first part of incoming address signals" may denote one portion of incoming address signals. Typically, the most significant bit or bits may be used as first part.

The term "clock signal" may denote a clock signal available as part of a computer system, computer subsystem or individual chip, in particular a memory chip like an SRIM array. However, individ-nal components may have different clock speed. Here, the clock signal may denote the clock signal available for the SRAM array.

The term "decoding element" may denote a sub-part of the word decoder adapted to address a cell core row of SRAM cells. There may be several deooding elements as part of the word decoder for different cell core rows.

The term "word line driver" may denote a driver for selecting a line addressing and activating a single word for a read or write operation. The word line driver may activate a line carrying a The term "most significant bits" (MSB5) may denote the higher order bits of parallel organized words, or addresses, or lines.

The term "least significant bits" (LSB5) may denote the lower order bits of parallel words, or addresses, or lines.

The term "half word select signal" may denote a special select signal which may not select a complete word with its full word length, but only a part of the bits of a word. This may be a half word comprising only 50% of the bits of a word or only the lower or the upper portion of a storage word. The half word select signal may be used to activate only one cell core or a subset of the cell cores of a cell core row. In particular, also smaller portions of a word -e.g., a quarter word or other portions of a storage word -may be selectable under a strict power regime, meaning that even more power may be saved within the SRAI4 array.

The proposed SRAM array comprising multiple cell cores may offer a couple of advantages: The inventive concept described here may eliminate the problem of excessively high power consumption of SRAM array operating at very high frequencies. This may be achieved by a pre-deccding of a core select signal from the input address and a combination of it with a clock signal of the word decoder. This newly built cell core row select signal may cnly be active for the accessed core region, being built out of one or more cell cores. It may be sent to a first stage of pre-decoders and may activate only the set necessary to access the desired core region. This may reduce the amount of power reguired without affecting the access time to launch a word line. The inventive concept may also have the advantage to only activate cell cores comprising portions of a word, e.g., the upper part or the lower part of the word if a word may be split into two cell cores.

It may be clear that the cell core row select signal may at the same time be the clock signal for individual and active portions of the decoder. Those areas of the decoder not reguired for decoding a specific address may not receive the modified clock signal at all. Without a clock signal that individual portion of the decoder may not be active and thus, not require any power or much less power than with a clock signal. So, in addition to the modified clock signal no additional wiring and/or signal qeneration may be required in order to put the individual portions of the decoder into a sort of sleep mode. Only the active portions required to decode the address signals may receive a clock signal -i.e. the cell core row select signal -and be active.

According to one embodiment of the SRAM array, word-wise organized data may be stored in two relating cell cores building the core cell row, such that one portion of the word-wise organized data are stored in storage cells of a first cell core of the core cell row and the remaining portion of the word-wise organized data may be stored in a storage cell of a corresponding second cell core of the core cell row. Thus, the word to be stored may be split into two parts/halves, wherein each part of the storage word may be stored in one of the two cell cores. This may allow shorter word lines per driver, thus less reguired charge per word line and conseguently less power consumption.

According to one embodiment of the SRAM array, the one portion of the word-wide organized data and the remaining portion of the word-wide organized data may be equal in size. This may be a natural split of a word into different cell cores. However, more cell cores per word may be possible.

According to an alternative embodiment of the SRAM array, the word-wise organized data may be stored in four corresponding cell cores building a core cell row, such that a first portion of the word-wise organized data may be stored in a first cell core of the core cell row, a second portion of the word-wise organized data may be stored in a second cell core of the core cell row, a third portion of the word-wise organized data may be stored in a third cell core of the core cell row and the remaining portion of the word-wise organized data may be stored in a fo-nrth cell core of the core cell row. Thus, a storage word may be split into four parts. Each part of the word may be stored in a different cell core. A skilled person may understand that more cell cores per word may be implemented.

According to a further embodiment of the ShAM, the most significant bits of the word-wise organized data may be stored in the first cell core and the least significant bits of the word-wise organized data may be stored in the second cell core.

In an alternative configuration, a storage word may be spread over foir or more cell cores which may require organizing the split of the word in an eguivalent way. Thus, storage words may be spread across different cell cores keeping required wiring physically shcrt. This may require less charge tc active the related lines. Thus, additional energy or power may be saved.

According to one additicnal embodiment of the SRAM array, the combining the upper portion and the lower portion of word line select signal to form a unique word line signal per storage address may comprise combining pair-wise one upper porticn signals from the first decoding block and one lower portion signal from the second decoding block. This technique has been proven to be an efficient way to generate signals for the word lines. A driver for each word line may also be included in the electronic combination circuitry of the upper and lower portion signals.

According to an advanced embodiment of the SRAJYI array, the word decoder may be adapted to address more than two cell core rows.

Thus, a more advanced SHAM array may be built comprising more storage cells allowing increasing the storage capacity, and at the same time, contributing to power savings for the SRAM array.

In one embodiment of the SRAM array, the word line driver may comprise separate units for decoding the output signals from the first decoding block and the second decoding block and for driving the word lines. This way different chip technologies may be used for the different components. One component may be optimized for low power consumption and speed and the other part may be optimized for maximum output to drive the word lines.

According to a further advanced embodiment of the SRAM array, the cell core select unit may be configured to receive a half word select signal and selectively activate only one of the cell cores of a cell core row. In case a cell core row comprises two cell cores, a half-word may be selected. In this case, the other cell core may not be activated at all saving even more power. In case there may be more than two core cells per cell core row, also quarter words or even smaller parts of a storage word may be selected. Typically, the number of cell cores per cell core row and the number of sub-part of a storage word may correspond to each other.

It should also be noted that embodiments of the invention have been described with reference to different subject-matters. In particular, some embodiments have been described with reference to method type claims, whereas other embodiments have been described with reference to apparatus type claims. However, a person skilled in the art will gather from the above and the following description that, unless otherwise notified, in addition to any combination of features belonging to one type of subject-matter, also any combination between features relating to different subject-matters, in particular, between features of the method type claims, and features of the apparatus type claims, is considered as to be disclosed within this document.

The aspects defined above and further aspects of the present invention are apparent from the examples of embodiments to be described hereinafter and are explained with reference to the examples of embodiments, but to which the invention is not limited.

BRIEF DESCRIPTION OF THE DRAWINGS

Preferred embodiments of the invention will now be described, by way of example only, and with reference to the following drawings: Fig. 1 shows a block diagram of an embodiment of the inventive SRAM array.

Fig. 2 shows a block diagram of deooding elements according to the state of the art.

Fig. 3 shows a block diagram of an embodiment of the inventive SRAM array in more detail.

Fig. 4 shows a block diagram of an embodiment of elements of the pre-decoding units.

Fig. 5 shows a block diagram of an embodiment of a part of the core cell select unit with a plurality of core cells.

Fig. 6 shows an embodiment of the method for operating an SRAI4 array.

In the following, a detailed description of the figures will be given. All instructions in the figures are schematic. Firstly, a block diagram of an embodiment of the inventive SRAM array comprising multiple cell cores is given. At the end, an embodiment of the method for operating an SRPM array will be described.

Fig. 1 shows a block diagram of an embodiment of the inventive SRAI4 array. The SRAM array 100 may comprise a plurality of SRAM cell cores 102, 104, 106, 108 comprising a plurality of SRAM cells 112. For instance, all SRAM cells in one horizontal line may define a word in the memory defined by the SRAF4 array in which data words composed out of data bits may be stored and retrieved. Consequently, the at least two corresponding cell cores 102, 104 or 106, 108 may build a cell core row 122. The SRAI4 cells 112 of one memory word 120 may be addressed by a word line which may activate all SRAM cells 112 belonging to one word. Once activated, these SRAM cells may signal their status on the bit lines 118. It may be noted that a reference numeral for the bit lines is only shown for cell core 102. A skilled person will understand that also the other cell cores have corresponding bit lines.

A word decoder 110 may be configured to decode incoming address signals 116 -representing a storage address -into a single word line 114 so that one storage or memory word may be activated or selected or addressed.

Fig. 2 shows a block diagram of decoding elements according to the state of the art. The incoming address signals 216 may be decoded by the word decoder 210. Each address line combination may be translated to a single word line 214. The SRAN cells 212 in a cell core 204, which may belong to a storage word, may be selected or activated by the word line 214. Once activated, the data may be read from, or written to, the individual SRAM cells of the word via the bit lines 210.

Fig. 3 shows a block diagram of an embodiment of the inventive SRAF4 array in more detail. Firstly, the word decoder 110 may comprise a cell core select unit 306. The address signals 116 may be fed to the cell core select unit. It should be clear that a specific storage word may either be locatable in one of the two core cell rows being built by either cell cores 102 and 104, or cell cores 106 and 108. The task of the cell core select unit 306 may only activate those cell cores that are relevant for activating the selected storage word. The other cell cores may uot be selected. Thus, the corresponding decoding elements may uot be active at all. The cell core select unit 306 may function as a pre-selection for activating relevant decoding elements 302 or 304. If, e.g., a storage word may be addressable by wcrd line related to the cell cores 102 and 104, the decoding element 304 may stay inactive. This may have the advantage to save energy and operate the SRAM array more effectively. The same may apply for the word hue drivers 310. Only those word line drivers may be activated that may be relevant for activating the selected/addressed storage word. This may be important because the word line may be pretty long and thus, may require a lot of charge to activate the physically long wire to reach the last SRAI4 cell belonging to the storage word to be addressed.

Hence, the cell core select unit 306 may be configured tc generate a cell core row select signal (cf., Fig. 4) from a combination of a first part of the incoming address signals 116 and a received clock signal 308. The clock signal 308 may also be fed to the cell ccre select unit 306.

Fig. 4 shows a block diagram of an embodiment of elements of the decoding elements 302, 304 of Fig. 3, respectively. There may be one decoding element for each cell core row (exemplarily shown only for one cell core row 122 in Fig. 1) . Each decoding element 302, 304 of Fig. 3 may comprise a first decoding block 404 for decoding a second part 414, in particular an MSB part frcm first part of the incoming address signals 116 for building an upper portion 408, in particular an MSB portion, of word line select signals 422. Each decoding element 302, 304 of Fig. 3 may also comprise a second decoding block 406 for decoding a third part 416, in particular an LSE part, of the incoming address signals 116 for building a lower portion 410, in particular an LOB portion of word line select signals 422. A first part 412 of the address signals, in particular the primary NOB 412 or bits, may be used as input signal for the cell core select unit 306. This bit, respectively these bits, may also be called "cell ccre select bit". As second input, the cell core select unit 306 may receive the clock signal 308 of the SRAM array. Out of these two signals 412 and 308, a cell core row select clock 402 may be generated. Fig. 4 shows only one cell core row select clcck line 402. For more cell cores, multiple lines 402 may be required.

It may be understood that each cell core row may have its own cell core row select clock line which actually may also be referred to as pre-decoding clock. Thus, only those cell core rows may receive a cell core row select clock line 402 that may be activated to activate a specific word line addressed by the incoming address signals 116.

The word line select signals 422 may then be logically combined to build a word line that may be specific for a unique storage word. This may be referred to as last stage decoding' . Finally, a word line driver 418, 420 may function as an amplifier of the signals 422 to drive the word lines 114 for the right and the left cell core 102, 104 (of. Fig. 3) of the SRAM array 100.

The word line driver 418, 420 for each cell core row may be configured to combine the upper portion 408 of the word line select signal 422 from the first decoding block 404 and the lower portion 410 of the word line select signal 422 from the second decoding block 406 to form a word-wise unique word line signals 114a, 114b per storage word address. In particular, the word line driver 418, 420 may each be configured for decoding and driving the word lines 114 in a combined function. In another embodiment, these two functions may be separated. It may also be clear that for power saving reasons for an addressed half word only one of the two word line drivers 418 or 420 may be activated. The cell core row select clock signal 402 may be repurposed for this.

As the example shows, there are eight address bits: 412, 414, 416. The F4SB may be used from -together with the clock signal 308 -the cell core row select signal or clock 402. The cther three MSBs 414 may be used to decode eight address lines 408.

The remaining four LSBs 416 may be used to decode 16 address lines 410. To decode the "real" word line 114a and 114b, a oombination of the lines 408 and 410 may be built such that always one line from each group 408 and 410 may logically be combined.

Fig. 5 shows a block diagram of an embodiment of a part of the core cell select unit with more a plurality of core cells. Here, four cores 502, 504, 506, 508 may be configured for the decoding element 302 as part of the word decoder 110. The storage words may now not be split on two parts as on Fig. 1 and 3 but in 4 parts b-iilding a cell core row 522. Tn one example of a split, a storage word may be divided in 4 egually large sub storage words. iach part may be stored in one core cell 502, 504, 506, 508. Each core cell may have an associated word line driver 310.

The data-in and data-out into/out-of the individual SRAN cells may be organized via bit lines 118, as described above. Such architecture may have the advantage that the individual word line may be physically smaller and may thus require less charge, and thus less power, for activation. The overall SRAM array may reguire less energy to be operated. It may be noted that in Fig. only one word line 114 may be shown exemplarily with a reference numeral.

A skilled person may understand that a storage word may be split across even more cell cores, e.g., six or eight, or even more.

A split of a storage word into, e.g., two parts may have another advantage: It may be possible to address only half storage words. A special signal half word select signal", fed to the decoding element from either the core cell select unit or from another side, may activate only half a decoding element, i.e., one decoding block and related word line drivers. This way, the power consumption of the SRAM array may further be reduced. Such architecture may be advantageous if, e.g., ASCII text may be stored in long or very long storage words. In that case, single characters may be activated as a partial storage word.

Fig. 6 shows an embodiment 600 of the method for operating an SRAI4 array. The method 600 may comprise storing and retrieving 602 data using multiple oell cores. Each oell core may comprise a plurality of SRAI1 cells. At least two corresponding cell cores may build a cell core row, as described above.

The method may also comprise configuring 604 a word decoder to decode incoming address signals representing a storage address into a single word line, so that one storage word may be activated.

The word decoder may be adapted for generating 606 a cell core row select signal using a cell core select unit from a combination of a first part of the incoming address signals and a received clock signal, as well as deploying 608 a decoding element for each cell core row.

The decoding element may be adapted for using 610 a first decoding block for decoding a second part of the incoming address signals for building an upper portion of word line select signals. Furthermore, the decoding element may be adapted for using 612 a second decoding block for decoding a third part of the incoming address signals for building a lower portion of In addition, the method may comprise configuring 614 a word line driver for each cell core row in order to combine the upper portion of the word line select signal from the first decoding block and the lower portion of the word line select signal from the second decoding block to form a unique word line signal per storage address.

While the invention has been described with respect to a limited number of embodiments, those skilled in the art, having benefit of this disclosure, will appreciate that other embodiments may be devised, which do not depart from the scope of the invention, as disclosed herein. Accordingly, the scope of the invention should be limited only by the attaohed claims. Also, elements described in association with different embodiments may be combined. It should also be noted that reference signs in the claims should not be construed as limiting elements.

As will be appreciated by one skilled in the art, aspects of the present disclosure may be embodied as a system, method or computer program product. Accordingly, aspects of the present disclos-jre may take the form of an entirely hardware embodiment, an entirely software embodiment (including firmware, resident software, micro-code, etc.) or an embodiment combining software and hardware aspects that may all generally be referred to herein as a "circuit," "module" or "system." Furthermore, aspects of the present disclosure may take the form of a computer program product embodied in one or more computer readable medium(s) having computer readable program code embodied thereon.

Aspects of the present disclosure are described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems) and computer program products according to embodiments of the present disclosure. It will be understood that each block of the flowchart illustrations and/or block diagrams, and combinations of blocks in the flowchart illustrations and/or block diagrams, may be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions/acts specified in the flowchart and/or block diagram block or blocks.

The block diagrams in the Figures illustrate the architecture, functionality, and operation of possible implementations of systems, methods and computer program products according to various embodiments of the present disclosure. In this regard, each block in the block diagrams may represent a module, segment, or portion of code, which comprises one or more executable instructions for implementing the specified lcgical function (s) . It should also be noted that, in some alternative implementations, the functions discussed hereinabove may occur out of the disclosed order. For example, two functions taught in succession may, in fact, be executed substantially concurrently, or the functions may sometimes be executed in the reverse order, depending upon the functionality involved. It will also be noted that each block of the block diagrams, and combinations of blocks in the block diagrams, may be implemented by special purpose hardware-based systems that perform the specified functions or acts, or combinations of special purpose hardware and computer instructions.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit of the invention. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.

The corresponding structures, materials, acts, and equivalents of all means or steps plus function elements in the claims below are intended to include any structure, material, or act for performing the function in combination with other claimed elements, as specifically claimed. The description of the present invention has been presented for purposes of illustration and description, but is not intended to be exhaustive or limited to the invention in the form disclosed.

Many modifications and variations will be apparent to those of ordinary skills in the art without departing from the scope and spirit of the invention. The embodiment was chosen and described in order to best explain the principles of the invention and the practical application, and to enable others of ordinary skills in the art to understand the invention for various embodiments with various modifications, as are suited to the particular use contemplated.

Claims (10)

1. CLAIMS1. An SRAN array (100) comprising -multiple cell cores (102, 104, 106, 108) to store and retrieve data, wherein each cell core (102, 104, 106, 108) comprises a plurality of SRAI1 cells (112), and wherein at least two corresponding cell cores (102, 104; 106, 108) build a cell oore row (122), -a word decoder (110) configured to decode incoming address signals (116) representing a storage address into a single word line (114), so that one storage word is activated, the word decoder (110) comprising, -a cell core select unit (306) configured to generate a cell core row select signal (402) from a combination of a first part (412) of the incoming address signals (116) and a received clock signal (308), -a decoding element (302, 304) for each cell core row (122), the decoding element (302, 304) comprising -a first decoding block (404) for decoding a second part (414) of the incoming address signals (116) for building an upper portion (408) of word line select signals (422) and a second decoding block (406) for decoding a third part (416) of the incoming address signals (116) for building a lower portion (410) of word line select signals (422), -a word line driver (418, 420) for each cell core row (122) configured to combine the upper portion (408) of the word line select signal (422) from the first decoding block (404) and the lower portion (410) of the word line select signal (422) from the second decoding block (406) to form a unique word line signal (114) per storage address.
2. 2. The SRAM array (100) according to claim 1, wherein word-wise organized data (120) are stored in two relating cell cores (102, 104) building the core cell row (122), such that one portion of the word-wise organized data is stored in a first cell core (102) of the core cell row (122) and the remaining portion of the word-wise organized data (120) is stored in a corresponding second cell core (104) of the core cell row (122.
3. 3. The SRAM array (100) according to claim 2, wherein the one portion of the word-wide organized data and the remaining portion of the word-wide organized data are equal in size.
4. 4. The SRAM array (100) according to claim 1, wherein word-wise organized data (120) are stored in four corresponding cell cores (502, 504, 506, 508) building a core cell row (522), such that a first portion of the word-wise organized data (120) is stored in a first cell core (502) of the core cell row (522), a second portion of the word-wise organized data (120) is stored in a second cell core (504) of the core cell row (522), a third portion of the word-wise organized data (120) is stored in a third cell core (506) of the core cell row (522) and the remaining portion of the word-wise organized data (120) is stored in a fourth cell core (508) of the core cell row (522)
5. 5. The SRAM array according to claim 2 or 3, wherein most significant bits of the word-wise organized data (120) are stored in the first cell core (102) and least significant bits of the word-wise organized data (120) are stored in the second cell core (104)
6. 6. The SRAM array (100) of any of the preceding claims, wherein the combining the upper portion (408) and lower portion (410) of word line select signals to form a unique word line signal (114) per storage address comprises -combining pair-wise one upper portion (408) signals from the first decoding block (404) and one lower portion (410) signal from the second decoding block (406)
7. 7. The SRAM array (100) of any of the preceding claims, wherein the word decoder (110) comprises more than two cell core rows (122, 502)
8. 8. The SRAM array (100) of any of the preceding claims, wherein the work line driver (418, 420) comprises separate units for decoding the output signals from the first decoding block (404) and the second decoding block (406) and for driving the word lines (114)
9. 9. The SRAM array (100) of any of the preceding claims, wherein the cell core select unit (306) is configured to receive a half word select signal and selectively activate only one of the cell cores (102, 104) of a cell core row (122, 522)
10. 10. A method (600) for operating an SRAM array (100), the method (600) comprising -storing and retrieving (602) data using multiple cell cores (102, 104, 106, 108), wherein each cell core (102, 104, 106, 108) comprises a plurality of SRAF4 cells (112)), and wherein at least two corresponding cell cores (102, 104; 106, 108) build a cell core row (122), -configuring (604) a word decoder (110) to decode incoming address signals (116) representing a storage address into a single word line (114) so that one storage word is activated, the word decoder (110) comprising, -generating (606) a cell core row select signal (402) using a cell core select unit (306) from a combination of a first part (412) of the incoming address signals (116) and a received clock signal (308), -deploying (608) a decoding element (302, 304) for each cell core row (122), wherein the decoding element (302, 304) is adapted for, -using (610) a first decoding block (404) for decoding a second part (414) of the incoming address signals (116) for building an upper portion (408) of word line select signals (422) and using (612) a second decoding block (406) for decoding a third part (416) of the incoming address signals (116) for building a lower portion (410) of word line select signals (422), -configuring (614) a word line driver (418, 420) fcr each cell core row (122) to combine the upper portion (408) of the word line select signal (422) from the first decoding block (404) and the lower portion (410) of the word line select signal (422) from the second decoding block (406) to form a unigue word line signal (114) per storage address.