GB2506141A - Distributed power semiconductor device - Google Patents

Abstract

A MOS-controlled power semiconductor device 19 has an array of semiconductor cells on a substrate which is sub-divided into a plurality of sub-arrays or cell groups 20a-d which may have equal or unequal areas. Each sub-array has a central gate connector 22a-d to which a plurality of cells is connected in parallel by a gate runner structure 24, providing a distributed gate for each sub-array. The cells in each sub-array are mutually electrically isolated from the cells in further sub-arrays because the gate runner structures or cathode materials for each sub-array are mutually electrically isolated. The sub-arrays may be controlled by a common gate driver or individually controlled. There may be more than one or an unequal number of gate connectors for each sub-array.

Description

Distributed Semiconductor Device The present invention relates to power semiconductor devices.

Power semiconductor devices are conventionally used as switches or rectifiers in power electronics circuits. Such devices can be found as discrete components for low power applications as well as in power modules for medium and high power applications. Medium to high power applications may include, for example, power management, electric fuel cells, electric/hybrid vehicles, traction, Flexible AC Transmission Systems (FACTS), High Voltage DC (HVDC) applications, etc. Metal Oxide Semiconductor (MOS) controlled devices are the most commonly used in power semiconductor applications. Metal Oxide Semiconductor Field Effect Transistors (MOSFETs) and Insulated Gate Bipolar Transistors (IGBTs) are both common types of Metal Oxide Semiconductor (MOS) device.

Electrically driven switches can be categorised as either voltage-controlled or current-controlled devices. Voltage-controlled MOS devices are generally considered to allow a simplified drive circuit when compared to current controlled devices such as the Bipolar Junction Transistor (BJT). MOS controlled power semiconductor devices work in two states, on and off. The devices can be made to electrically conduct when an appropriate gate voltage, larger than the threshold voltage, is applied to a gate contact. The gate voltage can then be reduced below to cut off this conducting current.

Power devices are typically designed to have as low on-state' and switching' losses as possible; this then increases the efficiency and performance of the device and overall system. Low on-state' losses are characterised by low on-resistance, and low switching losses are defined by fast turn-on' and turn-off' times.

The structure of conventional power semiconductor devices is vertical or planar.

Vertical semiconductor devices are generally considered to exhibit greater blocking voltage and current handling ability. As a result, they are generally used in medium to large power applications. Within the vertical structure, the component area is roughly proportional to the current it can sustain, and the component thickness relates to the breakdown voltage A schematic cross-sectional view through a conventional vertical IGBT power device unit cell structure is shown in Figure 1. The device gate 2 is made from a layer of polycrystalline silicon (poly-Si) that is electrically isolated from the active region of the device below it by a thin oxide layer 4. The gate 2 is provided in cathode 6, which is spaced from the anode 8 by a conventional semiconductor material.

Within a so-called three-terminal device, the state of the device is governed not only by the external power circuit but also the signal on the driving terminal (i.e. the gate).

The IGBT is operated in the same way as a power MOSFET by applying a positive gate voltage that is larger than the threshold voltage. This forms an inversion layer under the gate oxide, which connects n+ cathode to n-drift. This allows electrons to flow into the n-drift region when a positive voltage is applied to anode contact.

The electron current serves as a base current for the PNP transistor, promoting injection of holes from p+ anode to n-drift causes conductivity modulation in the drift region, where both the electron and hole densities are increased abruptly compared to the background density. This significantly reduces voltage drop as compared to a power MOSFET, which uses unipolar conduction.

As will be appreciated by the skilled person, the behaviour of the device will be determined by its fabrication. In the example of Fig. 1, the IGBT is the same layout as a double diffused power vertical MOSFET except that the n-'-drain (located at the bottom of the substrate) is replaced by a p+ layer, which forms the anode. The p+ anode, n-drift and p base form a BJT with a low current gain due to the wide n-drift base. From its equivalent circuit diagram, it can also be considered as a p-n-p transistor with its base current controlled by an n-channel MOSFET, which is located on the top of the structure and formed by n-'-, p base and n-drift regions.

In a conventional power semiconductor device, a number of cells of the type shown in Fig. 1 are connected in parallel so as to form the overall device structure.

Figure 2 is a top view of a typical power device. A grid-like pattern of, typically polycrystaffine silicon, gate runners 10 is provided so as to provide a common connection to all of the individual unit cells. The cells are provided in the form of a two-dimensional array on a substrate 12, the array typically being bounded by an edge termination structure 14 about its perimeter.

The current rating of the power device depends upon the number of cells (and hence active area size). There is a trend to reduction of individual cell sizes, for example using techniques such as fine lithography, and to increase the number of cells per unit area, thereby enhancing electron current.

A gate pad 16 is employed to facilitate electrical connection from the MOS controlled device to the terminal 18 of the device-package. The gate runner structure 10 connects the individual gate electrodes within the device to a single gate pad 16 so as to form the overall MOS gate structure.

It has been identified that variations in gate impedance across a device may affect device performance. When a gate voltage is applied or removed to or from the device package termination (or pin) in order to turn the device on or off, there is a time-delay associated with the voltage response at the appropriate cell that is dependent on the impedance and therefore distance of the electrical connection from the pin to the appropriate cell. This then creates a non-uniform distribution of instantaneous impedance between the anode and cathode of device cells during a switching transition or fault condition.

The divergence in the instantaneous cell voltages across the active area of the device causes differences in the instantaneous device currents and consequently uneven temperature distribution across the device.

Local temperature increases the device may cause damage to individual cells. The effect is magnified in operation by repeated switching operations and/or short circuit fault conditions. This effect is also exacerbated by the trends in modern devices toward increased power density and higher operating temperature.

Significant in-homogeneity of current distribution occurs at higher temperatures due to the positive temperature coefficient of resistance of Poly-Si.

Inhomogeneous current and the associated hot spots may also influence yield, maximum die-size, reliability and safe operating area (SOA). These factors ultimately limit the scalability of the power device.

In view of the above problems, there is a need to provide a power semiconductor device which can offer an increased active area and/or current rating. It may be considered to be an additional or alternative aim of the invention to provide a power semiconductor device which can mitigate one or more of the above problems.

According to the present invention, there is provided a power semiconductor device comprising an array of semiconductor cells provided on a substrate, said array comprising a plurality of sub-arrays, each sub-array comprising a gate connector and a plurality of cells connected in parallel thereto, wherein the cells in one sub-array are electrically isolated from the cells in one or more further sub-array.

The present invention may allow each sub-array to be independently and/or selectively controllable.

The plurality of gate connectors may be connected in parallel. Each gate connector may be centrally arranged with respect to its sub-array. Each gate connector may be provided on the substrate. The gate connector may comprise a gate pad.

The provision of a plurality of sub-arrays, each having its own dedicated gate pad allows reduced RC delay times. Furthermore the electrical isolation of the cells of each sub-array allows for improved and more-complex control strategies than have been hitherto possible.

The array of cells may represent the total activatable area of the device and may be sub-divided into four or more sub-arrays.

Each cell may comprise a gate. Each sub-array may comprise a gate runner structure connecting each cell to the gate connector. The gate runner structure of one sub-array may be isolated from the gate runner of the one or more further sub-arrays. Each gate connector may have a dedicated gate runner structure and cell sub-array. A space or insulator material may be provided between the gate runner structures of each sub-array.

Each gate connector may comprise an independent gate drive connection.

In one embodiment, each cell comprises a cathode material, wherein the cathode material of one sub-array may be isolated or separated from the cathode material of one or more further sub-arrays. Each cell of a sub-array may have a common cathode. A space or insulator material may be provided between the cathodes of each sub-array.

The array may comprise a two-dimensional array of vertical semiconductor cells.

The array may define an activatable area of the device. The sub-arrays may comprise individually activatable zones or regions of the activatable area.

Thus the arrangement of isolated sub arrays can alleviate in-homogenous current distribution problems whilst allowing for the provision of large active areas.

Any reference herein to a Metal-Oxide-Semiconductor Field-Effect-Transistor may be considered to comprise common material variants thereof and may be considered to constitute a reference to an Insulated-Gate Field-Effect Transistor (IGFET) or Insulated-Gate Bi-polar Transistor (IGBT) as necessary.

Practicable embodiments of the invention are described in further detail below by way of example only with reference to the accompanying drawings, of which: Figure 1 shows a section through a conventional IGBT power device unit cell structure; Figure 2 shows a plan view of a conventional power semiconductor device; Figure 3 shows a circuit representation of a plurality of power MOS device cells; Figure 4 shows a plan view of a power semiconductor device according to one example of the present invention; Figure 5 shows a plan view of a power semiconductor device according to a second example of the present invention; Figure 6 shows a plan view of a power semiconductor device according to a third example of the present invention; Figure 7 shows a first example of a schematic connection arrangement for a device according to the invention; Figure 8 shows a second example of a schematic connection arrangement for a device according to the invention; Figure 9 shows a modified arrangement of Figure 8, in which a diode chip is provided; Figure 10 shows a schematic electrical diagram for individual control of sub-arrays of a device according to the invention; Figure 11 shows a schematic plan view of a driving arangement for one embodiment of the invention; Figure 12 shows a schemlic diagram of an active gate multiplexing arrangement for use in accordance with a further embodiment of the invention; and Figure 13 shows an example of a control system for a distrubuted gate arrangement according to the invention Figure 14 shows an example of a gate drive circuit; Figure 15 shows a schematic plan view of a driving arangement showing a first examplary operational state; Figure 16 shows the arrangement of Figure 15 in a further operational state; and Figure 17 shows a plan view of a conductor array which may be use with an example of the invention.

The present invention may be considered to comprise a distributed or multiplexed gate drive scheme for a MOS controlled power semiconductor device.

With reference to the problems described in the introduction with reference to the example of Fig. 2, the effective impedance of a gate connection for MOS power device cells is dominated by: a) The inductance of the wire bond from the device package terminal 18 to the gate pad 16; b) The capacitance of the gate itself; c) The resistance and capacitance of the gate runner 10.

The inductance of the wire bond and the capacitance of the gate itself remain constant for the device. However, the gate runners 10 shown in Fig. 2 form an electrical resistor-capacitor (RC) network across the device. In Fig. 3 an equivalent circuit diagram of four parallel connected IGBT cells shows that each cell gate is connected to the RC network. In Fig. 3, C' and R' represent the respective resistance and capacitance of the poly silicon gate runners across the relevant portion of the active area of the device. The effective impedance between the gate pad 16 and each cell (celli, cell2, cell3, cell4, etc.) increases as a function of the distance between them. Thus the associated problems with device performance are exacerbated as devices active area is scaled up and as current density increases.

This gives rise to a variation in gate impedance across the device, which can be described by an RC time-constant. The interconnection delay time may increase exponentially with distance along the gate runners dependent on the resistance thereof. The delay time could increase proportionally, for example if the sheet resistance (measure in Ohms per unit length) is increased depending on the manufacture conditions.

This invention provides a new design layout, for example, as indicated by the device 19 of Figure 4, which shows a plan view of a MOS controlled device with four cell groups and a centered gate pad for driving each group.

The layout is achieved by dividing the active area of the device on the substrate 12 into a number of cell groups or sub-arrays 20a-d as shown (rather than a single active area and a single gate pad 16 on the die as shown in Fig. 2). The sub-arrays 20a-d may be provided on a single/common substrate of a conventional type and may be bounded by a common edge termination structure 14, e.g. around the perimeter of the active area.

Each sub-array 20a-d is electrically isolated such that one sub-array can potentially be activated in isolation of one or more further sub-arrays. The sub-arrays may be physically spaced apart. Each sub array 20a-20d has a dedicated gate connector 22a-d, e.g. a gate pad, which forms a part of the connection from outside of the active area to the individual cell gates. Each sub-array has a gate runner structure or network 24 connecting the gate pad 22 to all the cells of the sub-array such that all the cells in the sub-array are connected in parallel. The gate runner structure is shown only for the upper-right sub-array for simplicity, although it will be appreciated that each sub array will typically have a corresponding gate runner structure.

The electrical isolation of the sub-arrays 20a-d in the embodiments of Figs. 4 to 6 is achieved by separation of the gate runner structure 24 between sub-arrays. This may be achieved by providing a break (e.g. an intermediate insulating material) so as to separate the gate poly-silicon layer portion for one sub-array from the layer portion corresponding to another sub-array. That is to say the gate runner structure can be sub-divided by area to correspond to the area of the individual sub-arrays. However it is also possible to provide similar electrical isolation between sub-arrays by a combination of separating the gate and cathode materials.

The number of sub-arrays may be modified according to the power rating of the chip and function requirements of the system. For example, as shown in Fig. 5, another embodiment of the invention could include six sub-arrays 20, each having their own gate pad. A common or individual gate runner system may be provided.

The sub-arrays may thus themselves be arranged in a two-dimensional array having rows and columns. In this manner anywhere between two and, for example, ten or more sub-arrays could be accommodated.

A further example is shown in Fig. 6 which shows that different shapeslgeometries of sub-arrays can also be accommodated. In Fig. 6 there is shown a plan view of a device arrangement in which sub-arrays are of unequal cell number/area. In this example the sub-arrays are concentrically arranged such that a central sub-array 20e is located within the perimeter of (i.e. surrounded by) one or more further sub-arrays 20f and/or 20g. Fig. 6 may be considered to provide a design of MOS controlled device having a plurality of circular sub-arrays. However alternative layouts may be possible.

It is also possible that sub-arrays may have more than one gate pad 22 for connection to the individual cells thereof. The number of gate pads 22 may also differ from sub-array to sub-array, for example depending on the area thereof.

However in the event that a sub-array has a plurality of (e.g. three) gate pads, it is notable that the gate runner and cell arrangement in a single sub-array is such that the plurality of gate pads commonly drive the cells of the array in parallel, rather than defining a further level of sub-array within the sub-array itself.

Each sub-array and associated gate pad(s) in any of the embodiments described above may be considered to provide a distributed gate. The result is multiple gate pads driving a plurality of individual cell groups. Each distributed gate would typically, but not exclusively, be connected to the gate pads/contacts located outside of the chip area by a conducting channel or a wire bond.

In one example of the invention, the individual sub-arrays (i.e. cell groups) making up the active area of the device can be driven together, in parallel, e.g. to benefit from reduced RC delay times (i.e. so as to achieve reduced gate RC time-constants for active device area). Increasing the number of distributed gates in such an arrangement can reduce the maximum gate pad to cell distance and thereby reduce the RC time-constant variation across the active area. Thus the sub-arrays may then be electrically connected in parallel to achieve a single device with a single gate drive, e.g. to reduce the in-homogeneity of current distribution in cells across the device. In such a scheme, the cathode cells from all parts are controlled to conducting and un-conducting states by the gate voltage as with traditional MOS controlled design, but with improved switching characteristics.

The current redistribution among cells can be improved due to their reduced gate delay time.

An example of a MOS controlled device which can be driven in parallel as described above is shown in Fig. 7. The multi-sub-array device is provided in the form of a chip 26 (e.g. a IGBT chip) mounted on a substrate or board such as Direct Bonded Copper (DBC) or Direct Aluminium Bonded (DAB) board 28.

Discrete wiring patterns for each of the anode, cathode and gates are provided on the board so as to provide suitable connections for the sub-arrays 20. Bonding wires 30 connect the anode, cathode and gate pads of the sub-arrays to the corresponding wiring/connection arrangement 32, 34, 36 on the board.

In the arrangement of Fig. 7, it can be seen that a single connection (e.g. wire bond 30a) connects a plurality of gate pads 22 of different sub-arrays 20 to the correponding connection arrangement 36. Also the gate connection 36 is a common connection for all of the gates bonded there-to, such that all sub-arrays can be driven by a common driving signal. Similarly a common cathode connection 34 is provided. Accordingly all sub arrays 20 are driven in a pallel manner via a common control signal.

However the invention also allows variations and improvements in the control of the device as will be described below. In particular, the invention may allow for the individual control of different the sub-arrays to be individually controlled. Thus in addition to, or as an alternative to, the control of the sub-arrays to operate in parallel (i.e. akin to a uniformly controlled device) individual sub-arrays may be switched on or off as required. The period of high voltage and low voltage applied to each gate pad may be actively controlled and may differ from one sub-array to another. The device can then be fully or partly switched on/off with the desired output current level. This can increase efficiency and provide advanced device level control.

Turning to Fig. 8, there is shown an example of a device which allows individual control of the sub-arrays. The device of Figure 8 is substantially as described above in relation to Fig.7 with the exception that the gate wiring arrangement in Fig. 8 comprises a plurality of individual (i.e. electrically isolated) connection arrangements 40. Each connection arrangement 40 on the board is separately connected to the gate pad 22 of a sub-array, for example by a wire bond 30. Thus there may exist an individual connector 40 for each sub-array 20 or gate-runner system thereof. An individual connector 40 may be provided for each sub-array or else for a plurality of sub-arrays dependent on the level of control required.

In Figure 9, there is shown a further example which is similar to the arrangement of Fig. 8 with the exception that a diode 42 (i.e. diode chip) is provided on the board and connected to the device 26 via the collector wiring arrangement 44, for example to provide a reverse blocking arrangement as would be understood by the skilled person. The wiring arrangement 44 may provide a common connector for all sub-arrays of the device.

In any of the embodiments of Figs. 7-9, the gate wiring pattern may be arranged such that the gate pads are relatively close to each other to minimize the wire bond length.

Furthermore it will be appreciated that the arrangements of Figs. 7-9 are relevant to an embodiment in which the individual sub-arrays are isolated from each other by way of separate gate runner arrangements being provided for each sub-array.

In the event that the sub-arrays are provided by provision of suitable discontinuities in the cathode material, then it will be appreciated that discrete cathode wiring/connector arrangements may additionally or alternatively be provided in order to allow independent control of the sub-arrays.

Any embodiment of the invention may be controlled/driven typically by a logic unit or any programmable device so as to be able to control the current in each sub- array of the device. For this purpose, with reference to the examples of Figs. 10- 13, a suitable digital signal processor or integrated circuit controller 46 may be provided.

One proposed arrangement of achieving independently controlled sub-arrays (i.e. distributed gate control) is shown in Fig. 10. Which shows a schematic electrical diagram of an individual gate driver scheme. In this example each gate pad connection 40, labelled GP, is driven by an independent gate drive circuit, and the total number of drives is equal to the total number of independently driven gates or cell groups.

In other embodiments a plurality of sub-arrays may be controlled in combination (or in varying combinations) for example so as to provide a multiplexing gate or sub-array control system.

In Fig. 11 an example of an active gate multiplexing system is provided. The plurality of sub-arrays are arranged, e.g. in a regular two-dimensional array, such that one or more row (Ri, R2, R3) and one or more column (Cl, C2, C3) of sub-arrays (or asociated gate pads) can be defined. Those are labelled in Fig. 11 as Gxy where the identifiers X and Y denote a row and column identifier respectively.

Acordingly individual sub-arrays can be identified by their unique row and column combination or else entire rows or columns as necessary.

In the example of Fig. 11 a driving arrangement is provided which can apply a different driving signal to each row and colum of sub-arrays of the device. Each sub array may be connected to the driver using a suitable switching/transistor arrangement 48 such that combined inputs from the row and column driver may activate the relevant sub-array. Thus individual or combinations of sub-arrays in the distributed gate device can be activated by selecting different row and column combinations. In particular individual rows or columns can be switched according to a desired control scheme.

In Fig. 12 a further schemtic example of an active gate multiplexing system for a distributed gate device is shown, in which a power suply unit 49 is connected to the device via column and row drivers 51 and 53. In this example, an active matrix drive scheme such as those used in the display applications to drive the gates individually or collectively. Such active gate multiplexing may use Active-Matrix Liquid Crystal Display (AMLCD) technology such as CMOS Thin Film Transistors (TFTs) to control cell groups independently.

An overall representation of a suggested gate driving system for a distributed gate device according to the invention is shown in Fig. 13. A programmable controller 50, such as for example a field programmable gate array (FPGA) board, can be used to control the status of distributed gates of MOS power device according to any embodiment of the invention. The FPGA circuit board may be connected to a buffer 52 and level shifting circuit 54, which may be used to recondition signals and shift the logic to a suitable level (e.g. 5V logic) when necessary.

The suitable signals are fed to the gate drivers 56. The gate driving stages contain multiple drive circuits, which take the PWM logic inputs and output switching voltage to the gates between positive voltages, +V and negative voltage -V00.

The output current of the power semiconductor device can be actively controlled by PWM gate signals applied to the gate pads of the device. The duty cycle of PWM signals are adjusted according to the load requirement. When distributed gates are appropriately controlled during operation, the invention enables any or any combination of: increased device efficiency; reduced power loss; larger chip/device sizes; operation at high power densities; operation at higher temperatures; and/or, increased reliability through redundancy. If used across multiple devices, advanced inter-chip level control of power semiconductor devices may provide further benefits compared to the state of the art.

In Figure 14, an example of an equivalent circuit diagram for a matrix gate drive circuit according to an example of the invention is shown. A FET transistor 60 is placed between the column voltage, V, and gate 58 of IGBT. The column voltage, V0, can be applied to the IGBT gate 58 once the row voltage, VR, is turned on in the gate of the MOSFET. Both Vc and VR can be used in combination to control the gate voltage of IGBT. VR is used to control the status of control FET 60. Vc is the voltage applied to IGBT gate. When the control FET is at on-state, Vc is applied the IGBT gate 58 through the transistor. When the control FET is at off-state, the IGBT is turned-off regardless the voltage level of Vc.

For example, in Figure 15, the control FET 60 is at on-state with +15V row driver voltage applied their gates. But gate voltage of sub-area Gil, G21, and G31 is turned-off by the -5V column driver voltage, Vci. In this case, 2/3 of the total active area is conducting with +15V column voltage applied at V2 and V3.

In Figure 16, the control FET 60 is turned-off by OV row driver voltage, VR1 and VR3. The sub-areas G11-G13 and G31-G33 of IGBT are at off-state. In this case, only 1/3 of the total active area (G21, G22, and G23) is conducting.

In such an example of active gate multiplexing system (AGM), each sub-area can only be activated/conducting when both of its corresponding row and column drivers are controlled at a desired voltage level. Such a system/method of operation may provide a further definition of the invention.

Such an AGM system may be advantageous in that output current level can be achieved by selectively controlling status of the sub-areas by row and column drivers. A reduced number of drivers are required relative to increasing numbers of gate pads for distributed gate device.

The above-described techniques may pave way for active gate multiplexing for multi-level converters in a single power device, which contrasts to conventional thinking in which power devices are considered as discrete devices. These devices encompass active regions and edge termination regions. For a given current rating depending upon the voltage ratings, the ratio between active region/edge termination region can vary, with increasing area being taken up for edge termination with increasing voltage rating. In accordance with the present invention, a distributed, isolated gate driver arrangement can provide an intelligent solution for multi-level converter topologies using a single device.

In further developments of the invention, the lost active area of the semiconductor device due to the presence of a plurality of gate pads can be addressed in a number of ways if necessary to improve potential power density. For example, using finer wire bonds may provide for further active area. Additionally or alternatively, it is possible to replace the relatively-large gate pad area of each sub-array with multiple smaller gate pads to which contacts can be made using a contact array (often referred to as a pin grid array), for example, a Ball Gate Array (BOA) or by Stud-Bumping. Such approaches can also increase the number of cathode cells thus achieving higher power density. An example of the 3x3 distributed gate device is shown in Fig.17, although it will be appreciated that any required number of contacts can be formed in a two-dimensional array as required. Each sub-area has a protruding contact 62 (e.g. a solder bump) for gate connection and surrounded by cathode contacts 64 (e.g. solder bumps). This method can greatly reduce the gate pad area used by wire bonding and achieve higher density of sub-arrays.

It is possible to integrate sensing functions into each of the individual portions (i.e. the sub-arrays) of the device in order to achieve comparison between the different locations of the single power device. It is possible to conceive integration of these elements monolithically on top of the power device to reduce the parasitic gate inductances and speed up the sensing functions.

In such an example of integrated distributed gate monitoring, any or any combination of current, voltage and/or temperature sensors may be incorporated within the power device architecture. Any of those sensors may be embedded within or integrated on the surface of the power device. It is also been possible to integrate CMOS logic within the power device. Some technologies, such as the Clustered IGBT are well suited for such an approach due to its unique cathode cell protection by self-clamping.

Increasingly, wide band gap (WBG) devices using Silicon Carbide (SiC) or Gallium Nitride (GaN), for example, SiC Metal-Oxide Semiconductor Field Effect Transistor (MOSFET), SiC IGBT, SiC Bi-polar Junction Transistor (BJT), GaN Heterostructure Field Effect Transistor (HFET), GaN MOSFET,etc are being used to make power devices instead of Silicon. In these materials, carrier lifetime varies considerably axially and vertically through the devices. In light of the trend to reduce cell dimensions (e.g. via fine-line lithography) and increase the operational current density, WBG devices may provide a suitable application for the present invention in order to reduce have in-homogenous current distribution over a large active area device, particularly since carrier lifetime can vary considerably axially and vertically through these devices.

Independent gate control also allows the control signal to be tailored to maintain homogenous current distribution during DC and switching transients.

In summary, the invention provides a new arrangement and associated control system for MOS gated power devices. It may allow a multiplexed gate drive scheme to be implemented for MOS controlled power semiconductor devices.

Such techniques are applicable to all MOS power devices, including Junction Field Effect Transistors (JFET). The invention can be applied to current controlled power devices too, such as BJT, IGCT, GTO, etc by using similar techniques.

Conventional current triggered devices may also suffer delay/loss during the switching transients due to their large active area.

Claims (18)

1. Claims: 1. A power semiconductor device comprising an array of semiconductor cells provided on a substrate, said array comprising a plurality of sub-arrays, each sub-array comprising a gate connector and a plurality of cells connected in parallel thereto, wherein the cells in one sub-array are electrically isolated from the cells in one or more further sub-array.
2. 2. A device according to claim 1, wherein each sub array comprises a gate runner structure connecting each cell to the gate connector.
3. 3. A device according to claim 2, wherein the gate runner structure of one sub-array is isolated from the gate runner of the one or more further sub-array.
4. 4. A device according to any preceding claim wherein each cell comprises a cathode, the cathode material of one sub-array being electrically isolated from the cathode material of the one or more further sub-array.
5. 5. A device according to any preceding claim wherein each sub-array is selectively controllable between an on-state and an off-state independently of the one or more further sub-array.
6. 6. A device according to any preceding claim, wherein the gate connector of each sub-array is provided on the substrate.
7. 7. A device according any preceding claim wherein a plurality of sub-arrays are connected to a common gate driver via the gate connectors.
8. 8. A device according to claim 8, wherein the gate connectors are connected in parallel to said common gate driver.
9. 9. A device according to claim 8 or 9, wherein a plurality of gate drivers are provided, each gate driver being independently controllable to provide a signal to the corresponding gate connectors in use.
10. 10. A device according to any preceding claim, wherein the gate connector of each sub-array is connected to a gate driver via a control transistor.
11. 11. A device according to any preceding claim, wherein the sub-arrays and/or gate connectors are arranged in a two-dimensional array or matrix.
12. 12. A device according to claim 11, wherein the matrix of sub-arrays comprises a plurality of rows and columns, each row and column being connected to a respective row and column driver.
13. 13. A device according to claim 12, wherein each sub-array is activated from an off-state to an on-state only when an activation signal is provided by both of its respective row and column drivers.
14. 14. A device according to any preceding claim further comprising a connector array having a plurality of conductors, each conductor arranged to provide a connection with a single gate connector.
15. 15. A device according to any preceding claim, comprising a controller arranged to control the supply of signals to each gate connector so as to selectively switch each sub-array between an on-state and an off-state and vice versa.
16. 16. A device according to any preceding claim, comprising four or more sub-arrays.
17. 17. A device according to any preceding claim, wherein the array of cells comprises a two-dimensional array of vertical semiconductor cells
18. 18. A device or control system substantially as hereinbefore described with reference to the accompanying drawings 4 to 17.