GB2443105A - Sector programming method in a flash memory device - Google Patents
Sector programming method in a flash memory device Download PDFInfo
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- GB2443105A GB2443105A GB0724391A GB0724391A GB2443105A GB 2443105 A GB2443105 A GB 2443105A GB 0724391 A GB0724391 A GB 0724391A GB 0724391 A GB0724391 A GB 0724391A GB 2443105 A GB2443105 A GB 2443105A
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Classifications
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/08—Address circuits; Decoders; Word-line control circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/10—Programming or data input circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/10—Programming or data input circuits
- G11C16/12—Programming voltage switching circuits
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Abstract
A semiconductor device comprises sectors having memory cells connected to local word lines, decoders 240 selecting the sectors and a circuit generating, in programming of a selected sector, control signals that cause the local word lines of unselected sectors to be in a floating state. Each sector could also comprise pull-up 242 and pull-down 243 transistors which are turned off in the unselected sectors during programming. The decoders 240 could select sectors via global word lines and a circuit could be used to couple a dummy line with the global word lines when discharging the local word lines after erasing using a negative voltage applied to the local word lines. A bias circuit could be used to bias a given voltage to the dummy line during reading and programming.
Description
TITI OF THE INVENTION
SEMICONDUCTOR DEVTCE AND ITS CONTROL METHOD
MCQROuND OF THE JNVEN'I'lON
1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly, to a semiconductor device having global word lines connecting a plurality of sectors and local word lines provided in the sectors and a method of controlling the same.
2. Description of the Related Art
Recently, applications of the non-volatile semiconductor memories such as flash memories have drastically expanded. It is known that the flash memory has a cell array of a NOR type, NAND type or AND type. One of the features of the flash memory is to perform erasing on the sector basis. There have been manyproposals of the arrangement of sectors. For instance, it is known that the sectors are arrayed iii a matrix formation in which the sectors are laterally connected by global word lines, and are vertically connected by vertical word lines. Each of the sectors has a respective local word line with which a connection is selectively made by the global word line and the vertical word line.
The above-mentioned structure has a problem about the reduction of current consumed. The above-mentioned array requires complicated switching, and is likely to waste current such as leakage current, As the capacity of the flash memory increases, the problem becomes more conspicuous.
SUMMARY OF THE INVENTION
The present invention has an objective of reducing current consumed in semiconductor devices such as a non-volatile semiconductor memory.
The present invention is a semiconductor device comprising; sectors having memory cells connected to local word lines; decoders selecting the sectors; and a circuit generating, in erasing of a selected sector, a control signal that causes a corresponding one of the decoders associated with the selected sector to be temporarily unselected.
The above semiconductor device may be configured so that: each of the sectors comprises a pull-np transistor that is driven by a corresponding one of the decoders via a corresponding one of global word lines connecting the sectors and drives one of the local word lines; and the pull-up transistor is kept OFF by the control signal.
The semiconductor device may be configured so that the circuit generates the control signal that keeps the corresponding one of the decoders unselected in an initial stage of erasing.
The semiconductor device may be configured so that the circuit generates the control signal that keeps the corresponding one of the decoders unselected until a negative pump path connected to the colTesponding one of the decoders unselected lalls to a given intermediate negative voltage in erasing.
The semiconductor device may be con ligured so that: each of the sectors comprises a pull-up transistor and a pull-down transistor fbi driving one of the local word lines, both transistors being driven by a corresponding one of the decoders; and the. control signal disabling a path including the pull-up and pull-down transistors for a given period of time in erasing.
The present invention includes a semiconductor device comprising: sectors having memory cells connected to local word lines; decoders selecting the sectors; and a circuit generating, in programming of a selected sector, control signals that cause the local word lines of unselected sectors to be in a floating state.
The semiconductor device may he configured so that: each of the sectors comprises a pull-up transistor and a pull-down transistor for driving one of the local word lines, both transistors being driven by a corresponding one of the decoders; and the control signals turning OFF the pull-Lip and pull-down transistors in the unselected sectors in programming, The semiconductor device may be configured so that one of the decoders associated with the selected sector to bc programmed sets unselected local word lines in the selected sector at a given potential via a global word line that connects said one of the decoders arid the selected sector.
The present invention includes a semiconductor device comprising: sectors having memory cells connected to local word lines; decoders selecting the sectors via global word lines; a dummy line; and a circuit coupling the (Tummy line with the global word lines at the time of discharging the local word lines after erasing using a negative voltage applied to the local word lines.
The semiconductor device may be configured so as to further comprise a bias circuit biasing a given voltage to the dummy line in reading and programming.
The semiconductor device may be configured so as to further comprise another circuit generating, in erasing of a selected sector, a control signal that causes a corresponding one of the decoders associated with the selected sector to be temporarily unselected.
The semic:onductor device may be configured so as to further comprise yet another circuit generating, in programming of a selected sector, control signals that cause the local word lines of unselccted sectors to be in a floating state.
Thc semiconductor device may be configured so that the memory cells are now vol ati Ic memory cells.
Thc present invention includes a method of controlling a semiconductor (leVice comprising the steps of: selecting one of sectors hving memory cclls connected to local word lines; and generating, in erasing of a selected sector, a control signal that causes a decoder for selectively driving the selected sector to he temporarily unscleci ccl.
The present invention includes a method of controlling a semiconductor devic:e comprising the steps of: selecting one of sectors having memory cells cormected to local word lines; and generating, in programming of a selected sector, control signals that that cause the local word lines of unselected sectors to be in a floating state.
The present invention includes a method of controlling a semiconductor device comprising the steps of: selecting one of sectors having memory cells connected to local word lines; and coupling a dummy line with a global word line at the tinie of discharging the local word lines after erasing using a negative voltage applied to the local word lines.
BRIEF DESCRIPTION OF THE DRAWINGS
Preferred embodiments of the present invention will be described in detail based on the following figures, wherein: Fig.1 is a diagram of the entire structure of a semiconductor device according to a first embodiment of the present invention; Fig. 2A shows the levels of signals applied to a global word line decoder of the semiconductor device shown in Fig. I; Fig. 2B shows the levels of signals applied to a vertical word line decoder of the semiconductor device shown in Fig. I; Fig. 2C shows the levels of signals applied to a sector switch control circuit of the semiconductor device shown in Fig. I; Fig. 2D shows the levels of signals applied to a local word line decoder of the semiconductor device shown in Fig. 1 Fig. 3 is a circuit diagram of the local word line decoder (xdec_suh) provided iii the semiconductor device shown in Fig. I Fig. 4 is a circuit diagram of a high-voltage output circuit (gvpx) provided in the semiconductor device shown in Fig. I; Figs. 5A and 513 are timing charts of the operation of the high-voltage output circuit shown in Fig. 4; Fig. 6 is a circuit diagram of a global word line (row direction) decoder (xdee) provided in the semiconductor device shown in Fig. 1; Fig. 7 is a circuit diagram of an XT generating circuit used in the semiconductor device shown in Fig. 1; Fig. 8 is a circuit diagram of a Predetermined polential detection circuit (ncgpl) used in the semiconductor device shown in Fig. I; Figs. 9A and 911 are timing charts of the opcral.ions of the global word line decoder shown in Fig. 6 and the XI' generating circuit shown in Fig. 7; Fig. 10 is a circuit diagram of a global sector switch circuit (sswitchg) in the row direction provided in the semiconductor device shown in Fig. 1; Figs. ii A and 11 B are timing charts of the operations of the predetermined voltage detection circuit shown in Fig. 8 and the global sector switch circuit; Fig. 12 is a circuit diagram of a global sector switch circuit (sswitchv) in the column direction provided in the semiconductor device shown iii Fig. 1; Fig. 13 is a circuit diagram of a vertical word line decoder (vdec) in the semiconductor device shown in Fig. 1; Figs. .t4A and 1411 are timing charts of the operations of the global sector switch circuit shown in Fig. 12 and the vertical word line decoder shown in Fig. 13; Fig. 15 shows a configuration and operation of a sector switch (sswitch) provided in the semiconductor device shown in Fig. 1; Fig. 16 is a graph explaining discharging a local word line discharging a global word line alter erasing; Fig. 17 is a block diagram of the entire structure of a semiconductor device according to a second embodinient; Fig. 18 is a circuit diagram of a global sector switch circuit in the horizontal direction used in the second embodiment; Fig. 19 is a graph explaining discharging the local word line and discharging the global word line after erasing in the second embodiment; and 1.:ig. 20 is a b]ock diagram of an entire structure of the semiconductor device according to the present invention.
SCRIPTION OF THE PREFERRF.D EMBODIMENTS A description will now be given, with rekrence to the accompanying drawings, of embodiments of the present invention.
First Embodiment Fig. I is a block diagram of a structure of a flash memory which is an example of a non-volatile scmiconductor memory according to a first embodiment of the present. invention, The flash memory has a plurality of sectors 200, -arranged in rows and columns (Ii and v are respectively arbitrary natura] numbers).
Bach of the sectors 200,1 -200hv has 11011-volatile memory cells. Each of the rows has thc same structure, and each of the columns has the samc structure. Thus, the following description is mainly directed to only the hth row and the vth column, and a description of the other rows and columns may be omitted occasionally.
A pair ol global word lines (JWLNh and CWLBh connects the sectors 2001)1 - 20O,, in the lith row in the lateral direction (row direction). A programlread voltage supply line VPXh and a sector switch control line (JXDSh are provided laterally and are eonneetcd to the sectors 200,, -200,,. Main decoders (row decoders) 1001 -1 h are provided in the rows. The main decoder t.10b controls the pair of global word lines CWLNII antI (JWLB1I, the program/read voltage supply line VPXh, and the sector switch control line GXDSh. The main decoder 100,1 has a high-voltage output circuit (gvpx) 110, a global word line decoder (xdee) 140, and a global sector switch circuit (sswitchg) 180. The high-voltage output circuit 110 supplies the sectors 200h[ -200 with a programlread voltage VPXh. The global word line decoder 140 selectively drives the global word line GWLNh and GWLBh. The global sector switch circuit 180 controls the sector switch control line GXDSh in the row direction.
The main decoders 1001 -1001) are supplied with a high voltage VPXG and a negative voltage NEOP from a voltage generating circuit 400. The voltage generating circuit 400 has a high-voltage generating circuit 410 that generates the high voltage VPXQ and a negative voltage generating circuit 420 that generates the negative voltage NEOP. The negative voltage NEOP is used to erase the sectors, as will be described later.
Column decoders 300, 300 are provided in the columns. Sector switch select signal lines AENv and NENv and a vertical word line VWLv that extend from the column decoder 3O0 are connected to the sectors Iv -00hv located in the vth column, The column decoder 300v has a global sector switch circuit (sswitchv) 3 1 0 in the column direction, and a vertical word line decoder (vxdec) 340. l'he global sector switch circuit 310 sclects the sector switch select signal lines AENv and NENv.
Tile vertical word line decoder 340 selectively drives the vertical word line VWLv.
The voltage generating circuit 400 supplies the column decoders 300, -300w with the high voltage VPXG and the negative voltage NEGP.
The sector 2O0,, has a sector switch circuit (sswitch) 210 and local word line decoders (xdec_sub) 240 each of which is associated with a respective one of the local word lines provided therein, The sector switch circuit 210 is controlled by the -.5-sector switch select signal lines AENv and NENv, and supplies a signal line XDSn with the negative voltage NBGP or ground voltage Yss. The local word line decoders 240 are selectively connected to the vertical word line VWLv. The selected local word line decoder 240 supplies the associated local \vord line with the high voltage VPXh or ground voltage Yss supplied via the vertical word line VWLv.
Memory cells ai-e connected to the local word line.
An outline of the operation ci [lie flash memory will now be described. One sector and one local word line provided therein arc selected by the signals VPXh, (]WLNh, GWL}ih arid (JXDSh in the row direction and the signals \1Wl.v, AENv and NENv in the column direction. The negative voltage NEGP output by the global sector switch circuit 180 in the main decoder h is supplied to the selected local word line in the selected sector via the line (iXDSh. The line GXDSh is conunon to tile sectors 200 -200h ni the row direction, and are sequentially connected thereto starting from the sector 2001i1 closest to the nmm decoder 0h Figs. 2A through 2D show an outline of tile operation of the flash memory shown in Fig. 1. Fig. 2A is a view of an operation of the global word line decoder (xdec) 140, Fig. 2B is a view of an operation of [he vertical word line decoder (vxdce) 340, Fig. 2C is a view of an operation of the sector switch circuit (sswiteh) 210, and Fig. 2T) is a view of an operation of the local word line decoder (xdec_sub) 240.
Figs. 2A through 21) show operations in erase verification, erasing arid programming.
The operations in reading are the same as those in programming.
For convenience of explanation, the local word line decoder (xdee_sub) 240 will be described first. As will he described below, there is a possibility that a leakage current may flow through the local word line decoder 240 in the shift from the erase verification to the erasing and in the programming unless the following circuit configuration is employed. In the following, the configuration of the local word line decoder 240 will be described with reference to Fig. 3 first, the leakage current that may flow in the shift from the erase verification to the erasing and in the programming will be described second, and an outline of the configuration designed to prevent the occurrence of the leakage current will be described third.
Fig. 3 is a circuit diagram of a configuration of the local word line decoder (xdee_sub) 240. The local word line decoder 240 is macic up of N-channel transistors 241, 242 and 243, l'he transistor 242 is a pull-up transistor, and the transistor 243 is a pull-down transistor. The vertical word line VWLv is selectively connected to the local word line P2WLn via the transistor 242, and the sector switch control line XDSn from the sector switch circuit 210 is selectively connected 1.0 the local word line P2WLn via [lie transistor 243. The transistors 241, 242 and 243 are formed in P-type wells, and are back-biased by the sector switch control line GXDSh extending from the global sector switch circuit 180 of the main decoder bOb. The P-type wells that respectively include tile transistors 241, 242 and 243 are provided in an Ntype well for isolation from a Ptype substrate. The N-type well is biased by a power supply voltage Vcc. The gate of the transistor 242 is controlled by the global word line GWLNh via the transistor 241. The gate of the transistor 241 is connected to the high-voltage supply line VPXh that extends frorri the high voltage output circuit of the main decoder 100h. The gate of the transistor 243 is controlled by the global word line (JWLBh, A small circle given to the symbol of each transistor denotes that these transistors have threshold voltages lower than these of transistors described l)y symbols having no circle.
The voltages shown in Fig. 2D are applied Lu tile selected word line and unselected word lines at the time of erase verification. The detail is as follows. At the time of erase verification, GWLNh/GWL}31-p-A'PXh/Vss, VWJ1v=VPX\' and the local word line P2WLn is supplied with the high voltage in connection with the selected word line. In connection with the unselected word lines, tile local word line P2WLn is Vss under the condition that GWLN1iJOWJJ-3h=\'PXhjVss (selected) and vwi vVs s (unselected), or GWT NhIG WLB h= V ss/Vcc (unselected) and VWLv=VPXV (selected). At the time of erasing, in connection with the selected sector, GWLNh/OWLBh=NBGP/Vec, YWI N=Vss, XDSn=GXDSh=NJjGP, and the beak word line P2WLn is supplied with the negative voltage. In connection with the unselected sectors, the local word line P2WLn is Vss under the condition that GWLNhJGWLBhNEGP/Vss (selected) and XDSn=Vss (unselected), or GWLNhIGWLBh=Vss/Vcc (unselected) and XDSn=Vss (unselected). Ill this case, the former condition, tile local word line P2SI fl is in the floating state, the word line P2WLn has a negative voltage due to coupling resulting from OWLNhg=NEGP.
however, there is no substantial adverse influence.
In the sector selected through the global word line OWLNh and (IWLBh when the operation sllifts Irorn the erase verification to the erase operation, it is desired to shill the local word line P2WLn from the high voltage to the negative voltage quickly. in order to achieve tile quick shifting, it is required to turn OFF tile transistor 242 from ON quickly and turn ON the transistor 243 from OFF quickly.
Just prior to the shift to tile erase operation, the global word line (JWLNh is at the high voltage VPXh, which turns ON the transistor 242. Thus, the voltage sufficient to set the global word line P2WLn to the higil voltage by turning ON the transistor 242 is retained at a node F. In this state, when the operation shifts from the erase verification to tile erase operation, the global word line (JWLNh connected to the selected sector changes from the high voltage VPXh to the negative voltage NEOP.
At this time, in tI-ic conventional art, the global word line GWLNh is maintained at a voltage higher than Vss. Thus, the transistor 242 is maintained in the ON state, and a leakagc current path from the yertical word line VWLv is formed. Thus, the local word line P2WLn cannot he efficiently driven to (lie negative voltage NEGP via the transistor 243, In contrast, the present embodiment employs the unique structure that wil I he described latem This structure forcedly turns OFF the transistor 212 during a given period of time From the start of the erase operation, and thus drives the local word line P2WLn to the negative voltage NEUP quickly. The above-mentioned leakage current path occurs in the local word line decoders 210 in the selected sector.
Therefore, as the memory capacity increases, the efficiency of the supply of the negative voltage NFGP decreases, and there may be a case where the negative voltage NTGP cannot be supplied. The suppression of the leakage current path according to the present embodiment is especially advantageous to the above-mentioned situation.
There is also a possibility that the leakage current may flow through the local word line decoders 240 shown in Fig. 3 at the dine of programming. During the programming, on the selected vertical word line VWLv (=VPXV), there are provided the local word line decoder 240 in which the global word lines GWLNh/GWLBh are in the selected states (=VPXh/VPXY) and the other local word line decoders 240 in which the glocal word lines GWLNhJGWLBh are in the unselected states (=Vss/Vec).
in the local word line decoders 240 in which the global word lines GWLNh1OWLBh are in the unselected states, the transistors 242 are OFF because of GWLNh=Vss, and the transistor 243 is ON. Howevei; since the transistors 242 and 243 have small threshold values, there is a slight leakage current flowing in the transistor 242. As the memory capacity increases, an increased number of unselected local word line decoders 240 exists, and the adverse influence of the leakage current becomes more conspicuous. In order to solve this problem, the present embodiment employs a unique structure that turns OFF both the transistors 242 and 243 in each of the local word line decoders 240 in the unselected states at the time of programming so that n leakage current can Flow through the transistors 242 and 243 (as shown in Fig. 2D, the transistor 243 is turned OFF by setting the global word line (iWLl3h to Vss). Thus, the word line lines P2WLn in the unselected sectors are in the floating states, and the local word line P2WLn driven by the local word line decoder 240 on the selected vertical word line VWLv does not affect the programming although the level of the local word line P2WLn is -slightly raised due to coupling. It is to he noted that the bit line level is raised in the selected sector. In order to prevent erroneous programming clue to the coupling-based rise of the local word line P2WLn, it is required to connect the unse]ectcd local word lines to the ground potential Vss. This causes a leakage current to flow in the unselected local word line decoders 2'lO in the selected scctor.
However, thcre is no adverse influence unless a huge number of unselected local word line decoders is employed.
A description will he given of parts of the structure shown in Fig. 1.
Fig. 4 is a circuit diagram of the high-voltage output circuit (gvpx) 110 provided in the main decoder 1 OOh. The high-voltage output circuit 110 outputs the high voltage VPXII, and has AND gates ill, 112, a NOR gate 113, N-channel transistors I 14, 117 and LIX, P-channel transistors 115, 116 and 119, an inverter 120 and a floating instruction signal generating circuit 121. A symbol GSELh is a global W(}r(l line select instruction signal, a symbol ERSFT. is an erase decode period instruction signal, a symbol GSELBIi is an inverted signal of the global word line select instruction signal OSPIh, a syirihol SVPX is a VPX select instruction signal, a symbol \PXG is the high voltage (> Vcc) generated by a charge pump operation, a symbol FRSELBVT is an inverted signal of the erase period instruction signal F.RSEL, a symbol PGMB is a signal that indicates a period of time during which the high voltage is applied to the gate and drain of the memory cell during the period of programming, a symbol FLOATXBh is a signal indicating a floating period. The control signals GSI2Lh, ERSEL, GSFLh, SVPX, ERSELBYT and P0MB are supplied from a control circuit (control circuit 520 shown in Fig. 20) that will be described later.
Figs. 5A and SIB show an operation of the high-voltage output circuit 110.
Fig. 5A shows the operation at the tmie of programming, and Fig. SB shows the operation at the time of erasing. When the global word line in the hth row is selected at the time of programming, the high--voltage output circuit 11 0 in the main decoder lOOh generates the high voltage VPXh (> Vec) from the voltage VPXG that is raised by the charge lurnp operation, and outputs the high voltage VPXh. if the global word line in the hth row is unselected at the time of programming, the high-voltage output circuit 110 remains the output voltage VPXh at Yce. When the global word line in the hth row is selected at the time of erasing, the high-voltage output circuit 110 in the main decoder I OOh generates the output voltage \PXh equal to Vss.
When the above global word line is unselecied, the high-voltage output circuit 110 retains the output voltage VPXh at Vcc. The floating instruction signal generating circuit 1 21 outputs a low-level signal in synchronism with the control signal PGMB when the global word line in the 11th i-ow is unselected at the time of programming.
Fig. 6 is a circuit diagram of the global word line decoder (xdec) 140 provided in the main decoder 10Db. The global word line decoder 140 includes NAND gates 141, 147, N-channel transistors 142, 145, P-channel transistors 143 and (44, an OR gate 146 and an invcrter 148. The voltage VP)UI from the high-voltage output circuit 110 shown iii Fig. 4 is app] ied to the sources of the transistors 143 and 144, and the control signal FLOATXB]i is applied to the NAN]) gate 147. A signal GXRSTL is supplied from a control circuit that will be described later, and is used to reset the global word lines GWT.Nh and Ci WI.Bh or set these lines to Vss. A signal XTx is supplied from an XT generating circuit 150, which will be descrihed with reference to Fig. 7, and is used to sc]ect the global word ime decoder 140 of the main decoder bOy. The operation of the global word line decoder 140 will be described later with rcference to Figs. YA and PB.
Fig. 7 is a circuit diagram of the XT generating circuit ISO. Ihe XT generating circuit 150 outputs signals XT(0) -XT(h) to the main decoders 10I -1 OO, respectively. The XI' generating circuit 150 decodes an address signal to select one' main decoder. The X'I' generating circuit 1 50 includes x decode circuits each having an identical structure. It is now assumed that x xclec circuits are provided in the main decoder. For example, the decode circuit that outputs the signal XT(0) includes an AND gate 151, NOR gates 152 and 153, and inverters 154 and 155. The AND gate 151 is supplied with three bits Al IB, AI2B and AI3B among the bits consisting of the address signal. The output of the AND gate 151 is supplied to the NOR gate 152, which performs a NOR operation on the output of the ANT.) gate 151 and the signal ERSEL that is at the high level at the time of erasing. The output of the NOR gate 152 is supplied to the NOR gate 153, which performs a NOR operation on the output of the NOR gate 152 and a disable signal DISXT output by a disable signal generating circuit 156. The output of the NOR gate 153 passes through the inverters 154 and 155, and is output as XT(O). rrhc disable signal generating circuit 156 generates, by means of a NAND gate 1 57 and an inverter 158, the disable signal DJSXT from an erase instruction signal ER output by tile after-mentioned control circuit and a detection signal NEGPL generated by a predetermined potential detection circuit 1 60 that will be described later with reference to Fig. 8. The signals X'I'(O) ... generated by the Xi' gcnerati iig circuit 150 function as control signals that temporarily causes the decoder connected to the selected sector to he unselected. The operation of the XT generating circuit ISO will be described later with reference to Figs. 9A and 9B.
Fig. 8 is a circuit diagram of the predetermined potential detection circuit 160, which detects a given negative voltage (for example, -3 V) in the process of a transition in which the negative voltage NEOP changes from Vss to a negative voltage (for example, -6 V) necessary for the erasing at the time of erasing. The given voltage detection circuit 160 includes a NAND gate 161, inverters 162, 172-174, N-channel transistors 163, 167, 169. 170 and 175, and P*-channe] transistors 164, 165, -10* 166, 168 and 171. The negative voltage NEOP gencrated by the negative voltage generating circuit 420 is applied to the gate of the P-channel transistor 165. rnlc NAND gate 1 61 receives a signal that is at the high level during the erasing period, and opens its gate. An output ENLB of the NAND gate 161 is app]ied to the gates of the transistors 163 and 170. When the negative voltage NEG1 does not reach the given negative voltage equal to -3V from Vss, the P channel transistor 165 is OFF, and a predetermined potential detection signal NEGPL is at Vcc. Thus, the signal ENIJB is at the low level, and the output of the inverter 162 is at. the high level. At that time, the transistors 164 and 166 arc OFF. When the negative voltage NE(]P falls to the predetermined potential (-3 V), the transistor165 is turned ON, and the transistors 164 and 166 are turned ON. Thus, the potential of a node N'VD rises, and the transistor 175 is turned ON. This changes the given potential detection signal NEGPT... from the high level to the low level. Since the latch circuits of the inverters 172 and 173 retain the high level, the predetermined potential detection signal NEGPL changes to the low level. Even when the signal ENLB changes to the high level, the predetermined potential detection signal NEGPI. is maintained at the low level.
Pigs. 9A and 913 are tiniing charts of the operations of the global word line decoder 140 (Fig.6), the X.T generating circuit 150 (Fig. 7), and the predetermined potential detection circuit 160 (Fig. 8). Fig. 9A shows the operations observed at the time of programming, and Fig. 913 shows the operations observed at the time of erasing. The aforementioned leakage current flowing through the local word line decoders 240 occurs in the following mechanism. First, a description is given of the leakage current that occurs when the operation changes front the erase verification operation to the erase operation. This leakage current results from a situation in which the operation enters into the erase operation and immediately a signal (SELh for selecting the main decoder 10011 and the signal XTx for selecting the global word line decoder 140 are set to the high level (the signals GSELh and XTx are set to the high level even at the time of erase verification, and are retained at the high level at the time of the shift to the erase operation).
During the erase verification, the signals XTx and (SEI.h in the selected gional word line decoder 140 shown in Fig. 6 are both at the high levels. Therefore, the transistor 144 is in the ON state (its gate voltage is equal to Vss), and the transistor is ii) the OFF state (tis gate voltage is equal to Vss). Thus, the global word line (JWLNII is supplied with the VPXh that is at the high voltage via the transistor 144.
When the operation enters into the erase operation, the transistors 144 and 145 are both OFF because VPXh=Vss and GXDSh=Vss at the commencement of the erase operation in the state in which the, global word line decoder 140 is continuously in the
-U
selected stale, that is, the signal XTx is continuously retained at the high level. Thus, n voltage equal to Vss-i-Vta (Vta is the threshold value of the transistor 144) remains on the global word line GWI Nh. in the local word line decoder 240 (Fig. 3) or' the global word line (JWJJNh, the node F retains the voltage sufficient to pass the high voltage to the local word line P2WLn via the vertical word line VWLv during the erase verification. When the operation enters into the erase operation, GWLNhVssjVta as described above, and a voltage equal to Vss+ Vth (Vtb is the threshold value of the transistor 241) remains at the node 1!. This voltage is sufficient to turn ON the transistor 242 (Fig. 3) in the process in which XDSn falls to the negative voltage after VWJ.v becomes equal to (JWLBh becomes equal to Vec and XDSn becomes equal to Vss in the erase operation. Thus, the transistor 242 serves as a leakage path, which does not prevent the efficient supply of the negative voltage to the local word line P2WLn. Also, at that time, the global word line GWI.Nh falls to the negative voltage following XDSn. However, since VPXh is already equal to \ss, the node F retains the voltage equal to Vss+Vth until (3 WI Nh falls to a voltage that turns ON the transistor 241. Therefore, there is the leakage current until GWLNh falls to the voltage that turns ON the transistor 241.
in contrast, according to the present embodiment, as shown in Fig. 9B, at the time of erasing, the selected global word line decoder 140 is not enabled in synchronism with the erase enable signal ER, but is enabled when it is detected that the negative voltage NEGP falls to the predetermined negative potential (-3 V) from Yss (NEGPL falls to the low level). That is, the signal XTx is retained at the low level until the negative voltage NEGP falls to the predetermined negative potential (-3 V) from Yss. In the shift from the erase verification operation to the erase operation, the signal XTx changes from the high level 1.0 the low level at the time of the above shift, and changes to the high level at the time when the negative voltage NECP falls l.o the predetermined negative potential (-3 V) from Vss.
In the global word line decoder 140 shown in Fig. 6, the signal XTx is at the low level immediately after the erase operation is initiated. Thus, the global word line decoder 140 is in the unselected state, and the transistor 144 is OTT and the transistor 145 is ON. Thus, as the sector switch control line GXDSh is falling to the negative voltage from Vss, the global word line (]WLNII is gradually falling from Vss.
That is, the gate of the transistor 242 of the local word line decoder 240, that is the node F is supplied, via the transistor 142, with the voltage that gradually falls from Vss. Thus, the transistor 242 is controlled to OFF at the commencement of the erase operation. Thus, no leakage current path occurs. After that, the global word line decoder 140 is maintained in the unselected state until the negative voltage NFGP -12-becomes equal to the predetermined negative voltage (-3 V). Then, negative voltage NEGP reaches the predetermined negative voltage (-3 V), and the predetermined potential detection signal NEGPL falls to the low level. Thus, X'l's falls so that the word line decoder 140 returns to the selectecistate. If the word line decoder 140 is continuously in the unselected state, in the transistor 145 (Fig. 6), tue potential difference between the gate voltage (=Vcc) and (3X[)Sn becomes greater as OXDSn falls towards the negative voltage. This may cause a problem about the breakdown voltage of the transistor 145. Yak ing the above into consideration, the global word line decoder 140 is switched to the selected state when NEOP reaches -3 V and the gate voltage of the transistor 145 is set at the Yss level, the problem about the breakdown voltage can be avoided.
The operation of tile unselected sectors at the time of erasing is as shown in the lower side of Fig. 9B.
As has been described previously, the local word line decoder 240 shown in I S Fig. 3 has the leakage current path that is formed at the time of programming. In order to cope with this problem, in the]ocal word line decoders 240 in the unselected sectors, the local word lines P2WLn are set to the floating state. That is, the transistors 242 and 243 are both turned OFF. This is implemented by using the floating instruction signal FLOATXBh generated by tile floating instruction signal generating circuit 121 shown in Fig. 5. The floating instruction signal.FLOATXI3II is applied to the NAND gate 147 of the global word line decoder 140 shown in Fig. 6.
As shown in Fig. 9A, at the time of programming, in the unselected sectors, tile floating instruction signal FLOATXB1I changes from the high level to the low level, and the global word line (iWLBh changes from the high level to the low level (Vss) responsive to the change of FLOATXBh. This change is the gate voltage of the transistor 243 shown in Fig. 3, and turns ON the transistor 243 from OFF. As shown in Fig. 9A, since the global word line GWLNh is retained at the low level (Vss), the transistor 242 is in the OFF state. In this manner, it is possible to prevent the leakage current path from being formed. In programming of the selected sector is, as shown in Fig. 9A, the global word line GWLNh is set to the high voltage by the charge pumping of VPXh. It is to be noted that the bit line level rises in the selected sector, and the local word line P2WLn may cause erroneous programming clue to the coupling-based rise. In order to prevent this problem, it is required to set the unselected local word lines to the ground potential Vss. Although this allow leakage currents to flow in the unselected local word line decoders 240 in tile selected sector, there is no adverse influence unless a huge number of unselected local word line decoders is employed.
Fig. 10 a circuit diagram of the global sector switch circuit (sswitchg) 180 in the horizontal direction (row direction). The global sector switch circuit 1 80 includes NAND gates I 81 and 1 83, inverters 122 and 184, P-channel transistors 1 86, 187, 188, 190, 192 and 194, and N-channcl transistors 185, 189, 191, 193, 195 and 1 96. A symbol FNSSW is a sector switch enablc signal siipplicd from the after-mentioned control circuit, a symbol (3SELh is a global word line select instruction signal, a symbol NEN is a sector switch decode signal supplied from thc drain of the transistor 192. The global sector switch circuit 180 supplies the scctor switch control line (iiXlJSh with Vs.s via the transistor 195, and supplics it with the negative voltage NF.OP via the transistor 196.
Figs. hA and JiB are timing charts of an operation of the global sector switch circuit 180 shown iii Fig. 10, Fig. I IA shows an operation at: the timc of programming, and Fig. I 18 shows an operation at the time of erasing. l'he control tine GXiSh is set to the Vss level at the time of programming, and is set to the negative voltage NEGP generated by the negative voltage generating circuit 420 and output via the transistor 196. Along with the control line (JXDSh, a sector switch control line (IXDSBh is supplied to the scetors 200h -200hy* In Fig. 1, the illustration of the sector switch control line GXDS]3h is ornitl.ed. The voltage NEGP is equal to Vss ixmnediately after the global sector switch circuit 1 80 is selected. The aforementioned predetermined potential detection signal NEGPL is equal to Yss, and the transistors 191 and 189 are turned ON, and GXDSBh is equal to Vss. When the voltage NEGF falls from Vss and becomes equal to the predetermined potential (-3 V in the aforementioned example), the voltage NEGPL switches to Vss. At that tinie, the potential of NEOP (-3 V) is output to GXDXBh via the transistors 191 and 180, l'he node NEN is set at Vss (the potential of NEGPL) via the transistor I 92, and GXDSh is output to the potential of NEGP (-3 V) via the transistor 196. In the unselected sectors, the control line (3XDSBh is maintained at the high level.
Fig. 12 a circuit diagram of (lie global sector switch circuit (sswitcl]v) 310 arranged in the vertical direction (column direction) and providcd in the column decoder 300v. I'hc circuit 3 10 has a configuration similar to that of the global sector switch circuit 1 80 arranged in the horizontal direction. More specifically, the global sector switch circuit 3 10 includes NAND gates 311, 313, inverters 312, 314, P-channel transistors 316, 317, 318, 320, 322 and 324, and N-channel transistors 315, 31 9, 321, 323, 325 and 196. The sector switch select signal AENv is output from the drain of the transistor 319, and the sector switch select signal NENv is output froni the drain of the transistor 323. The operation of the global sector switch circuit 310 will he describe(l later with reference to Figs. 14A and l4B.
Fig. 13 is a circuit diagram of the vertical word line decoder (vxclec) 340 provided in the column decoder 30th'. The vertical word line decoder 340 has a NAND gate 348, P-channel transistors 341, 342 and 343, and N-channel transistors 344, 345 and 347. The NAN)) gate 348 is supplied with a vciiical word line decoder driving signal VXTq aiid a select signal VS'LLv supplied frnn [lie after-meritioncd control circuit. The high voltage \TPXv generated by [lie high-voltage generating circuit 110 is applied to the transistors 341, 342 and 343, as shown in Fig. 12. Whmi the transistor turns ON, the high voltage VPXv is applied to the vertical word line VW1,v.
Figs. 14 And 14B are timing charts of the global sector switch circuit (sswitchv) 3 10 and the vertical word line decoder (vxdec) 340. The setting of AFNv=Vcc and NENv=NFGPVss is implemented in the global sector switches 3 I 0 in both the selected and unselected columns at the time of programming shown in Fig. 14. In the vertical word line decoder 340 in the selected column, the output. of the NAN)) gate 348 shown in Fig. 13 switches to the low level, and the transistors 343 and 347 are turned ON and OFF, respectively. Thus, the vertical word line VWLv becomes equal to VPXV of the high voltage. In the unselected vertical word line decoders 340, the output of the NAN)) gate 348 is at the high level, and the vertical word line VWLv is equal to Vss. At the time of erasing shown in Fig. 14B, the global sector switch 3 10 in the selected column sets AENv to NEGP of the negative voltage, and changes NENv to the low level after setting it to the high level. Al that time, in the global sector switch circuit 310 shown in Fig. 12, the transistor 315 is turned ON responsive to the change of the signal ENSSW to the high level, and the sector switch select signal line AFNv is set to Vss via the transistors 316 and 319.
Continuously, the sector switch select signal line AENv is set to the voltage of NEOP via the transistors 321 and 319. At the time of erasing, in the global sector switches 310 in the unselected columns, the sector switch select signal line AENv is set to the high level (Vec), and the sector switch select signal line NENv is set to the voltage of NEOP via the transistor 323.
Fig. 15 is a circuit diagram of the sector switch circuit (sswitch) 210, which has N-channel transistors 211, 212 and 231. Fig. 15 also shows the relationship between the input and output signal lines of the sector switch circuit 210. In the combination of the sector switch select signal lines AENv and NENv, (1) and (2) relate to the unselected case, and (3) arid (4) relate to the selected casc. In the combination of the voltages of the sector switch control lines GXDSh and (JXDSBh.
(5) and (7) relate to the selected case, and (6) and (8) relate to the unselected case.
As shown, the signal line XDSn is set to the voltage NEOP in the case where l5-AENv/NENv=NEOP/Vss, GXDSh/OXDSBh=NFQP/NEGl and is set to Vss in the other cases. The signal line Xi)Sn is selectively connected to the local word line P2WLn via the transistor 243 as is shown in Fig. 3, and sets the local word line P2WLn of the sector selected at the time of erasing to the negative voltage.
The first embodiment has just been described in detail. The first embodiment is capable of reducing the leakage currents that flow through the local word line decoder,s 240 shown in Fig. 3 at the time of erasing and progr;n-nming.
Second Embodiment A description will now he given of a second embodiment of the present invention. The second embodiment relates to discharging of the local word line P2WLn that is carried out after erasing.
In the local word line decoders 240 shown in Fig. 3, the local word line P2WLn is set to the negative voltage XDSn when the selected sector is erased. Thus, the local word line P2WLn is discharged to return to the Vss level after the erase.
The local word line P2WLn is discharged through the transistor 243, the signal line XDSn, the transistor 213 shown in Fig. 15, tile selector switch control line (3.XDSh shown therein, and the transistor 1 95 of the global sector switch circuit 180 shown in Fig. 10, At that time, the signal line supplied with the negative voltage NEOP (negative voltage pump path) is also discharged simultaneously through the transistors 196 and 195. The global word line GWLNn shown in Fig. 3 is discharged because it is set to tIle negative voltage at the time of erasing. This discharge is carried out via the transistor 145 of the global word line decoder 140 shown in Fig. 6. The sector switch control dine GXDSh output from tile global sector switch circuit 180 is connected to the source of the transistor 145, and the global world line GWLNh is discharged via the transistor 145, the sector switch control line (XDSh and the transistor 195 shown in Fig. 10.
Since the load on the global word line (JWLNh is much smaller than that on the local word line P2WLn, the global word line (JWLNh is discharged more quickly than the local word line P2WLn (in other words, charged up to Vss). Thus, the transistor 242 shown in Fig. 3 is turned ON and the vertical word line VWLv happens to he biased to the negative voltage. Then, in the transistor 347 of the vertical word line decoder 340 shown in Fig. 13, the voltage (negative voltage) of the N channel region (connected to VWLv) formed in the P-type well is lower than the voltage (=Vss) of the P-type well biased to Vss. In this ease, forward biasing takes place.
The second embodiment is intended to avoiding the possibility of forward biasing.
Fig. 1 7 shows the entire structure of the second embodiment. As is shown in Fig. 17, the wiring routes that are set to the negative voltage are different from those -16-shown in Fig. 1. The Selector switch control line (JXDSh extending from the global sector switch Circuit 180 is connected to the sector switch 210 of the first column to the sector switch 210 of the vth columit iii that order, and further extend, as a wiring line GXDSXh serving as a dummy wiring line, from the farthest sector switch 210 to the global sector switch 180 and the global word line decoder 140.
The wiring line (}XDSXh is connected to the source of the transistor 145 of the global word line decoder 140 shown in Fig. 6. Thns, the global word line GWLNh having the relatively low load is connected to the wiring line GXDSXh via the line P2WLn having the relatively laree load, and is discharged via the line OXDSXh. Thus, the transistor 145 follows the discharge of the local word line P2WLj, arid thus prevents the transistor 242 from turning ON.
Fig. 18 is a circuit diagram of the global sector switch circuit 180 used in the second embodiment. The same reference numerals as those shown in Fig. 10 refer to the same structural elements as those shown therein. As shown in Fig. 18, an N-channel transistor 197 is newly provided. The selector switch control line CIXDSh connected to an intermediate node between the transistors 195 and 196 passes through the sectors in turn, and is connected to the transistor 197 via the wiring line (iXI)SXh.
The transistor 197 is turned ON/OFF by the selector switch control line OXDSBh connected to the drain of the transistor 189, and is set to the high level in cases other than erasing. The biasing of the global word line GWLNh is carried out in the order of GXDSh, GXDSXh and GWLNh. Thus, it is possible to prevent the transistor 242 from turning ON clue to coupling in boosting the VPXh gate by means of the transistor 197 in the unselected local word line decoders 240 1i the sector selected at the time of reading/programming.
Fig. 19 shows the discharge operation of the second embodiment. Nodes F and U shown in Fig. 3 are substantially simultaneously discharged (to Vss).
In Fig. I?, a sector switch control line UXDSWh is used to bias the P-type wells of the transistors and is provided separate from UXDSh for driving the local woi-d line P2WLn. The line GXDSWE is intended to reduce the load on the wiring line OXDSh.
As described above, the second embodiment is capable of canceling the timing difference between the discharge of the local world lines and the discharge of the global word line.
Fig. 20 is a block diagram of a flash memory that is an embodiment of the semiconductor device according to the present invention. The flash memory is equipped with a control circuit 520, a voltage generating circuit 522, a tinier 524, an address latch 526, a Y decoder 528, an X decoder 530, a Y gatc 532, a cell matrix 534, a chip enable/output enable circuit 535, a data latch 538 and an input/output buffer 540.
The control circuit 520 has a built-in command register, arid operates in synchronism with a chip enable signal CE and a write enable signal WE externally supplied. The control circuit 520 generates timing signals'.hased on commands externally supplied via the input/output buffer 540, and supplies these timing signals to associates parts. The control circuit 520 generates the aforementioned various control signals in response to a command input. mc voltage generating circuit 522 corresponds to the voltage gcnerating circuit 540 shown in Fig. I. The timer 524 generates clocks and dining signals internally used. The address latch 526 latches an address externally suppljed, and supplies the latched address to the Y decoder 528 and the X decoder 530. The Y decoder 528 corresponds to the column decoders 300 - 3OO shown in Fig. 1. The X decoder 530 corresponds to the main decoders 1001 - 10th, shown hi Fig. 1. The chip enable/output enable circuit 536 activates the Y decoder 528 in response to the chip enable signal CE, and activates the input/output buffer 540 in response to the output enable signal QE. Data read from the cell matrix 534 is output to the outside of the flash memory via the Y gate 532, the data latch 538 and the ipput/outpiit buffe'r 540. Write data externally supplied is written into the selected memory cell in tile cell matrix 534 via the input/output buffer 540, the data latch 538 and theY gate 532.
dcacrihcd.*. The *prcccnt Ofl flo+4inSedte-c abovc-mcntjgncd embodiments butincJ-u4e-eh& -system-having a built hi flash memey
Claims (8)
1. A semiconductor device comprising: sectors having memory cells connected to local word lines; decoders selecting the sectors; and a circuit generating, in programming of a selected sector, control signals that cause the local word lines of unselected sectors to be in a floating state.
2. The semiconductor device as claimed in claim I, wherein: each of the sectors comprises a pull-up transistor and a pull-down transistor for driving one of the word lines, both transistors being driven by a corresponding one of the decoders; and the control signals turning OFF the pull-up and pull-down transistors in the unselected sectors in programming.
3. The semiconductor device as claimed in claim 1, wherein one of the decoders associated with the selected sector to be programmed sets unselected local word lines in the selected sector at a given potential via a global word line that connects said one of the decoders and the selected sector.
4. The semiconductor device as claimed in claim 1, wherein said decoders select the sectors via global word lines, the device further comprising; a dummy line; and a circuit coupling said dummy line with said global word lines at the time of discharging the local word lines after erasing using a negative voltage applied to the local word lines.
5. The semiconductor device as claimed in claim 4, further comprising a bias circuit biasing a given voltage to said dummy line in reading and programming.
6. The semiconductor device as claimed in claim 4, further comprising a further circuit generating, in erasing of a selected sector, a control signal that causes a corresponding one of the decoders associated with the selected sector to be temporarily unselected.
7. A method of controlling a semiconductor device comprising the steps of: selecting one of sectors having memory cells connected to local word lines; and generating, in programming of a selected sector, control signals that that cause the local word lines of unselected sectors to be in a floating state.
8. The method as claimed in claim 7, comprising the further steps of: coupling a dummy line with a global word line at the time of discharging the local word lines after erasing using a negative voltage applied to the local word lines.
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