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GB2440459B - High speed flip-flops and complex gates using the same - Google Patents

High speed flip-flops and complex gates using the same

Info

Publication number
GB2440459B
GB2440459B GB0719451A GB0719451A GB2440459B GB 2440459 B GB2440459 B GB 2440459B GB 0719451 A GB0719451 A GB 0719451A GB 0719451 A GB0719451 A GB 0719451A GB 2440459 B GB2440459 B GB 2440459B
Authority
GB
United Kingdom
Prior art keywords
flops
same
high speed
speed flip
complex gates
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
GB0719451A
Other versions
GB2440459A (en
GB0719451D0 (en
Inventor
Min-Su Kim
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Samsung Electronics Co Ltd
Original Assignee
Samsung Electronics Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from KR1020040024507A external-priority patent/KR20050099259A/en
Application filed by Samsung Electronics Co Ltd filed Critical Samsung Electronics Co Ltd
Publication of GB0719451D0 publication Critical patent/GB0719451D0/en
Publication of GB2440459A publication Critical patent/GB2440459A/en
Application granted granted Critical
Publication of GB2440459B publication Critical patent/GB2440459B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/353—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of field-effect transistors with internal or external positive feedback
    • H03K3/356—Bistable circuits
    • H03K3/356104—Bistable circuits using complementary field-effect transistors
    • H03K3/356113—Bistable circuits using complementary field-effect transistors using additional transistors in the input circuit
    • H03K3/356121—Bistable circuits using complementary field-effect transistors using additional transistors in the input circuit with synchronous operation
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
    • H03K19/094—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors
    • H03K19/096—Synchronous circuits, i.e. using clock signals
    • H03K19/0963—Synchronous circuits, i.e. using clock signals using transistors of complementary type
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/01—Details
    • H03K3/012—Modifications of generator to improve response time or to decrease power consumption

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Logic Circuits (AREA)
GB0719451A 2004-04-09 2007-10-04 High speed flip-flops and complex gates using the same Active GB2440459B (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
KR1020040024507A KR20050099259A (en) 2004-04-09 2004-04-09 High speed flipflops and complex gates using thereof
GB0507178A GB2413020B (en) 2004-04-09 2005-04-08 High speed flip-flops and complex gates using the same

Publications (3)

Publication Number Publication Date
GB0719451D0 GB0719451D0 (en) 2007-11-14
GB2440459A GB2440459A (en) 2008-01-30
GB2440459B true GB2440459B (en) 2008-08-13

Family

ID=38917458

Family Applications (2)

Application Number Title Priority Date Filing Date
GB0719451A Active GB2440459B (en) 2004-04-09 2007-10-04 High speed flip-flops and complex gates using the same
GB0719452A Active GB2440460B (en) 2004-04-09 2007-10-04 High speed flip-flops

Family Applications After (1)

Application Number Title Priority Date Filing Date
GB0719452A Active GB2440460B (en) 2004-04-09 2007-10-04 High speed flip-flops

Country Status (1)

Country Link
GB (2) GB2440459B (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9742382B2 (en) * 2013-05-08 2017-08-22 Qualcomm Incorporated Flip-flop for reducing dynamic power
CN114388016B (en) * 2021-12-08 2024-07-02 中天弘宇集成电路有限责任公司 Pulse signal generating circuit and memory

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5041742A (en) * 1990-05-09 1991-08-20 Motorola, Inc. Structured scan path circuit for incorporating domino logic
US5821775A (en) * 1996-12-27 1998-10-13 Intel Corporation Method and apparatus to interface monotonic and non-monotonic domino logic
US5917355A (en) * 1997-01-16 1999-06-29 Sun Microsystems, Inc. Edge-triggered staticized dynamic flip-flop with conditional shut-off mechanism
US5933038A (en) * 1997-02-25 1999-08-03 Sun Microsystems, Inc. Flip-flop with logic function incorporated therein with minimal time penalty
US6459316B1 (en) * 2000-12-08 2002-10-01 Intel Corporation Flip flop circuit
US6617902B2 (en) * 2001-03-29 2003-09-09 Kabushiki Kaisha Toshiba Semiconductor memory and holding device
US6717442B2 (en) * 2002-04-15 2004-04-06 Broadcom Corporation Dynamic to static converter with noise suppression

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5041742A (en) * 1990-05-09 1991-08-20 Motorola, Inc. Structured scan path circuit for incorporating domino logic
US5041742B1 (en) * 1990-05-09 1992-08-18 Carbonaro Joseph
US5821775A (en) * 1996-12-27 1998-10-13 Intel Corporation Method and apparatus to interface monotonic and non-monotonic domino logic
US5917355A (en) * 1997-01-16 1999-06-29 Sun Microsystems, Inc. Edge-triggered staticized dynamic flip-flop with conditional shut-off mechanism
US5933038A (en) * 1997-02-25 1999-08-03 Sun Microsystems, Inc. Flip-flop with logic function incorporated therein with minimal time penalty
US6459316B1 (en) * 2000-12-08 2002-10-01 Intel Corporation Flip flop circuit
US6617902B2 (en) * 2001-03-29 2003-09-09 Kabushiki Kaisha Toshiba Semiconductor memory and holding device
US6717442B2 (en) * 2002-04-15 2004-04-06 Broadcom Corporation Dynamic to static converter with noise suppression

Also Published As

Publication number Publication date
GB2440459A (en) 2008-01-30
GB2440460B (en) 2008-08-06
GB0719452D0 (en) 2007-11-14
GB0719451D0 (en) 2007-11-14
GB2440460A (en) 2008-01-30

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