GB2422928B - Data transmission arrangement and method - Google Patents
Data transmission arrangement and methodInfo
- Publication number
- GB2422928B GB2422928B GB0512416A GB0512416A GB2422928B GB 2422928 B GB2422928 B GB 2422928B GB 0512416 A GB0512416 A GB 0512416A GB 0512416 A GB0512416 A GB 0512416A GB 2422928 B GB2422928 B GB 2422928B
- Authority
- GB
- United Kingdom
- Prior art keywords
- data transmission
- transmission arrangement
- arrangement
- data
- transmission
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 230000005540 biological transmission Effects 0.000 title 1
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0668—Interfaces specially adapted for storage systems adopting a particular infrastructure
- G06F3/0671—In-line storage system
- G06F3/0673—Single storage device
- G06F3/068—Hybrid storage device
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F5/00—Methods or arrangements for data conversion without changing the order or content of the data handled
- G06F5/06—Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
- G06F3/061—Improving I/O performance
- G06F3/0613—Improving I/O performance in relation to throughput
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
- G06F3/0629—Configuration or reconfiguration of storage systems
- G06F3/0632—Configuration or reconfiguration of storage systems by initialisation or re-initialisation of storage systems
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/44—Arrangements for executing specific programs
- G06F9/4401—Bootstrapping
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Software Systems (AREA)
- Human Computer Interaction (AREA)
- Computer Security & Cryptography (AREA)
- Stored Programmes (AREA)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
GB0512416A GB2422928B (en) | 2005-06-17 | 2005-06-17 | Data transmission arrangement and method |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
GB0512416A GB2422928B (en) | 2005-06-17 | 2005-06-17 | Data transmission arrangement and method |
Publications (3)
Publication Number | Publication Date |
---|---|
GB0512416D0 GB0512416D0 (en) | 2005-07-27 |
GB2422928A GB2422928A (en) | 2006-08-09 |
GB2422928B true GB2422928B (en) | 2007-01-31 |
Family
ID=34855753
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
GB0512416A Active GB2422928B (en) | 2005-06-17 | 2005-06-17 | Data transmission arrangement and method |
Country Status (1)
Country | Link |
---|---|
GB (1) | GB2422928B (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8021194B2 (en) | 2005-04-25 | 2011-09-20 | Nvidia Corporation | Controlled impedance display adapter |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7793029B1 (en) * | 2005-05-17 | 2010-09-07 | Nvidia Corporation | Translation device apparatus for configuring printed circuit board connectors |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5580147A (en) * | 1978-12-12 | 1980-06-17 | Mitsubishi Electric Corp | Data transfer system |
US6822654B1 (en) * | 2001-12-31 | 2004-11-23 | Apple Computer, Inc. | Memory controller chipset |
-
2005
- 2005-06-17 GB GB0512416A patent/GB2422928B/en active Active
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5580147A (en) * | 1978-12-12 | 1980-06-17 | Mitsubishi Electric Corp | Data transfer system |
US6822654B1 (en) * | 2001-12-31 | 2004-11-23 | Apple Computer, Inc. | Memory controller chipset |
Non-Patent Citations (1)
Title |
---|
A. Bhatt, "Creating a Third Generation I/O Interconnect" [online], 2003, Intel. Available from: http://web.archive.org/web/20040716100317/www.intel.com/technology/pciexpress/devnet/docs/WhatisPCIExpress.pdf [Accessed 12 Aug 2005] * |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8021194B2 (en) | 2005-04-25 | 2011-09-20 | Nvidia Corporation | Controlled impedance display adapter |
US8021193B1 (en) | 2005-04-25 | 2011-09-20 | Nvidia Corporation | Controlled impedance display adapter |
Also Published As
Publication number | Publication date |
---|---|
GB0512416D0 (en) | 2005-07-27 |
GB2422928A (en) | 2006-08-09 |
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