GB2421593A - Combined digital and analogue controller - Google Patents

Abstract

The invention provides a combined digital and analogue controller for use in a servo control system or open loop control system for generating an analogue output signal as a function of an analogue input signal. The controller comprises a combined analogue and digital circuit. The combined circuit is adapted to implement a corresponding sampled only controller and to compensate for the time delay of the sampling means, digital filter and the signal reconstruction part of said sampled only controller by implementing a time shift in a modified digital filter. The modified filter is modified from an nth order digital filter of the type having a transfer function represented in the z-domain by the expression (a0 + a1z-1 +....+ anz-n)/(1 + b1z-1 +....+ bnz-n) or the like.

Description

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COMBiNED DiGITAL AND ANALOGUE CONTROLLER This invention rclates to combined analogue and digital controllers and in particular concerns a method and apparatus for providing controlling and/or compensating actions for both open-loop and closed-loop control/processing systems. Such systems may include electronic, electrical, mechanical, fluid, pneumatic or acoustic control

systems, for example

Before the advent of digital electronics, electronic controllers were typically constructed of analogue circuit elements that processed continuous-time electrical signals.

The pnnciplc advantages of analogue processing are speed, resolution and the existence of many known design methods. The disadvantages of analogue processing include considerations such as poor rc-configurability due to fixed function, drift of electronic components, such as capacitors, that may determine performance characteristics such as frequency response, etc. More recently, following the introduction of digital electronics, sampled-data controllers have become popular as they have advantages such as rcconfigurability by software programme and accurate repeatability of performance.

As the name implies, sampled-data controllers take measurements at regular intervals and then compute the appropriate value to be provided as an output signal.

The present invention is applicable to any system that can be controlled by processing continuous and/or sampled-data signals, although the background art will now be described more fully in the context of electronic analogue (continuous-time) and digital (sampled-data) controllers.

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One particular, problem with sampled-data systems is the unwanted time delays which occur in such processes as analogue to digital conversion (ADC), computation of the desired control output signal and then the conversion back to analogue from the digital value (1)AC), also known as signal reconstruction. A major function in a typical l)AC process is known as Zero Order Ilold, which comes about due to the fact that when the control output value is set by the DAC, it remains fixed until the next sample is taken and a new control output value is computed and applied In fundamental terms, the period during which the output value is fixed constitutes a time delay compared to a system where the output value is provided on a continuous basis. Typically the delay introduced by a Zero Order I lold circuit is one hall the sampling period of the system.

It should also be noted that more complex signal reconstruction schemes are possible than just the popular Zero Order 1-bid type There may also be additional delays due to signal noise/waveform filtering The aforementioned delays do not occur in analogue controllers, therefore much of the useful knowledge existing for continuous controller design can not be applied in any simple way to the sampled-data controller Also, the delays in sampled-data systems can lead to limitations in the performance at high frequencies where the delay has a greater effect. In closed loop systems, the operating stability can be reduced or may turn to instability if the time delays are long enough. Whilst it may be possible to overcome the worst of the effects of unwanted delay by using high speed converters, processors and high sample rates, there can be additional problems with computing precision as well as the commercial consideration of additional cost.

Attempts have been made to improve the performance of sampled-data systems by introducing enhanced digital algorithms, but such improvements are invanably a compromise between desirable responses at one region and undesirable responses or increased noise in another region of operating frequencies.

There is a general requirement therefore to provide a simple controller that can compensate at least in part for the effects of unwanted controller delays to allow the high frequency performance associated with continuous-time controllers whilst maintaining the flexibility and repeatability associated with sampled-data controllers.

According to an aspect of the invention there is provided a combined digital and analogue controller for use in a servo control system or open loop control system for generating an analogue output signal as a function of an analogue input signal, the controller comprising a combined analogue and digital circuit, the combined circuit being adapted to implement a corresponding sampled only controller and to compensate for the time delay of the sampling means, digital filter and the signal reconstruction part of said sampled only controller by implementing a time shift m a modified digital filter, the modified filter being modified from an nth order digital filter of the type having a transfer function represented in the z-domain by the expression (nO + a 1 z- 1 +... + anz-n)/( 1 + b 1 z- 1 +. ..+ bnz-n) or the like.

The modified filter may be modified from a recursive filter or a nonrecursive filter, the latter also being known as a finite impulse response or FIR jilter in which the !edback (b) coefficients are zero.

Preferably, the said analogue circuit includes means for providing a first gain aO to the analogue input signal and providing a first output signal; said digital circuit including a sampling means for sampling the said input signal and a signal reconstruction means for reconstructing a second output signal from the said modified digital filter output signal; said modified filter having a transfer function in the z-domain in which the output gain coefficients aO to an-I and an of the said unmodified digital filter are replaced by the respective gain coefficients al-aObl to an-aObn and an = 0 to provide the said modified digital filter output signal, said reconstruction means including a time delay means for introducing a time delay to the said reconstructed signal to compensate for the delay due to a) the said sampling means, b) the said signal reconstruction means c) optional post reconstruction signal processing such that the net delay of a), b) and c) is substantially zero when added to the said time shift, a summing means for producing said analogue output signal as a summation of said first and second output signals.

The combined continuous and sampled-data controller of the above aspect of the invention can nullify or at Least in part nullify the effects of unwanted time Slays to provide good high-frequency performance Indeed, a degree of additional filtering to provide beneficial effects can be implemented on the basis that additional delays introduced by filtering remain within the range of delay that can be nullified.

Additionally, embodiments of the invention can be arranged such that the continuous part of the controller provides all or most of the higher frequency characteristic.

Correspondingly, the sampled-data contribution may be small or tend to zero at high frequencies, for example in cases where the desired characteristic of the controller tends towards a simple gain at higher frequencies.

The controller of the present invention preferably demonstrates the high frequency benefits of a continuous controller whilst retaimng the benefits of a sampled-data controller The control signals generated by the controller of the present invention are typically of lower amplitude in general, and in the levels of step changes in particular, when compared to an equivalent sampled-data only controller The system to be controlled (Plant) is thus subject to a more even control signal which can reduce wear and tear in mechanical systems and provide smoother output responses closer to those achieved by continuous controllers.

As a secondary benefit it is desired that accumulated knowledge for analysis and design of continuous-time systems can be easily applied to the structure of the present invention tO Controller design is therefore more straightforward since analysis methods based on the broad experience of continuous desigii techniques may be employed.

Cost advantages may also be gained by using slower converters and processors if their delay limes do not exceed the maximum value that can be effectively nullified.

The combined controller of the present invention provides the flexibility associated with the sampled-data type, whilst the continuous part is in the form of a simple set gain function which can be easily implemented to an accuracy, resolution and stability which matches the sampled-data part Various embodiments of the invention will now be more particularly described, by way of example only, with reference to the accompanying drawings, in which Figure 1 is a block diagram of a known type of closedloop analogue control system, Figure 2 is a block diagram of a known type of sampled-data closed loop digital control system; Figure 3a is a block diagram of an analogue compensator for a continuous controller of the type shown in Figure 1; Figure 3b is a block diagram of a digital compensator clenved from the continuous compensator of Figure 3a for use in a controller of the type shown in Figure 2; Figure 3c shows the respective outputs of the controllers of Figures 3a and 3b in response to a pre-deterrnined sine-wave input signal; Figure 4a is a block diagram of a known nth order digital filter; Figure 4b is a block diagram of the digital filter of Figure 4a shown in an equivalent rearranged form; Figure 4c is a block diagram of a combined digital and analogue controller according to an embodiment of the present invention, Figure Sa is a block diagram of a continuous controller of the type shown in Figure 1 having defined s-domain transfer functions; Figure Sb is a block diagram of a sampled-date controller of the type shown in Figure 2 having equivalent transfer functions expressed in the z-domain; Figure Sc is a block diagram of an equivalent combined digital and analogue controller of an embodiment of the present invention, Figure Sd is a block diagram of a combined digital and analogue controller according to an embodiment of the present invention; Figure 6a shows the output signals of each of the controllers of Figures 5a to Sc in response to a step input signal; Figure 6b shows the output signals of the controllers of Figures 5a to Sc in response to a sine-wave input signal; Figure 6c shows the respective outputs IJ(t) of the controllers of Figures Sa to Sc; Figure 7 is a block cliagrani of a simple lilter for use with a sampled- data controller of S the present invention, Figure 8a shows the effect of the delay clue to an optional R-C filter on the system responses to the sine-wave input of Figure 6b for each of the control systems 5a to 5c, Figure 8b shows the effect of the delay due to an optional R-C filter on the output signals of the respective controllers to the sine-wave input of Figure 6c for each of the control systems 5a to Sc, Figure 9a is a block diagram of a conventional cascade biquad digital filter; Figure 9b is a block diagram of a conventional cascaded biquad filter of the type shown in Figure 9a with the elements of the filter rearranged in a modified form; Figure 9c is a block diagram of a modified biquad digital filter, Figure 9d is a block diagram of a modified cascaded biquad digital filter applied to a combined digital and analogue controller according to a further embodiment of the present invention; Figure 1 Oa is a block diagram of a simple continuous-tulle controller having a high frequency gain of 1; Figure lOb is a block diagram of a mathematically identical controller of Figure 1 Oa; Figure 10 c is a block diagram of the controller of Figure lOb with the filter part transformed into a digital filter; Figure 1 Od is a block diagram of the transformed controller of Figure 1 Oc arranged in a mathematically identical but modified form; Figure 1 Oe is a block diagram of a controller according to a further embodiment of the invention in which the high frequency characteristic of the controller is provided by the continuous-time part of the controller The invention will now be described by initial reference to a controller according to

the prior art.

In Figure 1 there is shown a block diagram for a known type of continuoustime closed-loop control system 10 which includes a continuous-time controller/compensator 12 providing a controlling signal U(t) to the item to be controlled the "Plant" 14. Many design techniques exist for determining a suitable controller s-domain characteristic, or transfer function i'(s), to achieve satisfactory responses Rr the overall system 10.

En the control system of Figure 1 the output signal Y(t) or response of the Plant 14 is subtracted from the analogue demand input signal R(t) by summing means 16 to provide an error signal E(t) which is processed by the compensator or controller 12 to provide an actuator signal U(t) for controlling the plant.

Referring now to Figure 2 an alternative to the analogue control loop of Figure 1 is shown A sampled-data closed-loop control system 20 includes a sampled-data controller/compensator providing a controlling signal to the item to be controlled (Plant) Many design techniques exist to determine as suitable controller characteristic T(z) in the z-domain to achieve satisfactory responses for the overall system 20. These techniques may include sonic derived from continuous-time systems theory or may be entirely developed directly from sampled-data methods In the control system of Figure 2 the analogue compensator 12 of Figure 1 is replaced by an ADC device in the form of' a sample and hold circuit 22 including a sample clock 24, a digital filter 26 having a transfer function T(z) in the z-domain, and a DAC in the form of a zero order holding (ZOH) device 28.

In controllers of the type shown in Figure 2 it is normal practice to calculate and apply the control values to the plant as soon as possible after the sample and hold circuit has acquired its measurement. It is the unwanted delays in tins process together with the inherent delay introduced by such reconstruction devices as the ZOTI that result in the undesirable effects to overall system performance and stability.

The system input values can be provided either as continuous-time signals R(t) or sampled-data signals R(z) as appropriate.

Figures 3a and 3b show examples of two respective controllers, one with continuous form (Figure 3a) and one with sampled-data fonii (Figure 3h). In tins case the characteristics of' the digital filter 26 in the sampleddata form have been derived from the continuous controller by means of the well-known bilinear transformation.

Figure 3c shows the outputs U(t) of the controllers of Figures 3a and 3b in response to a pre-determined sine-wave input E(t).

The delay introduced by the ZOl I can be seen in the sampled-data outpUt 30 when compared with the continuous controller output 32 This (lelay is effectively half of the sample time, T/2. Other delays such as sample and hold acquisition time and computation time have been ignored in this example.

Figure 4a shows one of the forms for a generic nth order digital filter 40 which together with the sample and hold 22 and a signal reconstruction device for example, a ZOIl output device, constitute a sampled-data controller/compensator.

Other forms of filter exist such as the cascaded Biquad form, but it will be appreciated from the description that follows that the present invention is equally applicable to any of the equivalent digital filter representations One arrangement of the invention is best explained by first looking at a different (but mathematically identical) depiction of the generic digital filter shown in Figure 4a. It is to he noted that some conventions show the b coefficients of the generic digital filter as -b and then adjust for that by making the top left summation sign +ve for the input signal E(z) as before, hut +ve for the feedback signal In the drawings that accompany this description the b coefficients are represented +ve and the feedback -ye

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The generic digital filter shown in Figure 4a can be represented in the rearranged form of Figure 4b.

The input-output relationship U(z)/F(z) of the generic digital!ltcr of Figure 4a comprises the known generic digital filter expression:- aO + alz + a2Z2 + + anz U(z)/E(z) = (1) I +blzi +b2z2 + + bnz n the rearranged form of Figure 4b the a coefficients associated with each time delay period zi, z2. . are modified when compared with the corresponding coefficients of the generic arrangement of Figure 4a This compensates for the effect of introducing a separate path 42 for the simple gain a() The coefficients of the generic digital filter form of Figure 4a, al to an, are replaced by the modified coefficients al- aObl to an-a0bn in the block 44 of modified form of Figure 4b. The b coefficients remain unchanged. The input/output relationship of the modified filter arrangement of Figure 4b is.

(al-aObl)z' + (a2-aOb2)z2 + + (an-a0bn)z'1 U(z)/E(z) aO + ( 2) I -F blz + b2z2 + + bnz which is equal to.

aO(l + bIz + b2z2 +.. + bnz1) -F (al-a0bl)z + (a2-aOb2)z2 f. + (an-a0bn) z1 I + blz + b2z2 + + bnz (3) which reduces back to: aO + al z1 + a2z2 + + anz U(z)/E(z) (4) 1 + blz + b2z2 + + bnz' Which is the same as ecluation (I) which describes the generic digital filter of Figure 4a An embodiment of the present invention will now be described by reference to Figure 4c.

The simple gain function (value aO) shown in Figure 4b section 42 is timeindependent and is implemented as a simple continuous-time function in an analogue iS circuit outside of the sampled-data controller.

With reference to Figure 4b section 44, where the blocks marked liz are the well- known representation for a delay of 1 sample period, it can be seen that the output signal from section 44 is made up of the combination of the signals from blocks a 1 - aObl, a2 -aOb2, an - a0bn In the further modified controller arrangement of Figure 4c blocks al -- nOb!, a2- aOb2, . , an -- aObn have been moved up one stage such that their inputs are now fed from the original points of the generic arrangement of Figure 4a, but I sample period earlier, such thai they provide the original output of the modified arrangement of Figure 4b section 44, but again, moved in time, I sample period earlier Figure 4c shows the arrangement of the continuous gain aO and the transformed digital filter, together with the sample and hold block, the ZOH block and a delay block 46 to provide synchronisation between the sample and hold action and the ZOH output function.

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The timing shifts in the sampled-data controller part of the combined controller of Figure 4c consists of an advancement of I sample in the digital filter due to the new arrangement plus a delay of " sample penod due to the ZOH plus any other delays due to effects followmg the ZO}l function such as wave smoothing etc. The total time advance is therefore 14 sample period minus any further delays following the ZOH. Delays following the ZOH might be due to the response time of a DAC or delay due to additional filtering (shown as optional filter 48 in Figure 4c).

To correct the overall controller time-shift back to zero, a delay of (14 sample - delays following the ZOll) is introduced between the sample and hold clock 50 and the application of the signal to the ZON 28.

It will be appreciated that as long as the sample and hold acquisition delay and the cemputation delay are completed within a time period equal to 14 sample period minus delays following the ZOH, the overall timeshift will be maintained at zero as required, that is to say substantially the same as a continuous controller.

Referring now to Figures 5a to Sc.

Figure 5a shows a closed-loop continuous-time controller application with a Plant characteristic (transfer function) that could represent say a position control actuator and load The continuous-time controller of Figure 5a is of the well known Pill) type with additional noise!lter on the clifTerentiating element. The precise characteristic of' the controller has been found by trial to give acceptable results for the overall system.

Figure Sb shows a sampled-data version of the controller of Figure 5a with the continuous-time controller 12 replaced by a digital controller. ftc values of the z- domain transfer function for the digital controller are found by the well- known bilinear transform method. As previously discussed, the unwanted V2 sample time delay introduced by the ZOH will result in a significantly different response to that obtained by the continuous-time version of Figure 5a.

Figure Sc shows an equivalent controller arrangement according to the present invention where the continuous-time gain has been added, the digital filter characteristic has been transformed as previously described and the appropriate sample delay has been added to the ZOl-l output function, to give an overall time shift of zero Figure 6a shows the output responses to a step input of the systems shown in Figures Sa to Sc The response 50 of the controller of Figure Sc is quite similar to the reference continuous response 52 of the controller of Figure 5a. There is not an exact correspondence as there are inherent deviations due to the Bilinear Transform used to derive the Digital Filter values and also there is an amplitude effect for the ZOH, especially at higher frequencies. In addition it will be appreciated that even perfect sampled- data systems would only give correspondence at the sample points The response 54 of the SampLed-Data only system of Figure Sb is much less stable, as it is substantially affected by the ZOH delay, which it is unable to abcount for.

The comparison of controller responses shown in Figure 6a confirms that the controller of the present invention can account fir the undesirable ZOH delay inherent in sampled-data controllem IS Figure 6b shows the responses of the same systems of Figures Sa, Sb and Sc, to a 2KHz sine-wave input Again, it is clear that the responses of combined controller of Figure Sc remain close to the reference response 52, whilst the Sampled-Data only system is again substantially affected by the ZOM delay.

Figure 6c shows the signal of the controlled outputs U(t). These signals have all been scaled by the same factor and then separated for easy companson. The output SO from the controller of Figure Sc is seen to be substantially closer to the desirable continuous controller signal 52 than the Sampled-Data only output 54.

In particular the signal from the controller of Figure 5c is smoother than that from the Sampled-Data only controller.

Figure 7 shows a very simple filter example that can provide additional filtenng for the Sampled-Data only system and the system incorporating the invention This filter has a delay of 4Ops over much of the frequency range of interest.

In the case of an embodiment of the invention, the delay between the Sample and Hold Block and the 7OFI block has been reduced to lOps to account lbr the additional filter delay.

Figure 8a shows the effect of the delay on the system responses to the 2KHz sine- wave input previously described with reference to Figure 6b with the combined controller including an optional R-C filter of 1000 ohm, 4Onf added to the Zero Order I bId. The effect on the output 50 of the control system including the controller of Figure Sc is seen to be very small On the other hand, the response 54 for the Sampled-Data only system of Figure Sb can be seen to be substantially further away from the desired response 52.

Figure 8b shows that the controller output 0(t) from the controller of Figure Sc can be smoothed by the optional filtering 48 to give a signal not too dissimilar to the desirable charactenstic of the Continuous-time controller.

The controller output signal from the Sampled-Data only controller is somewhat smoother than before, but in fact makes larger jumps which are still sharp in nature.

The present invention thus enables additional filtering without the loss of performance or stability that may he seen in Sampled-Data only control systems.

Figures 9a to 9c show an example of an alternative Digital Filter form the 2 x Biquad, or cascaded Biquad form.

Figure 9a shows a conventional cascaded Biquad arrangement.

Figure 9b shows a cascaded sequence of two generic Biquad digital filters, where the form of each Biquad has been rearranged by suitable transforming in the same way that the generic filter of Figure 4a is transformed in Figure 4b for use in the present invention.

As shown in Figure 9b each Biquad is split into a Section A and a Section B. Sections IA, IB, 2A and 2B are designated by the enclosed regions 60, 62, 64 and 66 in the drawing of Figure 9b.

In terms input/output relationships for a single Biquad IJ(z) = E(z) . (A+ B) And for the cascaded Biquads U2(z) = E1(z) . ( IA+lB) . (2A+2B

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U2(z) = E1(z) . ( IA.2A + IA 2B + IB.2A + IB.2B) This is shown in the arrangement of Figure 9c and substantially eorrcsponds to the transformed arrangement of Figure 4b Figure 9d shows how the present invention is applied to the eascaded Biquad block diagram of Figure 9c As demonstrated in the previous example, the blocks shown in Figure 9e representing the output coefficients in section 2866 are shifted to give a time-advance of I sample penod input to output delay for most of the signal paths. The only remaining mampulation is to ensure that the path through block 68 aO' is also time-advanced by 1 sample pcriod. This is achieved creating the two additional signals 70 an 72 which provide the input to the aforementioned block 68 aO'.

Thus the present invention can be applied to digital filter forms other than the simple generic form shown in Fig. 4a.

The following description describes how in some cases the continuous-time part of the controller of the present invention can be made to dominatethe controller output signal at high frequencies.

Figures lOa to lOc show, for a simple controller example, the steps for one method of miplementing the current invention such that the highfrequency characteristic is provided mainly by the continuous-time part, and thereby provides the advantageous effects described earlier Figure lOa shows a simple continuous-time controller where the high-frequency characteristic is simply a gain of I Figure lOb shows a mathematically identical form of Figure lOa, that is to say the controller is split into a simple gain of 1 and a filter whose high-frequency output reduces to zero at high frequencies.

It is straightforward to show the equivalence of the arrangements of Figures lOa and lOb.

The equation for Figure lOa is:- S+B LJ(t)/E(t) = (5) S+A The equation tbr Figure lOb is

B-A

U(t)/E(t) = I (6) S+A S+A +B-A S+B = = (7) S+A S+A Which is the same as equatIon (5) which describes Figure IOa Figure 10c shows a version of Figure lOb where the filter part has been transformed by some suitable trarisfbrrn like the well-known Bilinear Transform, into a digital filter.

It will be readily understood that the Bilinear Transform and other transforms are only approximations and may deviate from the ideal, especially as the operating frequency approaches the Nyquist, or half sample rate, frequency Therefore, the high- frequency output of such digital filter designs will not reduce completely to zero at high-frequencies. I lowever, they will provide only relatively small levels of output at these points.

FigurelOd shows Figure lOc transformed into an identical mathematical form. Figure lOc shows the principles of the present invention applied to the digital filter of Figure I Od. In this case the substantial part of the controller output is provided by the Continuous-time element, as desired.

The embodiments described herein all refer to the well-known and simple Zero Order I bId (ZOH) type sampled-time to continuous-time converter, or signal reconstruction device. It will be appreciated that the invention can be applied to controllers having any type of signal reconstruction converter that introduces unwanted time delays, whether it be of the ZOH type, or any other type

Claims (11)

1. I. A combined digital and analogue controller for use in a servo control system or open loop control system for generating an analogue output signal as a function of an analogue input signal, the controller comprising a combined analogue and digital circuit, the combined circuit being adapted to implement a corresponding sampled only controller and to compensate for the time delay of the sampling means, digital filter and the signal reconstruction part of said sampled only controller by implementing a time shift in a modified digital filter, the modified filter being modified from an nth order digital filter of the type having a transfer function represented in the z-domain by the expression (aO + alz-l + + anz-n)/(l + blz-l + ..+ bnz-n) or the like.
2. 2 A controller as claimed in Claim 1 wherein: said analogue circuit including means for providing a first gain aO to the analogue input signal and providmg a first output signal; said digital circuit including a sampling means for sampling the said input signal and a signal reconstruction means for reconstructing a second output signal from the said modified digital filter output signal; said modified filter having a transfer function in the z-domain in which the output gain coefficients aO to an-l and an of the said unmodified digital filter are replaced by the respective gain coefficients al-aObl to an-aObn and an = 0 to provide the said modified digital filter output signal, said reconstruction means including a time delay means for introducing a time delay to the said reconstructed signal to compensate for the delay due to a) the said sampling means, b) the said signal reconstruction means c) optional post reconstruction signal processing such that the net delay of a), b) and c) is substantially zero when added to the said time shift; a summing means for producing said analogue output signal as a summation of said first and second output signals.
3. 3. A controller as claimed in Claim 1 or Claim 2 wherein the said time shift comprises a time shift advance of one sample period
4. 4. A controller as claimed in any preceding claim wherein the said reconstruction means comprises a holding means
5. 5. A controller as claimed in Claim 4 wherein the said holding means comprises a Zero Order I biding means.
6. 6 A controller as claimed in any preceding claim wherein the said digital circuit has substantially no effect on the output of the controller at high operating frequencies.
7. 7. A controller as claimed in any preceding claim further comprising post reconstruction processing means for processing the Output signal from the said reconstruction means.
8. 8 A controller as claimed in Claim 7 wherein the said post reconstruction processing means comprises filter means for filtering the output signal from the said reconstruction means.
9. 9 A controller as claimed in Claim K wherein thc said filter means compnses a smoothing filter.
10. 10. A controller as claimed in any preceding claim wherein the said modified filter is a modified cascaded biquad digital filter.
11. 11. A controller as claimed in any preceding claim wherein the said modified filter is a modified nth order recursive digital filter 12 A controller as claimed in any one of claims 1 to 10 wherein the said modified filter is a modified non-recursive digital filter