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GB2418269B - Reusable hardware IP protocol method for a system-on-chip device - Google Patents

Reusable hardware IP protocol method for a system-on-chip device

Info

Publication number
GB2418269B
GB2418269B GB0420483A GB0420483A GB2418269B GB 2418269 B GB2418269 B GB 2418269B GB 0420483 A GB0420483 A GB 0420483A GB 0420483 A GB0420483 A GB 0420483A GB 2418269 B GB2418269 B GB 2418269B
Authority
GB
United Kingdom
Prior art keywords
chip device
protocol method
reusable hardware
reusable
hardware
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
GB0420483A
Other versions
GB0420483D0 (en
GB2418269A (en
Inventor
Fu-Chiung Cheng
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Tatung Co Ltd
Original Assignee
Tatung Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tatung Co Ltd filed Critical Tatung Co Ltd
Priority to GB0420483A priority Critical patent/GB2418269B/en
Publication of GB0420483D0 publication Critical patent/GB0420483D0/en
Publication of GB2418269A publication Critical patent/GB2418269A/en
Application granted granted Critical
Publication of GB2418269B publication Critical patent/GB2418269B/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/32—Circuit design at the digital level
    • G06F30/327—Logic synthesis; Behaviour synthesis, e.g. mapping logic, HDL to netlist, high-level language to RTL or netlist
    • G06F17/505—

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Evolutionary Computation (AREA)
  • Geometry (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Communication Control (AREA)
GB0420483A 2004-09-15 2004-09-15 Reusable hardware IP protocol method for a system-on-chip device Expired - Fee Related GB2418269B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
GB0420483A GB2418269B (en) 2004-09-15 2004-09-15 Reusable hardware IP protocol method for a system-on-chip device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
GB0420483A GB2418269B (en) 2004-09-15 2004-09-15 Reusable hardware IP protocol method for a system-on-chip device

Publications (3)

Publication Number Publication Date
GB0420483D0 GB0420483D0 (en) 2004-10-20
GB2418269A GB2418269A (en) 2006-03-22
GB2418269B true GB2418269B (en) 2010-07-21

Family

ID=33306592

Family Applications (1)

Application Number Title Priority Date Filing Date
GB0420483A Expired - Fee Related GB2418269B (en) 2004-09-15 2004-09-15 Reusable hardware IP protocol method for a system-on-chip device

Country Status (1)

Country Link
GB (1) GB2418269B (en)

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6073267A (en) * 1996-09-25 2000-06-06 Nec Corporation Semiconductor integrated circuit with error detecting circuit
WO2001095161A2 (en) * 2000-06-02 2001-12-13 Virtio Corporation Method and system for virtual prototyping
US20020101257A1 (en) * 2001-01-30 2002-08-01 Takayuki Kawahara Semiconductor device
US6446243B1 (en) * 1999-04-23 2002-09-03 Novas Software, Inc. Method for functional verification of VLSI circuit designs utilizing reusable functional blocks or intellectual property cores
US20020144216A1 (en) * 2001-01-31 2002-10-03 Leonard Elizabeth A. Method for rapid, reusable system on a chip functional verification
US20040024895A1 (en) * 2000-05-25 2004-02-05 Michel Henrion Method for mutual transfers of control parameters through a communications network
US20040098701A1 (en) * 2002-11-15 2004-05-20 Mentor Graphics Corp. Automated repartitioning of hardware and software components in an embedded system

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6073267A (en) * 1996-09-25 2000-06-06 Nec Corporation Semiconductor integrated circuit with error detecting circuit
US6446243B1 (en) * 1999-04-23 2002-09-03 Novas Software, Inc. Method for functional verification of VLSI circuit designs utilizing reusable functional blocks or intellectual property cores
US20040024895A1 (en) * 2000-05-25 2004-02-05 Michel Henrion Method for mutual transfers of control parameters through a communications network
WO2001095161A2 (en) * 2000-06-02 2001-12-13 Virtio Corporation Method and system for virtual prototyping
US20020101257A1 (en) * 2001-01-30 2002-08-01 Takayuki Kawahara Semiconductor device
US20020144216A1 (en) * 2001-01-31 2002-10-03 Leonard Elizabeth A. Method for rapid, reusable system on a chip functional verification
US20040098701A1 (en) * 2002-11-15 2004-05-20 Mentor Graphics Corp. Automated repartitioning of hardware and software components in an embedded system

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
http://www.circuitcellar.com/pastissues/articles/Anderson109/Anderson.pdf *

Also Published As

Publication number Publication date
GB0420483D0 (en) 2004-10-20
GB2418269A (en) 2006-03-22

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Legal Events

Date Code Title Description
732E Amendments to the register in respect of changes of name or changes affecting rights (sect. 32/1977)

Free format text: REGISTERED BETWEEN 20101021 AND 20101027

PCNP Patent ceased through non-payment of renewal fee

Effective date: 20140915