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GB2409767A - Copper alloy interconnection layer - Google Patents

Copper alloy interconnection layer Download PDF

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Publication number
GB2409767A
GB2409767A GB0506567A GB0506567A GB2409767A GB 2409767 A GB2409767 A GB 2409767A GB 0506567 A GB0506567 A GB 0506567A GB 0506567 A GB0506567 A GB 0506567A GB 2409767 A GB2409767 A GB 2409767A
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United Kingdom
Prior art keywords
copper
film
interconnection
layer
treatment
Prior art date
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Application number
GB0506567A
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GB0506567D0 (en
Inventor
Hidemitsu Aoki
Hiroaki Tomimori
Norio Okada
Tatsuya Usami
Koichi Ohto
Takamasa Tanikuni
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NEC Electronics Corp
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NEC Electronics Corp
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Priority claimed from JP2001044949A external-priority patent/JP4535629B2/en
Application filed by NEC Electronics Corp filed Critical NEC Electronics Corp
Publication of GB0506567D0 publication Critical patent/GB0506567D0/en
Publication of GB2409767A publication Critical patent/GB2409767A/en
Withdrawn legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H—ELECTRICITY
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02041—Cleaning
    • H01L21/02057—Cleaning during device manufacture
    • H01L21/02068—Cleaning during device manufacture during, before or after processing of conductive layers, e.g. polysilicon or amorphous silicon layers
    • H01L21/02074—Cleaning during device manufacture during, before or after processing of conductive layers, e.g. polysilicon or amorphous silicon layers the processing being a planarization of conductive layers
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/0217—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz
    • H—ELECTRICITY
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02205—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition
    • H01L21/02208—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition the precursor containing a compound comprising Si
    • H01L21/02211—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition the precursor containing a compound comprising Si the compound being a silane, e.g. disilane, methylsilane or chlorosilane
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
    • H01L21/02274—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition in the presence of a plasma [PECVD]
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    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H01L21/76834—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers formation of thin insulating films on the sidewalls or on top of conductors
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/7684—Smoothing; Planarisation
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    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
    • H01L21/76846—Layer combinations
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
    • H01L21/76849—Barrier, adhesion or liner layers formed in openings in a dielectric the layer being positioned on top of the main fill metal
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76853—Barrier, adhesion or liner layers characterized by particular after-treatment steps
    • H01L21/76861—Post-treatment or after-treatment not introducing additional chemical elements into the layer
    • H01L21/76864—Thermal treatment
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76867—Barrier, adhesion or liner layers characterized by methods of formation other than PVD, CVD or deposition from a liquids
    • H—ELECTRICITY
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    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204—Conductive materials
    • H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
    • H01L23/53228—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being copper
    • H01L23/53238—Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

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  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

In a damascene method, trenches in interlayer insulation 12 are filled with a barrier layer, a seed layer and a copper containing layer 17. The surface of the copper layer 17 is kept free of copper oxide by not exposing the device to an oxygen containing atmosphere. The oxide-free surface of the copper is subjected to a N2 or NH3 nitriding plasma treatment to form a copper nitride (CuN) layer 24. A silicon containing copper diffusion prevention layer 18 (e.g. SiN, SiON, SiC, SiCOH) is formed by plasma CVD. The copper nitride layer 24 suppresses diffusion of silicon into the copper layer 17 such that the thickness of the copper silicide layer is reduced. Interconnection resistance is thus reduced.

Description

METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE
BACKGROUND OF THE INVENTION
The present invention relates to a method of manufacturing a semiconductor device which includes the step of forming a copper- containing film, and more particularly to a method of manufacturing a semiconductor device having an interconnection, an interconnection connecting plug, a pad section, or the like, made of copper or a copper alloy.
In recent years, copper and copper alloys have been widely used as the material for interconnections and connecting plugs to achieve higher speed operation. Using these metals, the interconnections and the like are generally formed by the damascene method.
Fig. 5 is a series of views illustrating the steps of a known method of forming a copper interconnection. $ First, as shown in Fig. 5(a), after an insulating film 10 and an interlayer insulating film 12 are formed, in this order, on a semiconductor substrate (not shown in the drawings), an interconnection trench is set within the interlayer insulating film 12, and thereon a barrier metal film 14 made of Ta, TaN or such and a seed copper film 15 are formed, in succession, and then a copper film 16 is formed by the plating method.
The semiconductor wafer 1 in this state is subjected to the chemical mechanical polishing (CMP) and copper lying outside of the interconnection trench is removed, while copper lying inside of the trench is left as it is, whereby a copper interconnection 17 is formed.
At this, copper oxide 21 is produced on the copper interconnection 17, and a carboxylic acid cleaning is performed (Fig. 5(b)) for removing this copper oxide 21.
In this way, copper oxide which may cause an increase in interconnection resistance or contact resistance can be eliminated (Fig. 5(c)). After that, as shown in Fig. 5(d), a silicon nitride film 18 is formed and thereon an interlayer insulating film 19 is formed.
In such steps of forming a copper interconnection, it is essential to remove copper oxide which is formed on the copper surface so that the electrical resistance may be prevented from increasing. While copper oxide is removed with carboxylic acid in the above method, other methods such as a method by a plasma treatment with a reducing gas are also known. For example, in a method described in iiTDDB Improvement in Cu Metallization under Bias Stress" by J. Noguchi et al. (IEEE 38th Annual International Reliability Physics Symposium, San Jose, California, 2000, pp. 339-343), a plasma treatment with a hydrogen or ammonia gas is carried out to achieve the reduction of CuO which is formed on the surface of the copper interconnection to Cu. along with the formation of a Cu layer thereon. Moreover, it is described therein that once Cur is formed, this may function as a o protective film, and when a copper- diffusion prevention film of SiN or the like is grown thereon, the CuN layer can suppress the formation of the copper silicide layer in the copper interconnection and, therefore, can restrain the increase in electrical resistance.
However, the known techniques described above have the following problems.
In a method comprising the step of removing a copper oxide film with carboxylic acid, after the cleaning to remove the copper oxide film is carried out, lo the wafer is taken out from the cleaning equipment and transferred for the step of growing the films. During the transfer, the wafer may be exposed to the air so that the copper surface therein may be Deoxidized, leading to a problem of the increase in electrical resistance and the decrease in adhesion between the copper interconnection and the copper-diffusion prevention film formed thereon.
Meanwhile, although a method with a reducing plasma treatment can control the increase in resistance in a certain degree, the method brings about another problem of the decrease in interconnection lifetime. In fact, it is the present inventors who first confirmed, through experiments, that a reducing plasma treatment may lower the interconnection lifetime, due to the electromigration or the like, and give rise to a variation in resistance. To remove the copper oxide film thoroughly by the plasma treatment, it is necessary to employ considerably rigorous conditions for the plasma treatment and, as a result, the copper surface becomes rugged. Furthermore, since the nitridation to form CuN proceeds with copper oxide still partially remaining on the copper surface, the film thickness of the CuN becomes non-uniform and, herewith, the film thickness of a copper silicide layer that is to be formed in the copper interconnection becomes also non uniform. This presumably causes a lowering of the interconnection lifetime and produces variation in resistance.
Further, in the method using the reducing plasma treatment, there are occasions where the film thickness of the copper-diffusion prevention film becomes non- uniform, owing to the unevenness of the underlying layer surface. This necessitates, in the later step of hole etching to form an interconnection connecting plug, to perform overetching further more so as to remove that copper-diffusion prevention film so that the degradation of the copper interconnection surface may be brought about by the plasma exposure.
SUMMARY OF THE INVENTION
The present invention provides a method of manufacturing a semiconductor device, the method comprising the steps of: forming a copper-containing film on a semiconductor substrate; applying a nitriding treatment to the surface of said copper-containing film without allowing the semiconductor substrate to be exposed to an oxygen-containing atmosphere; and forming a copper diffusion prevention film comprising a silicon on said coppercontaining film which has been subjected to the nitriding treatment. (
In the afore-mentioned manufacturing method, a nitriding treatment is applied to the surface of a copper-containing film without allowing a semiconductor substrate to be exposed to an oxygen-containing atmosphere. In the known method described in the BACKGROUND, wherein a copper oxide film is removed by a plasma treatment with a reducing gas, it is necessary to conduct the plasma treatment under somewhat rigorous conditions. For instance, in order to remove copper oxide, the plasma atmosphere is required to have a high reducing capability. This makes the surface of the copper-containing film rugged, causing the increase in interconnection resistance and contact resistance. Contrary to this, the plasma treatment in the present invention can be carried out under milder conditions, because the treatment does not aim at removing copper oxide.
Further, in the afore-mentioned known techniques, even if the treatment is conducted in a plasma atmosphere with a high reducing capability, a copper oxide film cannot help remaining in part. As against this, in the present invention, since the nitriding treatment is applied to a clean copper surface where no copper oxide film remains, the film thickness and the film quality of a CuN film which is formed by the nitriding treatment can be made uniform and, herewith, the film thickness of a copper silicide layer to be formed in the copper interconnection becomes uniform As a result, the following effects can be attained.
First, the increase in electrical resistance which may be brought about by oxidation of the copper containing film surface can be suppressed. In the afore-mentioned manufacturing methods, a protective film made of CuN is homogeneously formed to an uniform thickness over the copper- containing film so that a clean copper-containing metal surface where no copper oxide film is formed is directly covered with the protective film. This protects copper from oxidation with effect in the subsequent steps, and prevents the electrical resistance from increasing.
Secondly, the interconnection lifetime is lengthened. In the aforementioned manufacturing methods, CuN is formed, while the nitriding treatment is being applied to the surface of the copper-containing film, and once a copper-diffusion prevention film comprising silicon is formed, this CuN restrains silicon from diffusing into the copper-containing film. However, CuN does not cut off the silicon diffusion completely, and a small amount of silicon passes through CuN and reaches inside of the copper-containing film to form a thin copper silicide layer in the vicinity of the surface of the copper-containing film. As described above, the protective film made of CuN is homogeneously formed to a uniform thickness so that the silicide layer formed thereunder is a thin layer, homogeneous and having a uniform thickness. The formation of such a silicide layer is considered to be the cause for lengthening of the interconnection lifetime. A silicide layer of this sort can be also formed by the step of forming a silicon nitride film 18, in the method
described in the BACKGROUND, referring to Fig. 5.
However, because silicon nitride, in this instance, is deposited without a copper nitride layer being formed, silicon that is the very constituting material for silicon nitride diffuses into the copper interconnection, excessively, and a thick silicide layer is formed, causing a problem of the increase in interconnection - resistance and contact resistance. Meanwhile, in the afore-mentioned method with a reducing plasma treatment, the formation of a silicide layer itself is considered to be suppressed. Unlike these known techniques, in the present invention, because a CuN layer, capable to restrain silicon diffusion appropriately, is formed, a silicide layer can be formed homogeneously and uniformly to a thin film thickness. This enables both an improvement of the interconnection lifetime and a lowering of the electrical resistance, to be achieved together.
Thirdly, because the copper-diffusion prevention film can be formed homogeneously and with its film thickness well under control, the degradation of the copper-containing film in the subsequent steps can be prevented from occurring. For instance, when the present invention is applied to a method of forming a copper interconnection, after copper interconnection made of a copper-containing film is formed, an interconnection connecting plug is to be formed thereon.
In the step of hole etching, thereat, it is required to remove the copperdiffusion prevention film and expose the copper interconnection. In order to remove the copper-diffusion prevention film lying in a plurality of holes for sure, it is essential to make a certain amount of overetching. Nevertheless, in the present invention, as the copper-diffusion prevention film can be formed homogeneously and with its film thickness well under control, the film thickness for the copper-diffusion prevention film itself can be made thinner than the conventional one, and, as a result, the amount of overetching can be well reduced. Doing this, the alteration of the resist form can be lessened and the linewidth accuracy of the fabricated form, heightened.
Further, the thickness of the resist can be reduced so that more minute fabrication thereof can be made. In addition, the amount of deposits generated after etching may drop, and besides shavings and damages of the underlying copper interconnection due to overetching can be reduced. Further, as the film thickness of the copper-diffusion prevention film can be set thin, parasitic capacitances between horizontally adjacent JO interconnections and within the interconnection along the direction of the substrate thickness can be reduced.
As a result, cross talk between interconnections can be suppressed.
As set forth above, the present invention can make the film thickness and the film quality of CuN that is formed by the nitriding treatment uniform and, herewith, can form a copper silicide layer to an uniform thickness in the copper interconnection. Consequently, the present invention can improve the interconnection lifetime, while preventing the resistance of a copper-containing film from increasing.
Furthermore, because the present invention can form a copper diffusion prevention film homogeneously with a film thickness well under control, it is possible to prevent the degradation of the copper containing film from occurring in the subsequent steps.
BRIEF DESCRIPTION OF THE DRAWINGS
The invention will now be described in more detail by way of example with reference to the accompanying drawings.
Fig. 1 is a series of schematic cross-sectional views illustrating the steps of a manufacturing method of a semiconductor device according to the present invention.
Fig. 2 is a series of schematic cross-sectional views illustrating further steps of the manufacturing method of a semiconductor device according to the present invention.
Fig. 3 is a series of schematic cross-sectional views illustrating further steps of the manufacturing method of a semiconductor device according to the present invention.
Fig. 4 is a series of schematic cross-sectional views illustrating further steps of the manufacturing method of a semiconductor device according to the present invention.
Fig. 5 is a series of schematic cross-sectional views illustrating the steps of a known manufacturing method of a semiconductor device.
Fig. 6 is a pair of views in explaining a method of evaluating the interconnection resistances and the interconnection lifetimes in Examples.
Fig. 7 is a graph showing the evaluation results of the interconnection resistances in Examples.
Fig. 8 is a graph showing the evaluation results of the interconnection lifetimes in Examples.
Fig. 9 is a graph showing the evaluation results of the silicide occupation ratios in Cases for Reference.
In the accompanying drawings, referential numerals mean as follows; 1: silicon wafer, 10: insulating film, 12: interlayer insulating film, 14: barrier metal film, 15: seed copper film, 16: copper film, 17: copper interconnection, 18: silicon nitride film, 19: interlayer insulating film, 21: copper oxide, 22: anticorrosive, 24: copper nitride layer, 25: copper silicide layer, 27: interlayer connecting plug.
DETAILED DESCRIPTION
A copper-containing film as used in the described embodiments is either a copper film or a copper alloy film which contains at least 80 wt. % of copper and preferably at least 90 wt. % of copper. A copper alloy contains, as another component, a different element such as Mg, Se, Zr, Hf. Nb, Ta, Cr. Mo, or the like.
A copper-diffusion prevention film as used in the described embodiments is a film comprising a silicon, which is set to prevent copper from diffusing into and within the interlayer insulating film and is made of, for example, SiN, SioN, SiC, SiCoH or the like.
In the present examples, a solution, especially an aqueous solution containing any of carboxylic acid compounds is preferably used as a cleaning agent.
Carboxylic acid compounds as used herein include carboxylic acids and their salts. It is preferable to employ one or more compounds selected from the group consisting of oxalic acid, citric acid, malic acid, maleic acid, succinic acid, tartaric acid, malonic acid and their salts. Among these compounds, oxalic acid, in particular, is preferably used owing to its effectiveness to remove copper oxide. Oxalic acid has a good capability to form a chelate complex effectively with copper oxide, once copper oxide is produced by the Cu-CMP. Meanwhile, copper atoms in the Cu film constituting the interconnection are held together by the metallic bonding so that they are hard to form a complex with oxalic acid and spared from being etched.
In addition, since metals such as TiN, Ta, TaN, and TaSiN that may constitute a barrier film are also hard to form a complex with oxalic acid, they are also spared from being etched. Therefore, through the use of oxalic acid, CuOx in the form of a film and Cu particles that remain on the surface can be selectively removed, without etching the coppercontaining film or the barrier metal film. The total content of carboxylic acid with respect to the whole amount of the cleaning agent is set to be preferably 0.005 - 10 wt. % and more preferably 0.01 - 1 wt. %.
The cleaning agent as used in the present example may contain a completing agent. As a completing agent, any of polyaminocarboxylic acid compounds or ammonium fluoride may be preferably used. Among polyaminocarboxylic compounds, compounds such as ethylenediaminetetraacetic acid (EDTA), trans-1, 2- cyclohexanediaminetetraacetic acid (CyDTA), nitrilotriacetic acid (NTA), diethylenetriaminepentaacetic acid (DTPA), N-(2- hydroxyethyl) ethylenediamine-N, N', N,-triacetic acid (EDTA-OH) and their salts are preferable. If a salt is to be employed, a salt that does not adversely affect characteristics of the semiconductor device is preferable, and especially a salt containing no metal such as ammonium salt is preferable. The content of the complexing agent to the whole cleaning agent is set to be preferably 1 - 10,000 ppm, and more preferably 10 - 1,000 ppm. When this concentration is too low, a sufficient chelating effect cannot be obtained. On the other hand, if the concentration is excessively high, organic materials may remain on the substrate surface, which causes deterioration of the performance of the semiconductor element or increase in the cost required for the treatment of the waste fluid.
The cleaning agent as used in the present example may contain an anionbased or a cation-based surfactant.
6 Examples of an anion-based surfactant include carboxylic acid type ones, sulfuric acid type ones and sulfuric ester type ones, in other words, acids having a -COON group, a -SO3H group and a -OSO3H group and their salts.
If a salt is to be employed, ammonium salt or primary, secondary or tertiary amine salt having a little adverse effect on the quality of the semiconductor device that is the very object for the cleaning is preferable. As specific examples of an anion-based surfactant, there can be given, for example, C2H25O(CH2CH2O)2SO3H, C,Hl,PhO 16 (CH2CH2O)4SO3H, Cl2H25O(CH2CH2O)4SO3H, (Ph is a phenylene group) and their ammonium salts as well as their primary, secondary and tertiary amine salts. Among the above surfactants, ammonium salts of sulfuric ester and their -primary, secondary and tertiary amine salts, which have the particularly strong removing effect on metal contaminations adhered to the surface in the metal region, are preferable. As examples of a cation-based surfactant, there can be given CBH,N (CH3) 3 Br, C2H2sN (C2Hs) (CH3) 2 Br and the like.
The amount of the anion based or the cation-based surfactant to be used is appropriately determined, according to the type of the surfactant, but is set to be preferably 1 - 1,000 ppm, and more preferably 10 - 500 ppm, by weight, with respect to the cleaning agent for the substrate. When the added amount is too small, a sufficient cleaning effect may not be obtained. On the other hand, with an excessively large amount, the treatment of the waste fluid may become difficult.
In the present example, for an anticorrosive, there can be 0 used benzotriazole (referred to as BTA, hereinafter), its derivatives, uric acid, its derivatives or such. Through the use of any of these anticorrosives, excellent anticorrosive effect on the metal such as copper can be obtained.
As a benzotriazole derivative, any of IRGAMET Series placed on the market by Ciba Speciality Chemicals, and more specifically IRGAMET 42 is preferably used.
IRGAMET 42 is 2, 2-[ [ (methyl-lH-benzotriazole-1-yl) methyl] imino] bigethanol.
Examples of a uric acid derivative include: Purina; derivatives of purine such as 6-aminopurine, 2-amino-6 oxopurine, 6-furfurylaminopurine, 2,6(1H,3H) purinedione, 2-amino-6-hydroxy-8-mercaptopurine, allopurinol, uric acid, kinetin, zeatin, guanine, xanthine, hypoxanthine, adenine, theophylline, caffeine and theobromine; 8-azaguanine; derivatives of 8 azaguanine; pteridine; derivatives of pteridine such as 2-amino-4,6-dihydroxypteridine, 2-amino-4,7- dihydroxypteridine and 2-amino-4,6,7- trihydroxypteridine; pterin; derivatives of pterin; cyanuric acid; derivatives of cyanuric acid such as triscarboxymethylcyanuric acid and triscarboxyethylcyanuric acid; isocyanuric acid; derivatives of isocyanuric acid such as triscarboxymethylisocyanuric acid and triscarboxyethylisocyanuric acid; hydantoin; derivatives of hydantoin such as dimethylhydantoin; allantoin (5- ureidobydantoin); derivatives of allantoin; barbituric acid; derivatives of barbituric acid; nicotinic acid; and derivatives of nicotinic acid such as isonicotinic acid and citrazinic acid. Each of these substances can be used independently, or two or more of them can be used together.
Among these substances described above, purine, derivatives of purine, cyanuric acid, derivatives of cyanuric acid, isocyanuric acid, derivatives of isocyanuric acid, nicotinic acid, and derivatives of nicotinic acid are preferably used, because they demonstrate excellent anticorrosive effect on the metal such as copper.
An anticorrosive is preferably used as an aqueous solution, and, thereat, the minimum amount of the anticorrosive to be mixed into the aqueous solution is set to be preferably 0.0001 wt. % and, more preferably 0.001 wt. %. With such an amount mixed, the protection against corrosion can be made substantial. The maximum amount of the anticorrosive mixed thereinto is not particularly limited and set appropriately, depending on its solubility in the aqueous solution. The maximum amount to be mixed for BTA and its derivatives is set to be preferably 1 wt. or so, and the maximum amount for uric acid derivatives is set to be, for example, 20 wt. % or so, and preferably 10 wt. or so. Hereat, an inhibitor for precipitation of the anticorrosive, made of an amine compound or such, may be added to the 16 anticorrosive, as the occasion may demand.
After the step of an anticorrosive treatment, the step of a heating treatment wherein the anticorrosive adhered onte-the surface of the copper-containing film is detached by a heating treatment is carried out and, then, the step of a nitriding treatment follows. Further, it is preferable that the step of the afore-mentioned heating treatment is carried out in a vacuum and, thereafter, keeping the vacuum as it is, the step of the nitriding treatment is performed. Since this arrangement enables the nitriding treatment to be applied to the copper surface which is in a clean state, the film thickness and the quality for the copper nitride layer and the copper silicide layer can be made uniform, and thus, the interconnection lifetime can be lengthened, while lowering the interconnection contact resistance.
Next, referring to the drawings, one example of a method of manufacturing a semiconductor device is described below.
Firstly, as shown in Fig. l(a), on a silicon wafer, an insulating film 10 and an interlayer insulating film 12 are formed in this order and, then, a plurality of interconnection trenches patterned into a prescribed shape are formed by dry etching. For the material of the interlayer insulating film 12, in addition to silicon oxide, low-dielectric-constant materials, for example, polyorganosiloxanes such as MSQ (methylsilsesquioxane) and MHSQ (methylated hydrogen silsesquioxane) and aromatic organic materials such as polyallyl ether (PAR) and divinylsiloxane-bis- benzocyclobutane (BCB) can be utilized.
Next, after a barrier metal film 14 is grown over the entire surface by the sputtering method, a seed copper film 15 is formed by the sputtering method and then a copper film 16 is formed by the plating method.
For the material of the barrier metal film 14, metal materials such as Ta, TaN, W. WN, Ti and TiN can be used.
In the present embodiment, copper is employed as the interconnection material, although a copper alloy may be also used.
Subsequently, the wafer surface is polished by the CMP method so that a copper interconnection, as shown in Fig. l(b), may be formed. Hereat, by the effect of an oxidizing agent contained in a CMO slurry, the surface of the copper interconnection 17 may be oxidized to form copper oxide 21. Accordingly, a cleaning to remove this copper oxide 21 is carried out. For the cleaning agent, a solution containing carboxylic acid such as oxalic acid, maleic acid, succinic acid or acetic acid is preferably used.
16 After the cleaning, with carbon oxide removed, a clean surface of the copper interconnection 17 is exposed (Fig. l(c)). Next, a treatment with an anticorrosive is performed so as to adhere the anticorrosive 22 onto the surface of the copper interconnection 17 (Fig. 2(a)). As examples of the anticorrosive 22, as described above, there can be given BTA and its derivatives, and uric acid and its derivatives. By making the anticorrosive 22 adhered thereto, copper can be well protected from oxidation, even if the wafer is exposed to the air or left in the air for several days.
Next, by heating the wafer, the anticorrosive 22 is vapourized (Fig. 2(b)) . For example, when BTA is utilized as the anticorrosive, BTA can be removed almost completely by a heating treatment at a temperature equal to or higher than 200 C. This heating treatment for detachment of the anticorrosive is conducted preferably at a temperature of 200-500 C, and more preferably at a temperature of 300-450 C. Such a treatment can effectively detach the anticorrosive therefrom without affecting the elements therein adversely.
At this stage, the surface of the copper interconnection 17 is made to be, in the absence of copper oxide and anticorrosive, in a clean state. In such a state, the copper surface is subjected to a nitriding treatment. In the present example, a plasma treatment is performed, using a source gas containing nitrogen and ammonia. With this plasma treatment, a copper nitride layer 24 is formed on the surface of the copper interconnection 17 (Fig. 2(c)). An example of conditions for the plasma treatment is shown below.
Ammonia flow rate 50 - 5,000 scam Nitrogen flow rate 0 - 5,000 scam (A flow rate ratio of ammonia to nitrogen is preferably set to be 0.01 1.0.) Pressure 1 - 10 Torr High-frequency power 100 - 1,000 W. preferably - 500 W Substrate temperature 300 - 450 C, preferably 350 - 400 C Treatment time period 1 sec - 10 min In this plasma treatment, it is preferable to use a source gas comprising a nitrogen element and more preferable to use the gas further comprising a hydrogen element to provide a reducing nature. In this way, a copper nitride layer of high quality can be formed without damaging the surface of the copper- containing film. For a source gas, a mixed gas of nitrogen and hydrogen, a mixed gas of ammonia and nitrogen and mixed gases in which other components are appropriately added into either of these above mixed gases can be preferably used. Among these, a mixed gas of ammonia and nitrogen is particularly preferable, because, with this, a copper nitride layer of high quality can be formed well under control. Hereat, a ratio of the amount (volume ratio) of ammonia to the whole mixed gas is set to be preferably 1 - 50 %. This setting can prevent the degradation of the copper surface and, at the same time, facilitate to form a copper nitride layer of high quality.
Next, on the copper interconnection 17, a silicon nitride film 18 is formed as a copper-diffusion prevention film. The silicon nitride film 18 can be formed by the plasma CVD (Chemical Vapour Deposition) method. The conditions of the film growth can be set, for instance, as follows.
SiH4 flow rate 50 - 2,000 scam, preferable 50 - 300 scam Ammonia flow rate 10 - 2,000 sccm (A flow rate ratio of ammonia to nitrogen is preferably set to be 0.01 - 0.7.) Pressure 1 - 10 Torr High-frequency power 100 1,000 W. preferably 100 _ 500 W Substrate temperature 300 - 450 C, preferably 350 400 C In this step of film growth, silicon is diffused, through the copper nitride layer 24, into the copper interconnection 17, to form a copper silicide layer 25 (Fig. 3(a)). Hereat, the presence of the copper nitride layer 24 can suppress diffusion of silicon from thesilicon nitride film 18 into the copper interconnection 17 and, therefore, the film thickness of the copper silicide layer becomes less, compared with the case the copper nitride layer 24 is not provided. Further, because the plasma treatment is carried out, as described above, in a state where copper oxide on the surface of the copper interconnection 17 is removed, the copper nitride layer 24 can be formed homogeneously to an uniform thickness. Therefore, it is possible to suppress the increases in interconnection resistance and contact resistance and, at the same time, achieve an improvement of the interconnection lifetime.
Hereat, both of the plasma treatment and the film growth described above are carried out, using a parallel plate type plasma generation equipment. Within this plasma generation equipment, the steps from the step of a heating treatment to make the anticorrosive detached to the step of formation of a silicon nitride film are performed. Since the vacuum state is maintained throughout these steps, the oxidation of the copper surface can be prevented from occurring and the nitriding treatment can be conducted, while the clean surface thereof is maintained.
Next, after an interlayer insulating film 19 is formed from silicon oxide (Fig. 3(b)), a via hole is formed by dry etching. Firstly, as shown in Fig. 4(a), an interlayer insulating film 19 is etched and then, as -^ shown in Fig. 4(b), a silicon nitride film 18 is etched to expose the copper interconnection 17 at the bottom section of the hole. Hereat, in order to expose the copper interconnection 17 for sure, a certain overetching is, in general, required. In the present example, because the copper nitride layer 24 is homogeneously formed to a uniform thickness as described above, the silicon nitride film 18 can be also formed to a uniform thickness well under control. The overetching time period can be, therefore, held down to the minimum.
After that, by filling up the inside of the via hole with metal such as copper or tungsten, an interlayer connecting plug 27 is formed, and, thus, forming a multi-layered interconnection structure (Fig. 4(c)).
The above description is made for an example of a
method employing a series of steps wherein, after forming a copper interconnection 17, copper oxide is removed by a cleaning agent, and, then, after an anticorrosive treatment is conducted, a nitriding treatment is carried out. It is, however, possible not to include the step of a cleaning or an anticorrosive treatment in a manufacturing method.
Thus, in a preferred embodiment of the invention, after growing a coppercontaining film, the surface of the copper-containing fir-m is subjected to a nitriding treatment without being exposed to an oxygen-containing atmosphere. For instance, there can be employed a manufacturing method in which, after a copper film is grown and then patterned by means of etching or the like, it is subjected to a nitriding treatment, while keeping as it is, even without taking out from a plasma chamber. This makes the nitriding treatment applied to the surface in a state where no copper oxide is substantially formed so that a copper silicide layer can be formed homogeneously to a thin uniform thickness, allowing to achieve both a lowering of the electrical resistance and an improvement of the interconnection lifetime, at the same time.
Example 1
Using a method of manufacturing a semiconductor device as described above, copper interconnections were formed and their interconnection lifetimes and resistances were evaluated. The method of fabricating the copper interconnection is described below. First, by the plasma CVD method, a silicon oxide film was formed on a silicon wafer. Next, by dry etching, a plurality of interconnection trenches patterned into a prescribed shape were formed. Next, after a barrier metal film was formed from Ta by the sputtering method, a seed copper film and a plating copper film were formed in this order.
Subsequently, the wafer surface was polished by the CMP method so as to leave copper inside of the interconnection trenches, and thereby a copper interconnection was formed. Next, for the purpose of removing polishing grains, particles such as polishing shavings, metals and slurries, which were adhered onto the surface of the semiconductor wafer, the following steps of cleaning were performed.
First, a scrub cleaning was made. That is, particle contaminations were removed by moving a rotating brush, while spraying a cleaning agent made of electrolytic ionized water onto the brush. Next, a spin cleaning was made. In this step, while rotating the semiconductor wafer, a cleaning agent made of an aqueous solution containing 0.03 wt. % of oxalic acid was sprayed thereto for 10 seconds to remove copper oxide and then rinsing with pure water was carried out.
Next, an anticorrosive treatment was made. The agent for the anticorrosive treatment used herein had the following components.
Benzotriazole 0.1 wt. % Water the rest While rotating the semiconductor wafer, this agent for the anticorrosive treatment was sprayed onto the wafer surface with a flow rate of 1 litre / min for 10 seconds, and thereby an anticorrosive treatment was applied onto a Cu film. After that, the step of spin rinsing/drying, wherein after rinsing with pure water was conducted for 15 seconds, drying was made, was performed.
Subsequently, a plasma treatment was carried out, using a mixed gas of ammonia and nitrogen, and the surface of the copper interconnection was nitrided.
After that, using a source gas made of SiH4, ammonia and nitrogen, a silicon nitride film was formed, by the plasma CVD method, to a thickness of 50 nm on the copper interconnection. After that, an interlayer insulating film was formed thereon, and a plug to bring into contact with the copper interconnection was set, whereby a copper interconnection for the evaluation was accomplished.
Case 1 for Comparison Copper interconnections were formed in the same way as Example 1 except that, after the oxalic acid treatment, not a BTA treatment but only an ammonia plasma treatment was performed and thereafter a silicon nitride film was formed.
Case 2 for Comparison Copper interconnections were formed in the same way as Example 1 except that, after the oxalic acid treatment, not an ammonia plasma treatment but only a BTA treatment was performed and thereafter a silicon nitride film was formed.
The copper interconnections fabricated as described in Example l and Cases 1 and 2 for Comparison have planar structures shown in Fig. 6 (a) and (b). The interconnection resistances and the interconnection life times for these copper interconnections were evaluated.
With respect to the interconnection resistance, the evaluation was made through the value of resistance (El/Il) which was obtained by making an electric current (I1) flow between terminals for measurement P3 -P4 of Fig. 6 (a), while increasing from O A to 1 mA, and measuring the potential difference (E1) generated thereat between both ends PI - P2 of the measuring element. Regarding the interconnection lifetime, the evaluation was made through the measurement of the time period for the deviation of the value of resistance (E2/I2) to reach 3 %, owing to the degradation, when a given current (I2) in the range of 0.01 mA - lOmA was kept to flow between terminals for the measurement P5 - P6 of Fig. 6(b) in a given atmosphere (at a given temperature and such) and the potential difference (E2) generated between P7 - P8 was measured.
The results are shown in Fig. 7 and Fig. 8. In both of these graphs, the value of Example 1 is taken as 1, and the values of Cases for Comparison are expressed in reduced values, respectively. For the interconnection resistance in Fig. 7, the lower its value is, the better it is. For the interconnection lifetime in Fig. 8, the higher its value is, the better it is. Case 1 for Comparison has excellent interconnection resistances but their variations among elements are considerable and besides the interconnection lifetimes are short. Meanwhile, Case 2 for Comparison has the long interconnection lifetimes but large interconnection resistances with substantial variations. As against these, it is clearly demonstrated that the interconnections of Example 1 have both excellent interconnection lifetimes and interconnection resistances and besides variations in interconnection resistances among elements are small.
Case 1 for Reference On a silicon wafer, a silicon oxide film is formed and thereon a copper plating film is formed over the entire surface. Following that, after the copper surface was polished by the CMP method, for the purpose of removing polishing grains, particles such as polishing shavings, metals and slurries, the following steps of cleaning were performed.
First, a scrub cleaning was made. That is, particle contaminations were removed by moving a rotating brush, while spraying a cleaning agent made of electrolytic ionized water onto the brush. Next, a spin cleaning was made. In this step, while rotating the semiconductor wafer, a cleaning agent made of an aqueous solution containing 0.03 wt. % of oxalic acid was sprayed thereto for 10 seconds to remove metal contaminations which are CuO lying on the surface, and then rinsing with pure water was carried out.
Next, an anticorrosive treatment was made. The agent for the anticorrosive treatment used herein had the following components.
Benzotriazole 0.1 wt. % Water the rest While rotating the semiconductor wafer, this agent for the anticorrosive treatment was sprayed onto the wafer surface with a flow rate of 1 litre / min for 10 seconds, and thereby an anticorrosive treatment was applied onto a Cu film. The wafer in this state is designated as Sample 1.
Sample 1 is further subjected to a plasma treatment under the following conditions and, with the surface of the copper film therein being nitrided, is designated as Sample 2.
Flow gas Ammonia and nitrogen The total flow rate 5,000 scam Flow rate ratio of ammonia to nitrogen is 1 to 50.
Pressure 5 Torr High-frequency power 200 W Substrate temperature 400 Treatment time period seconds in a state without applying high frequency power, and 5 seconds in a state with applying high-frequency power Sample 1 and Sample 2 obtained as described above are each subjected to a treatment for the initial stage of the steps of forming a silicon nitride film by the plasma CVD method. That is, SiH4 was added to the above flow gas in the atmosphere at 400 C and held for 5 seconds. The pressure was set to be 5 Torr and the high-frequency power, 200 W. The occupation ratios of silicide formed on the surface of the copper film after the above treatment was completed were observed for respective samples. The observation was made by applying wet etching with a mixed solution of ammonia and hydrogen peroxide to the copper films after the above treatment. While copper and copper oxide are soluble in the above mixed solution, copper silicide is insoluble. Therefore, the insoluble portion signifies copper silicide. When elementary analysis of the insoluble portion was conducted by the SIMS (Secondary Ion Mass Spectroscopy), copper and silicon were actually detected. On the basis of results from such observations, an occupation ratio of the copper silicide area that is insoluble in etching with respect to the whole area of the copper film that has been originally present is defined as a silicide occupation ratio. The results of the experiments are shown in Fig. 9. It is evident that the formation of silicide was well suppressed in Sample 2 whose copper surface was nitrided with the ammonia plasma treatment.
These results of the experiments confirm that nitridation of the copper surface suppresses copper silicide formation.
The example described above thus illustrates the provision of a method of manufacturing a semiconductor device which can improve the interconnection lifetime and the variation in resistance of the copper interconnection, while controlling the increase in resistance thereof, and, in addition, can raise the manufacturing stability.

Claims (4)

  1. Claims 1. A method of manufacturing a semiconductor device, the method
    comprising the steps of: forming a copper-containing film on a semiconductor substrate; applying a nitriding treatment to the surface of the copper-containing film without allowing the semiconductor substrate to be exposed to an oxygen-containing atmosphere; forming a copper- diffusion prevention film comprising a silicon on the copper containing film which has been subjected to the nitriding treatment.
  2. 2. A method of manufacturing a semiconductor device according to claim 1, wherein the nitriding step treatment applied to the surface of the copper containing film is effected by a plasma treatment with a source gas comprising a nitrogen element.
  3. 3. A method of manufacturing a semiconductor device substantially as herein described with reference to Figures 1 to 4 of the drawings.
  4. 4. A semiconductor device having a connection portion thereon, the connection portion being made of copper or copper alloy which contains at least 80 weight percent of copper, the semiconductor device being made using a method in accordance with any of the preceding claims.
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Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6136680A (en) * 2000-01-21 2000-10-24 Taiwan Semiconductor Manufacturing Company Methods to improve copper-fluorinated silica glass interconnects

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6136680A (en) * 2000-01-21 2000-10-24 Taiwan Semiconductor Manufacturing Company Methods to improve copper-fluorinated silica glass interconnects

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
Noguchi et al, "TDDB Improvement in Cu Metallization under Bias Stress", IEEE 38th Annual International Reliability Physics Symposium, San Jose, California, 2000, pages 339-343. *

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