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GB2399222A - Semiconductor device comprising a thin oxide liner and method of manufacturing the same - Google Patents

Semiconductor device comprising a thin oxide liner and method of manufacturing the same Download PDF

Info

Publication number
GB2399222A
GB2399222A GB0412884A GB0412884A GB2399222A GB 2399222 A GB2399222 A GB 2399222A GB 0412884 A GB0412884 A GB 0412884A GB 0412884 A GB0412884 A GB 0412884A GB 2399222 A GB2399222 A GB 2399222A
Authority
GB
United Kingdom
Prior art keywords
oxide liner
semiconductor device
substrate
liner
manufacturing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
GB0412884A
Other versions
GB0412884D0 (en
GB2399222B (en
Inventor
Scott Luning
Daniel Kadosh
Jon D Cheek
James F Buller
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Advanced Micro Devices Inc
Original Assignee
Advanced Micro Devices Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advanced Micro Devices Inc filed Critical Advanced Micro Devices Inc
Publication of GB0412884D0 publication Critical patent/GB0412884D0/en
Publication of GB2399222A publication Critical patent/GB2399222A/en
Application granted granted Critical
Publication of GB2399222B publication Critical patent/GB2399222B/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
    • H01L21/26513—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors of electrically active species
    • H01L21/2652—Through-implantation
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/0223—Manufacture or treatment of FETs having insulated gates [IGFET] having source and drain regions or source and drain extensions self-aligned to sides of the gate
    • H10D30/0227—Manufacture or treatment of FETs having insulated gates [IGFET] having source and drain regions or source and drain extensions self-aligned to sides of the gate having both lightly-doped source and drain extensions and source and drain regions self-aligned to the sides of the gate, e.g. lightly-doped drain [LDD] MOSFET or double-diffused drain [DDD] MOSFET

Landscapes

  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • High Energy & Nuclear Physics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Toxicology (AREA)
  • Health & Medical Sciences (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Formation Of Insulating Films (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

A method of forming a semiconductor device provides a gate electrode (32) on a substrate (30); and an oxide liner (34) that is less than 100 A in thickness on the substrate (30) and the gate electrode (32). A nitride layer (38) is formed on the oxide liner (34). The nitride layer (38) is etched to form nitride spacers (40), the etching stopping on the oxide liner (34). The thinner oxide liner (34), e.g., less than 100 A, prevents the liner (34) from acting as a sink for dopants during thermal processing so that the dopants in the source/drain extension regions (36) and the source/drain regions (42) remain in the substrate (30) during the thermal processing, thereby preventing degradation of transistor performance.

Description

GB 2399222 A continuation (72) Inventor(s): Scott Luning Daniel Kadosh Jon
D Cheek James F Buller (74) Agent and/or Address for Service: Brookes Batchellor LLP 102-108 Clerkenwell Road, LONDON, EC1M USA, United Kingdom
GB0412884A 2001-12-19 2002-12-19 Semiconductor device comprising a thin oxide liner and method of manufacturing the same Expired - Lifetime GB2399222B (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US2103701A 2001-12-19 2001-12-19
PCT/US2002/041103 WO2003054951A1 (en) 2001-12-19 2002-12-19 Semiconductor device comprising a thin oxide liner and method of manufacturing the same

Publications (3)

Publication Number Publication Date
GB0412884D0 GB0412884D0 (en) 2004-07-14
GB2399222A true GB2399222A (en) 2004-09-08
GB2399222B GB2399222B (en) 2005-07-20

Family

ID=21801954

Family Applications (1)

Application Number Title Priority Date Filing Date
GB0412884A Expired - Lifetime GB2399222B (en) 2001-12-19 2002-12-19 Semiconductor device comprising a thin oxide liner and method of manufacturing the same

Country Status (7)

Country Link
JP (1) JP2005517285A (en)
KR (1) KR20040068269A (en)
CN (1) CN1322565C (en)
AU (1) AU2002358269A1 (en)
DE (1) DE10297582T5 (en)
GB (1) GB2399222B (en)
WO (1) WO2003054951A1 (en)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6583016B1 (en) * 2002-03-26 2003-06-24 Advanced Micro Devices, Inc. Doped spacer liner for improved transistor performance
JP2008124441A (en) * 2006-10-19 2008-05-29 Tokyo Electron Ltd Manufacturing method of semiconductor device
DE102011005641B4 (en) * 2011-03-16 2018-01-04 GLOBALFOUNDRIES Dresden Module One Ltd. Liability Company & Co. KG A method of increasing performance in transistors by reducing subsidence of active regions and by removing spacers

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4868617A (en) * 1988-04-25 1989-09-19 Elite Semiconductor & Sytems International, Inc. Gate controllable lightly doped drain mosfet devices
US5714413A (en) * 1995-12-11 1998-02-03 Intel Corporation Method of making a transistor having a deposited dual-layer spacer structure
US6156598A (en) * 1999-12-13 2000-12-05 Chartered Semiconductor Manufacturing Ltd. Method for forming a lightly doped source and drain structure using an L-shaped spacer
US6251764B1 (en) * 1999-11-15 2001-06-26 Chartered Semiconductor Manufacturing Ltd. Method to form an L-shaped silicon nitride sidewall spacer
US6277700B1 (en) * 2000-01-11 2001-08-21 Chartered Semiconductor Manufacturing Ltd. High selective nitride spacer etch with high ratio of spacer width to deposited nitride thickness
US6294480B1 (en) * 1999-11-19 2001-09-25 Chartered Semiconductor Manufacturing Ltd. Method for forming an L-shaped spacer with a disposable organic top coating

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6472281B2 (en) * 1998-02-03 2002-10-29 Matsushita Electronics Corporation Method for fabricating semiconductor device using a CVD insulator film
US6162692A (en) * 1998-06-26 2000-12-19 Advanced Micro Devices, Inc. Integration of a diffusion barrier layer and a counter dopant region to maintain the dopant level within the junctions of a transistor

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4868617A (en) * 1988-04-25 1989-09-19 Elite Semiconductor & Sytems International, Inc. Gate controllable lightly doped drain mosfet devices
US5714413A (en) * 1995-12-11 1998-02-03 Intel Corporation Method of making a transistor having a deposited dual-layer spacer structure
US6251764B1 (en) * 1999-11-15 2001-06-26 Chartered Semiconductor Manufacturing Ltd. Method to form an L-shaped silicon nitride sidewall spacer
US6294480B1 (en) * 1999-11-19 2001-09-25 Chartered Semiconductor Manufacturing Ltd. Method for forming an L-shaped spacer with a disposable organic top coating
US6156598A (en) * 1999-12-13 2000-12-05 Chartered Semiconductor Manufacturing Ltd. Method for forming a lightly doped source and drain structure using an L-shaped spacer
US6277700B1 (en) * 2000-01-11 2001-08-21 Chartered Semiconductor Manufacturing Ltd. High selective nitride spacer etch with high ratio of spacer width to deposited nitride thickness

Also Published As

Publication number Publication date
CN1606801A (en) 2005-04-13
CN1322565C (en) 2007-06-20
WO2003054951A1 (en) 2003-07-03
GB0412884D0 (en) 2004-07-14
AU2002358269A1 (en) 2003-07-09
JP2005517285A (en) 2005-06-09
KR20040068269A (en) 2004-07-30
DE10297582T5 (en) 2004-11-11
GB2399222B (en) 2005-07-20

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