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GB2376821B - Delayed locked loop clock generator using delay-pulse-delay - Google Patents

Delayed locked loop clock generator using delay-pulse-delay

Info

Publication number
GB2376821B
GB2376821B GB0221291A GB0221291A GB2376821B GB 2376821 B GB2376821 B GB 2376821B GB 0221291 A GB0221291 A GB 0221291A GB 0221291 A GB0221291 A GB 0221291A GB 2376821 B GB2376821 B GB 2376821B
Authority
GB
United Kingdom
Prior art keywords
delay
pulse
locked loop
clock generator
loop clock
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
GB0221291A
Other versions
GB2376821A (en
GB0221291D0 (en
Inventor
Seong-Hoon Lee
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
SK Hynix Inc
Original Assignee
Hyundai Electronics Industries Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from KR1019980061113A external-priority patent/KR100303777B1/en
Application filed by Hyundai Electronics Industries Co Ltd filed Critical Hyundai Electronics Industries Co Ltd
Publication of GB0221291D0 publication Critical patent/GB0221291D0/en
Publication of GB2376821A publication Critical patent/GB2376821A/en
Application granted granted Critical
Publication of GB2376821B publication Critical patent/GB2376821B/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 
    • G11C7/222—Clock generating, synchronizing or distributing circuits within memory device
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
    • H03K5/135—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals by the use of time reference signals, e.g. clock signals
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/081—Details of the phase-locked loop provided with an additional controlled phase shifter
    • H03L7/0812—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used
    • H03L7/0814—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used the phase shifting device being digitally controlled

Landscapes

  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Dram (AREA)
GB0221291A 1998-12-30 1999-12-30 Delayed locked loop clock generator using delay-pulse-delay Expired - Fee Related GB2376821B (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
KR1019980061113A KR100303777B1 (en) 1998-12-30 1998-12-30 Delay-Locked Loop Clock Generator with Delay-Pulse-Delay
GB9930812A GB2345395B (en) 1998-12-30 1999-12-30 Delayed locked loop clock generator using delay-pulse-delay conversion

Publications (3)

Publication Number Publication Date
GB0221291D0 GB0221291D0 (en) 2002-10-23
GB2376821A GB2376821A (en) 2002-12-24
GB2376821B true GB2376821B (en) 2003-04-09

Family

ID=26316155

Family Applications (1)

Application Number Title Priority Date Filing Date
GB0221291A Expired - Fee Related GB2376821B (en) 1998-12-30 1999-12-30 Delayed locked loop clock generator using delay-pulse-delay

Country Status (1)

Country Link
GB (1) GB2376821B (en)

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0655840A2 (en) * 1993-11-30 1995-05-31 AT&T Corp. Delay locked loop based clock synthesizer using a dynamically adjustable number of delay elements therein
EP0762262A1 (en) * 1995-09-06 1997-03-12 Mitsubishi Denki Kabushiki Kaisha Clock generating circuit, PLL circuit
US5684421A (en) * 1995-10-13 1997-11-04 Credence Systems Corporation Compensated delay locked loop timing vernier
US6191627B1 (en) * 1998-09-30 2001-02-20 Siemens Aktiengesellschaft Integrated circuit having adjustable delay units for clock signals

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0655840A2 (en) * 1993-11-30 1995-05-31 AT&T Corp. Delay locked loop based clock synthesizer using a dynamically adjustable number of delay elements therein
EP0762262A1 (en) * 1995-09-06 1997-03-12 Mitsubishi Denki Kabushiki Kaisha Clock generating circuit, PLL circuit
US5684421A (en) * 1995-10-13 1997-11-04 Credence Systems Corporation Compensated delay locked loop timing vernier
US6191627B1 (en) * 1998-09-30 2001-02-20 Siemens Aktiengesellschaft Integrated circuit having adjustable delay units for clock signals

Also Published As

Publication number Publication date
GB2376821A (en) 2002-12-24
GB0221291D0 (en) 2002-10-23

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Legal Events

Date Code Title Description
PCNP Patent ceased through non-payment of renewal fee

Effective date: 20161230