GB2369909A - Faulty cell repairing method for a semiconductor memory - Google Patents

Abstract

A faulty cell repairing method for a semiconductor memory having a plurality of normal columns and at least one redundant column, and data input and output lines corresponding to the columns, comprises the steps of: <SL> <LI>a) detecting the number i of a column having faulty cells, by counting columns with reference to the redundant column, <LI>b) detecting the number k of a column which will perform the operation of reading or writing of data, by counting columns with reference to the redundant column, <LI>c) determining whether k is larger than i, <LI>d) connecting a data transfer line IOk to a normal data input and an output line NIOk when the result of the step c) is "yes", and <LI>e) when the result of step c) is "no", carrying out the steps of:<BR> e1) determining whether the data transfer Line IOk is the first normal column starting from the redundant column when the result of step c) is "no",<BR> e2) connecting the data transfer line IOk to a redundant data input and output line RIO when the result of the step e1) is "yes", and<BR> e3) connecting the data transfer Line IOk to a data input and output line NIOk-1 when the result of the step e1) is "no". </SL>

Description

A SEMICONDUCTOR MEMORY DEVICE The present invention relates to a semiconductor memory device, and more particularly, to a semiconductor memory device having data input and output lines in a column direction and a circuit for repairing faulty cells using the memory device and a method therefor.

In general, a semiconductor memory device has a plurality of memory cells. A specific memory cell is selected by a row address and a column address. The data of the selected memory cell moves to local input and output lines through a pair of bit lines. When many memory cells are connected to a pair of bit lines, a parasitic capacitance increases. Accordingly, the memory operates more slowly, due to the large parasitic capacitance, as the number of memory cells connected to a pair of bit lines increases. Also, when all the cells of the semiconductor memory device are in one block, multi-bit input and output cannot be performed. Therefore, the semiconductor memory device is divided into multiple banks. Each bank can independently input and output data. Such a structure is called a stack bank architecture.

FIG. 1 is a block diagram showing the input and output lines of a semiconductor memory device having a conventional stack bank structure. Referring to FIG. 1, in the memory device having the stack bank structure, a bank constituted by the memory cells has a structure like that of stacked bricks. Each bank has a row decoder, a sense amplifier, and a local column decoder. Global input and output lines GIO use a common data bus. The row decoder is selected by a row bank address and is activated by selecting the word line of the memory cell. The word line of the memory cell is arranged in a row direction. The local column decoder is operated by the output

sins. iS 0. 1. 3. cOimn t's. rL 3. \ress n. s. i0ti coimnn. ecoer. iere is one i0cs. i coinm I I ii-I !,--I u I I u I I. L k I I I

decoder in every bank. The output signal lines of the global column decoder GSCL and the output signal of the local column decoder LSCLi are all arranged in a column direction. When the word line is selected by the row bank address and the row address, all the sense amplifiers of the selected banks operate. The data of the selected bank is amplified by the sense amplifier and

I--3 to lmoves to the local input and output lines (not shown) in the row direction. The data moved to the LIO again moves to the global input and output lines GIO. The global input and output lines GIO are commonly connected to the memory banks and are arranged in the column direction.

FIG. 2 is a block diagram showing the faulty cell repairing circuit applied in the semiconductor memory device of FIG. 1. In the faulty cell repairing circuit of FIG. 2, a normal switch is arranged between the data line DIOi of the memory cell and a local input and output line LIOi. A redundancy switch is arranged between redundancy input and output line RIO and the local input and output line LIOi. All the normal switches are turned on in a normal operating mode. At this time, the redundancy switches are all turned off. Therefore, the data lines DIOi are respectively connected to the local input and output lines LIOi. For example, data can be input and output since DIOO is connected to LIOO, DIO 1 to LIO 1, and Don-1 to LIOn However, when a cell is faulty, the normal switch of the related column is turned off and the redundancy switch is turned on. For example, when a faulty cell is generated in the column corresponding to the data line DIO 1, a normal switch 205 connected to the data line DIO 1 is turned off and a redundancy switch 207 is turned on. Therefore, the local input and output line LIO 1 is disconnected from the data line DIO 1 and connected to the redundancy input and output line RIO. The remaining data lines are connected to the respective local input and output lines and operate like in the normal operating mode.

The semiconductor memory device or the faulty cell repairing circuit having the stack bank structure according to a conventional technology has some problems. Firstly, in the semiconductor memory device having the conventional stack bank structure, layout area increases when the input and output lines increase. Many memory cell banks are arranged in a

memory block and the local input and output lines LIO are assigned to each bank. A local column decoder exists in each bank. In the case of increasing the input and output lines, the memory cell banks must be divided more or the number of local input and output lines output through the sense amplifier must increase. Also, the number of global input and output lines to which the respective local input and output lines are connected increases. Therefore, the input and output lines increase in the row and column directions of a memory chip. Secondly, the semiconductor memory device having the conventional stack bank structure draws a large current. Since the local column decoder of each bank must operate in a reading or writing mode, the current increases. Thirdly, a load difference is generated according to the different distances between the global input and output lines and the respective points of the local input and output lines. Accordingly, a difference in times spent outputting data from the respective columns to the global input and output lines is generated, thus deteriorating the performance of the memory.

In the faulty cell repairing circuit of FIG. 2, a plurality of redundancy switches are connected to the redundancy input and output line RIO. Therefore, the data is input and output slower during the redundancy operation.

According to a first aspect of the present invention, there is provided a faulty cell repairing method for a semiconductor memory having a plurality of normal columns and at least one redundancy column, and data input and output lines corresponding to the columns, the

11 1, I---±----C./'iiietho comprising tuC steps of : (a) detecting the number I of a column having faulty cells, -. kCL), Lil L"I vi u uiull"l 11-IIXE,'c"ILY

by counting columns with reference to the redundancy column ; (b) detecting the number k of zn a column which will perform the operation of reading or writing of data, by counting columns I with reference to the redundancy column; (c) determining whether k is larger than i; (d) connecting a data transfer line 10k to a normal data input and output line NIOk when the

result of the step (c) is"yes" ; and, (e) when the result of the step (c) is"no", carrying out the r esul) i 1-. steps of : (el) determining whether the data transfer line 10k is the first normal column starting from the redundancy column when the result of the step (c) is"no" ; (e2) connecting the data transfer line IOk to redundancy data input and output line RIO when the result of the step (el) is"yes" ; and, (e3) connecting the data transfer line 10k to a data input and output line NIOk-1 when the result of the step (el) is"no".

Examples of the present invention will now be described in detail with reference to the accompanying drawings, in which: FIG. 1 is a block diagram showing input and output lines of a conventional semiconductor memory device having a stack bank structure; FIG. 2 is a block diagram showing a faulty cell repairing circuit applied to the semiconductor memory device shown in FIG. 1; FIG. 3 is a block diagram showing an embodiment of a semiconductor memory device including data input and output lines in a column direction according to the present invention; FIG. 4 shows a column switch 311 of FIG. 3 having data input and output lines corresponding to a normal memory cell array;

FIG. 5 shows a column switch 311 of FIG. 3 having data input and output lines corresponding to

cell array anul a a HVHaal lU'-'lHV1Y'-"-'H a, Hay auu a l,-, uuauau,", y al,", lHV1Y,", uH aHa), FIG. 6 is a block diagram showing a faulty cell repairing circuit applied to the semiconductor memory device of FIG. 3 ; FIG. 7 shows a switch 603 of the faulty cell repairing circuit of FIG. 6; and, FIG. 8 is a flowchart showing a method for repairing faulty cells using the faulty cell repairing

circuit of FIG. 6 according to an embodiment.

CIFC'Lll I r u u Ul FIG. 3 is a block diagram showing a semiconductor memory device having data input and output lines in a column direction. Referring to FIG. 3, the present invention relates to a semiconductor memory device having a memory block constituted of a plurality of memory cells arranged in a row and a column. The semiconductor memory device in the present embodiment includes a row decoder 301, a column decoder 303, and data input and output lines 10. The memory block is constituted of many memory cell banks. Each memory cell bank can independently perform READ and WRITE operations. The row decoder 301 selects a memory cell bank in response to a row address signal group RAO, RA1,..., RAn-1, selects the row and activates a word line. The column decoder 303 activates a column select line CSL in response to a column address signal group CAO, CA1,..., CAn-1. The column select line CSL selects the column of the memory block. The column select line CSL is arranged in the row direction. The column decoder 303 according to the present embodiment is arranged on one side, in the row direction, of the memory cell bank. The data input and output lines 10 input data to and output data from the memory cell selected by the column decoder 303. The data input and output lines 10 are arranged in a column direction. The data input and output lines 10 are arranged so as to cross over the memory block area. Referring to FIG. 3, the structure and reading operation of the present embodiment will be described in detail as follows. The present embodiment is constituted of 16 memory cell banks.

- 6 ! Z, Ul LIIC, UliLli,-IIICil. IUI V-, a7 The size of the entire memory is 32 : i'vfb a : d there are 64 mpt a : d output li : es. A memory cell

bank is constituted of two memory cell arrays. For example, the uppermost memory cell bank is constituted of two memory cell arrays 307~1 and 307~2. The lowermost memory cell bank is constituted of two memory cell arrays 307~31 and 30732. Each memory cell array has a memory size of 1 Mb, and one memory cell bank has a memory size of 2Mb. Each memory cell bank has a sense amplifier 309 and a column switch 311. Therefore, the row of the memory cell bank and the memory cell are selected by the address signal group RAO, RA1,..., and RAn-1, thus activating the related word line. The data of the memory cell connected to the activated word line is transmitted to the sense amplifier over the bit line. At this time, the word lines are arranged in a row direction. The bit lines are arranged in a column direction. The data of the memory cell transmitted to the sense amplifier is amplified. The column switch 311 is turned on by the activated column select line CSL. The turned on column switch electrically connects the bit line to the data input and output lines 10. Therefore, the data of the amplified memory cell moves to the data input and output lines 10 through the turned on column switch and is transferred to an external pad through an input and output interface 313. The data can be input and output when two columns are selected in one memory cell bank. Therefore, 64 units of data can be input and output from the memory chip.

FIG. 4 shows the column switch 311 of FIG. 3 having data input and output lines corresponding to a normal memory cell array. A first switch group is constituted of four transistors arranged in four columns, in each column of the memory cell bank. Namely, the first switch group is repeated on the basis of four transistors 401,403, 405, and 407 arranged in four columns. In the first switch group, one among the four transistors 401,403, 405, and 407 is turned on in response to a first output signal CSLF of the column decoder 303. The first output signal CSLF of the

column decoder 303 is decoded and activated by lower column addresses. A second switch is turned on in response to a second output signal CSLS of the column decoder 303. The signal CSLS is decoded and activated by upper column addresses. Therefore, in order to connect the bit line of the selected memory cell to the data input and output lines, the first and second switches must be turned on. Therefore, the bit line of the memory cell, i. e. , the selection of the column, is determined by the combination of the CSLF and the CSLS, and is connected to the normal data input and output lines NIOi.

FIG. 5 shows the column switch 311 of FIG. 3 having the data input and output lines corresponding to the normal memory cell array and the redundancy memory cell array. Referring to FIG. 5, the data input and output lines in the normal memory cell array are shown in FIG. 4.

However, the column switch corresponding to the redundancy memory cell array is a little different from that corresponding to the normal memory cell array. The first switch group is arranged in the same way as the first switch group corresponding to the normal memory cell array. The signal group CSLF, for controlling the first switch group is arranged in the row direction. However, while the signal group CSLS for controlling the second switch group of the normal memory cell array is arranged in the row direction, the signal group CSLS for controlling the second switch group of the redundancy memory cell array is arranged in a column direction.

As mentioned above, the layout area and the operation current can be minimized during the increase of the data input and output lines by arranging the data input and output lines and data transfer lines in a column direction. Also, there is less loading difference from the respective input and output lines to the output pad.

FIG. 6 is a block diagram showing a faulty cell repairing circuit applied to the semiconductor memory device of FIG. 3. Referring to FIG. 6, the present invention relates to the faulty cell

r epairing cir cit orthe SCllliCOlldCtOl rllelllOly device having t least tw nollllal clull, n lid L H :"paUUlt ; L-UvUlL Vl. LUe : :'CUUL-VUUUL-LVl. U1C1UVlj ue v lvC ua VUlt ; aL lea : :'L LVVV UVl. l. Ual L-V1UUlll. ;) auu aL

least one redundancy column. The semiconductor memory device according to the present invention includes first and second normal data input and output lines N100 and Nif1, a J, u A li redundancy data input and output line RIO, first and second data transfer lines SIOO and SIO I, and first and second switches 601 and 603. The first and second normal data input and output

lines N100 and N101 input and output data, corresponding to the first and second normal columns. The redundancy data input and output line RIO inputs the data to the redundancy column or outputs data from the redundancy column. The first and second data transfer lines SIOO and SIO 1 input the data to an external circuit or output the data from the external circuit. The first switch 601 connects the first normal data input and output line NIOO to the first data transfer line 100 when there are no faulty cells in the column connected to the first normal data input and output line NIOO, namely, during the normal operation. However, when there are faulty cells in the column connected to the first normal data input and output line NID0, namely, during the redundancy operation, the first switch 601 connects the redundancy data input and output line RIOO to the first data transfer line SIOO. When there are no faulty cells in the column connected to the second normal data input and output line NIO 1, namely, during the normal operation, the second switch 603 connects the second normal data input and output line Nit 1 to the second data transfer line SIO 1. When there are faulty cells in the column connected to the second normal data input and output line N100, namely, during the redundancy operation, the second switch 603 connects the first normal data input and output line NIOO to the second data transfer lines 101. Here, the reference was made with respect to the two normal columns. However, such a structure can be applied to a semiconductor memory device having a plurality of columns. When there are no faulty cells in the memory cell block, the data transfer lines are connected to the originally assigned normal data input and output lines. However, when there are

-11-le laui ce'ii the faulty'cells in the memory cell block, the data transfer lines are connected to adjacent normal

data input and output lines. For example, when there are the faulty cells in the fifth column from the right side to the left side of FIG. 6, i. e., the column corresponding to N104 on the basis of the . t h . L x I column redundant cell array, SIOO and RIO are electrically connected. SIO 1, S102, SI03 (not shown), and SI04 (not shown) are respectively connected to NID0, N101, N102, and NIO3 (not shown). The six and subsequent data transfer lines, i. e., 8105 (not shown) are connected to the originally corresponding normal data input and output lines.

FIG. 7 shows the switch 603 of the faulty cell repairing circuit of FIG. 6. Referring to FIG. 7, the switch of the present embodiment includes a first transfer gate 701 and a second transfer gate 703. The first transfer gate 701 is turned on in a normal operation state for connecting the normal data input and output line NIO1 to the data transfer line SIO I. The second transfer gate 703 connects the normal data input and output line NIOO to the data transfer line SIO 1 when there are faulty cells in NIT 1 or the successive columns, i. e. , during the redundancy operation. In the present embodiment, whether the redundancy operation is to be performed is determined by a redundancy control signal RCSLi and FUSEi generated by cutting a fuse. Namely, when RCSLi and FUSEI simultaneously become"high", the second transfer gate 703 is turned on for connecting the normal data input and output line NIOO and the data transferring line SIO 1. In the present embodiment, the reference was made with respect to the switch 603 corresponding to the data transfer line SIO 1, but the above also applies to the switches 601 and 605. However, in the switch 601, SIOO is connected to the redundancy data input and output line RIO during the redundancy operation.

FIG. 8 is a flowchart showing a method according to the invention for repairing a faulty cell

L-palillir..-, *OTT--,using the faulty cell repairing circuit ofFIC. 6. Referring to FIG. 8, the present invention relates

to a method for repairing a faulty cell of the semiconductor memory device having a plurality of normal columns and at least one redundancy column when there are faulty cells in a column. The method includes a faulty column detecting step 801, a designated column detecting step 803, a determining step 805, a normal connecting step 807, and a repairing step 809. In the faulty column detecting step 801, the number i of the column to which the faulty cells belong is detected by counting the columns by position with reference to the redundancy column. In the designated column detecting step 803, the number k of a column for performing a reading or writing operation is detected by counting the columns by position with reference to the redundancy column. In the determining step 805, it is determined whether k is larger than i by comparing i and k. In the normal connecting step 807, the data transfer line 10k is connected to the normal data input and output line NIOk when the result of the determining step 805 is"yes". In the repairing step 809, the data transfer line IOk is connected to the data input and output line of the previous column when the result of the determining step 805 is"no". The repairing step 809 includes a first column determining step 811, a first redundancy connecting step 813, and a redundancy connecting step 815. In the first column determining step 811, it is determined whether the data transfer line 10k is the first normal column starting from the redundancy column, when the result of the determining step 805 is"no". In the first redundancy connecting

step 813, the data transfer line 10k is connected to the redundancy data input and output lines RIO when the result of the first column determining step 811 is"yes". In the redundancy connecting step 815, the data transfer line 10k is connected to a normal data input and output line NIOk-1. When the faulty cells are repaired by the above method, the originally assigned normal data input and output lines are connected to the data transfer lines like in the normal state, in the columns having numbers higher than that of the column having the faulty cells. The data transfer

11-"--i -, 4 +1, - fl, t-42+,linGs c leDpollding to the colmlls having nuil. bers eXual tc and lower tha +. hat ^fthe c^lurun 11

having the faulty cells are connected to the normal data input and output lines or the redundancy data input and output lines corresponding to the columns preceding by one column. Therefore, the difference of lengths of the data paths of the respective columns during the redundancy operation are minimized.

Claims (1)

1. CLAIMS: 1. A faulty cell repairing method for a semiconductor memory having a plurality of normal columns and at least one redundancy column, and data input and output lines corresponding

   + +he I.. S +he me+h-1 mp- : : n +h +e- O. c. to the columns, the method comprising the steps of : t, () Lh Lh Lil U I I Lil L i.

   (a) detecting the number 1 of a column having faulty cells, by counting columns with reference to the redundancy column ; (b) detecting the number k of a column which will perform the operation of reading or writing of data, by counting columns with reference to the redundancy column ; (c) determining whether k is larger than i; (d) connecting a data transfer line 10k to a normal data input and output line NIOk when the result of the step (c) is"yes" ; and, (e) when the result of the step (c) is"no", carrying out the steps of : (el) determining whether the data transfer line 10k is the first normal column starting from the redundancy column when the result of the step (c) is"no" ; (e2) connecting the data transfer line IOk to redundancy data input and output line RIO when the result of the step (el) is"yes" ; and, (e3) connecting the data transfer line 10k to a data input and output line NIOk-1 when the result of the step (el) is"no".