GB2360910A - ASIC for a Family Radio Service Wireless Communication Unit - Google Patents

Abstract

An ASIC (application specific integrated circuit) for an FRS (family radio service) wireless communication unit, formed in a single chip for light weight and small volume comprises a memory for storing channel frequency allocation data, a control block for outputting a control signal based on an inner program, a display drive, a received voice output level control block, a frequency divider for frequency synchronisation, a phase detection unit, an electric charge pump, a frequency fixing detection unit for detecting whether the frequency is locked, an input clock signal buffer, a reference divider and a clock signal drive. In a second embodiment a controller comprises an audio band pass filter provided in an ASIC chip, a sub-audio low pass filter, a CTCSS (continuous tone coded squelch system) tone generation unit, a CTCSS tone detection unit, a serial interface and power on/off controller.

Description

2360910 FAMILY RADIO SERVICE CIRCUIT

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a family radio service circuit, and in particular to a family radio service circuit which is capable of decreasing a volume and size of a system by forming major circuit units using ASIC and providing various additional functions.

2. Description of the Background Art

Generally, a family radio service(FRS) is directed to a radio unit which does not need any approval from an authorization for use and which is free. The frequency of the FRS is a short wave (HF) of 27MHz and recently uses a UHF of 448MHz(Korea) or 462MHz.

The FRS which is implemented based on UHF of 448MHz or 462MHz uses a FM modulation method, a maximum output of 0.5W and 15 channels and has a communication distance of maximum 3km under a condition that there is not any obstacle.

The above-described FRS has been advanced to have various functions.

For example, in the case that a communication is frequently performed between 1 friends or others, it is not needed to pay a communication fee.

The family radio service(FRS) is classified into an European type PMR and an American type of FRS. There is a small difference therebetween in their PMR of 446MHz and electrical specs such as a communication capacity. The above- described two methods are almost similar to each other.

The conventional FRS and PMR are not widely used compared to other mobile communication terminal such as PCS, city phone or digital mobile communication terminal due to its inconvenient usage. in addition, the volume and weight of the same are large. Therefore, there are much disadvantages in the io conventional FRS and PMR- SUMMARY OF THE INVENTION

Accordingly, it is an object of the present invention to provide a family radio circuit which overcomes the problems encountered in the conventional art- It is another object of the present invention to provide a family radio circuit which is formed in a single chip and implements a light and small volume product.

To achieve the above olbjects, there 'Is provided an ASiC_. circuit unit for controlling each component in a family radio service circuit which includes a wireless communication unit, a voice input and output unit, a power unit, and a display unit. The ASIC circuit unit includes a memory for storing a data with respect to a channel frequency allocated during a wireless communication, a 2 control block for outputting a control signal based on an inner program, a display drive for driving the display unit, an output level control block for controlling an output level of a received voice signal, a divider for dividing an inputted frequency into a certain level frequency for providing a frequency synchronization, a phase detection unit for detecting a phase of an inputted signal, an electric charge pump for controlling an oscillation frequency of an external oscillator based on a result of the detection by the phase detection unit, a frequency fixing detection unit for detecting whether the frequency is locked or unlocked, a buffer for performing a buffering operation of an inputted clock signal, a reference divider for providing a io reference of a phase comparison unit, and a clock signal drive for receiving a certain clock signal and implementing a fan out of the same.

To achieve the above objects, there is provided a radio family service circuit which includes a wireless communication unit, a voice input and output unit, a button input unit, a power unit, a display unit, and a controller. The controller according to the present invention includes an audio band pass filter provided in an ASIC chip having a plurality of terminals based on a hard wire programming method for selecting an audio signal band width,' a sub- audio low pass filter for removing a noise having a frequency below an audible frequency, a MSS tone generation unit for generating a MSS tone, a CTWS tone detection unit for detecting a WC5S tone generated by the CTWS tone generation unit, a serial interface for a serial communication with the outside, and a power onloff controller 3 for controlling the power of the entire system.

BRIEF DESCRIPTION OF THE DRAWINGS

The present invention will become better understood with reference to the accompanying drawings which are given only by way of illustration and thus are not limitative of the present invention, wherein, Figure 1 is a block diagram of a family radio service circuit according to the present invention; Figure 2 is a wave form diagram in the case that a back light is turned on in io a family radio service circuit according to the present invention; Figure 3 is a wave form diagram in the case that a non-tinesignal is outputted in a family radio set-vice circuit according to the present invention., Figure 4 is a wave form diagram of a non-tone signal and a back light signal in a family radio service circuit according to the present invention,- Figures 5 and 6 are viave form diagrams in the case that two alarm tone signals are outputted in a family radio service circuit according to the present invention; Figure 7A is a circuit diagram illustrating the construction of a power unit for detecting a low state of a battery in a family radio service circuit according to the present invention; Figures 713 and 7C are wave form diagrams for describing the wave forms 4 of Figure 7A; Figure 8 is a circuit diagram for describing a method for controlling a volume in an ASICcircuit unit according to the present invention, Figures 9 and 10 are wave form diagrams for describing a wave form of a single bit tone in an ASIC circuit unit according to the present invention; Figure 11 is a wave form diagram for describing a double bit tone in an AS IC circuit unit according to the present Invention; Figure 12 is a wave form diagram for describing a wave form when a channel is scanned in an ASIC circuit unit according to the present invention; Figure 13 is a wave form diagram for describing a wave form when a high tine signal is generated at the maximum volume level in an ASIC circ,,i, unit M4 at.

according to the present invention; Figure 14 is a wave form diagram for describing a wave form when a low tone is generated at the minimum volume level in an ASIC circuit unit according to the present invention., Figure 15 is a wave form diagram for describing a wave form when three series bil. tone signals are generated In an A&C circuit unit according to the present invention., Figure 16 is a wave form diagram illustrating a signal wave condition applied in a power save mode in an ASIC circuit unit according to the present invention., Figure 17 is a wave form diagram for describing a wave form related to an input timing in an ASIC circuit unit according to the present invention; Figure 18 is a wave form diagram for describing a method for removing a chattering problem based on an input in an ASIC circuit unit according to the present invention; Figure 19 is a wave form diagram for describing a wave form when a communication button of a family radio service circuit is pushed according to the present invention; Figure 20 is a wave! form diagram for describing a wave form after a communication button of a family radio service circuit is pushed according to the present invention., Figure 21 is a wave form for describing a voltage control oscillator wave form of a family radio service circuit according to the present invention. , Figure 22 is a wave form diagram for describing a wave form in the case that a lock is implemented in a transmission state in a family radio service circuit according to the present invention; Figure 23 is a wave form Ullagram, for describing a wave form based on a channel change in a family radio service circuit according to the present invention; Figure 24 is a wave form diagram for describing a wave form related to a channel scanning mode in a family radio service circuit according to the present invention; 6 Figure 25 is a wave form diagram for describing a call function in a family radio service circuit according to the present invention, Figure 26 is a wave form diagram for describing a -frequency fixing indication function in a family radio service circuit according to the present invention; Figure 27 is a wave form diagram for describing a wave form in the case that a communication button is pushed when a family radio service circuit is in a frequency fixing state according to the present invention,' Figure 28 is a wave form diagram for describing a wave form when a lo communication button is pushed after'a frequency fixing time is elapsed in a state that a family radio service circuit is in a frequency unlock state according to the present invention; Figure 29 is a block diagram of a control in the case that a unlock state occurs in a frequency during a signal transmission in a family radio service circuit according to the present invention., Figure 30 is a block diagram of a control in the case that a frequency unlock _CI 1 state o rs in a frequency during a signal receiving operation in a family radio service circuit according to the present invention; Figure 31 is a wave form diagram for describing a wave form when an external disturbance signal is inputted in a state that a family radio service circuit is in a frequency fixing state according to the present invention; 7 Figure 32 is a wave form diagram for describing a wave form in the case that a family radio service circuit is in a frequency unlock state during a receiving operation according to the present invention.

Figure 33 is a block diagram of an outer structure of a LCID display unit in a family radio service circuit according to the present Invention; Figure 34 is a block diagram of an outer structure of an ASIC circuit unit according to another embodiment of the present invention., Figure 35 is a block (diagram illustrating a detailed construction of a family radio service circuit according to another embodiment of the present Invention; Figure 36 is a block diagram illustrating the construction of a sub-audio squelch system adapted in an ASIC circuit unit according to amother embodiment of the present invention., Figure 37 is a block diagram illustrating the construction of a CTWS tone generation unit adapted in an ASIC circuit unit according to another embodiment of the present invention, Figure 38 is a block diagram illustrating the construction of a CTWS tone detection unit.31-1 an P101C. circuit unit according to an-other embodiment of the present invention- and Figure 39 is a block diagram illustrating the construction of a power onloff control unit adapted in a family radio service circuit according to another embodiment of the present invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

The family radio service circuit according to the present invention will be explained with reference to the accompanying drawings.

The first embodiment of the present invention which is formed of an ASIC circuit unit with 28 pins will be explained.

Figure 1 is a block diagram illustrating the construction of a FRS circuit according to the present invention. The FRS circuit includes a radio receiving unit for demodulating a radio propagation signal received from the outside, a radio io transmission unit 20 for modulating.the signal and transmitting the signal to the outside_ a frequency mixing unit 90 for generating a certain frequency for modulating and demodulating an audio signal and data, an audio input unit 30 for receiving a user's voice as an electrical signal, a power unit 40 for supplying a certain level power, a button input unit 50 for receiving a value selected by a user as an electrical signal, a LCD unit 60 for displaying the state and function of the system, an audio output unit 70 for outputting a voice of an opponent user, and an ASIC circuit unit 80 flor a radio communication and each component of the circuit.

The construction of the present invention will be explained in more detail.

The radio receiving unit 10 includes a pre-selector filter 12a connected with an antenna for selecting a matching and bandwidth frequency, a low noise 9 amplifier 14a connected with the pre-selector filter for amplifying a signal without any increaser of a noise level, a post-selector filter 12b connected with the low noise amplifier 14a for selecting a certain bandwidth frequency, a mixer 16 connected with the post-selector filter for a conversion to a first intermediate frequency based on a signal match for thereby enhancing a selection capacity, an intermediate frequency band pass filter 12c connected therewith for removing an unnecessary frequency component generated during the above-described routine, an intermediate frequency 1C. 18 connected with the intermediate frequency band pass filter 12c fo.r obtaining a second intermediate frequency conversion and io separating an audio signal therefrom, and a squelch circuit for disconnecting an output of a speaker of a noise signal when a valid signal is weak or there is not a valid signal.

In addition, the radio transmission unit 20 includes a driving amplifier 24b for receiving an audio signal modulated to a carrier wave from the frequency mixing unit 90 and driving the power amplifier 24a for transmitting a high output signal, a power amplifier 24a for increasing a power level necessary for a radio output, and an output low pass 22 for transmitting a signal to a variable band width without any affects to other frequency band widths.

The frequency mixing unit 90 is a sub-feed back system formed of a phase comparator, a loop filter, and a voltage control oscillator A programmable frequency divider is further provided. Namely, the frequency inputted from a temperature compensation crystal oscillator(TCXO) into the ASIC is divided into a reference frequency by a reference divider in the interior of the ASIC and is inputted into the voltage control oscillator 28. The thusly divided reference frequency is compared with the frequency divided by the frequency divider of the ASIC. At this time, a dividing ratio of the reference divider and the frequency divider is determined by the control block so that a certain frequency is mixed. In the case that a phase difference of two inputs is detected by the phase comparator, an input is applied to an electric charge pump by the difference for thereby generating a control voltage for determining the oscillation frequency of io the voltage control oscillator. The control voltage generated by the electric charge pump is outputted in a rectangular form. Therefore, in order to implement a lock frequency of the voltage control oscillator 28, an integrated value is outputted using the loop filter 29 formed of a low pass filter. Namely, the electric charge pump output is adjusted until there is not a phase difference between two input values for thereby mixing an accurate output frequency. In the case of using the frequency mixer, since the output of the voltage control oscillator is outputted in multiple of the reference frequency(for example, 6.25kHz) divided based on an output of the temperature compensation crystal oscillator which provided a lock frequency, it is possible to mix various frequencies. In the circuit, the circuit blocks except for the voltage control oscillator 28, the loop filter 29, and the temperature compensation frequency oscillator is formed in the interior of the 11 ASIC. The frequency mixer directly outputs a FRS frequency of the ultra short wave. In the case that the ultra short wave is not outputted due to a limit in the technology of the ASIC, the FRS frequency is generated using a frequency multiplier 26.

The audio input unit 30 includes a microphone unit 32 for converting a user's voice into an electrical signal, a voice amplifier 34 for amplifying the voice signal, and a first transistor 01 for outputting an output signal of the voice amplifier 34 and disconnecting the output signal of the same based on a control signal from the ASIC circuit unit 80. At this time, the voice amplifier 34 determines an io activation and non-activation of the operation based on a receiving approval signal from the ASIC to minimiZe a power consumption and a certain affect to a neighboring circuit In addition, the power unit 40 -includes first and second resistors R1 and R2 formed of a battery unit V-batt for supplying a certain level power, a power switch for determining whether the power of the battery power is supplied or not, and a power sampling circuit for determining the level of the voltage, and a constant voltage d L evi-.for changing a voltage levei inputted from the power switch as a certain level voltage and outputting the same.

In the button input unit 50, nine switches are formed of three column -20 output terminals and three ow input terminals are crossingly formed in a 3x3 matrix form for a key input detection. The button number selected by the user is 12 inputted into the ASIC circuit unit. At this time, the ASIC circuit unit includes 151h through 17 th terminals used for a common signal output of the LCID driving drive in the ASIC for detecting which button is pushed among nine buttons.

The LCID display unit 60 includes a LCID 82 for receiving a control signal and a data signal from the ASIC circuit unit 80 and displaying a certain data, and a 6 1h transistor Q6 for turning a back-light D3 of the LCID 62 in accordance with a control signal frorn the AS C circuit unit 80.

In addition, the voice output unit 70 includes an amplifier 72 for amplifying a voice signal of an opponent as a signal level from the ASIC circuit unit 80 is adjusted and outputted, a speaker 74 for outputting an amplified voice signal, and a 4 1h transistor 04 and a 5 transistor 05 for non-activating an operation of the amplifier in order to minimize the power consumption. The signals for determining the state of an activation and non-activation of the amplifier are determined by receiving an audio binding control signal from the ASIC circuit unit for detecting a power saving and transmission mode. A diode is further provided for properly transferring the signals.

The F R S AS If C. cil Arcu it u nil wi 11 be exp 1 @'1 ned i n deta i L The ASIC circuit unit according to the present invention is formed of a single chip having 28 pins. The assignment of each pin will be explained as follows.

The 15' pin is a port for receiving a busy signal based on whether a valid signal is inputted. In the case that there is a valid signal, a high logic signal level is 13 inputted, and in the case that there is not a valid signal, a low logic level signal is inputted. In addition, the 2 nd pin is an analog port for receiving a feed-back signal of a VCO frequency for generating an accurate frequency in the frequency synthesizing unit.

The 3 d port is an analog port for outputting an output result of the phase detection unit in the ASIC, and the 5th pin is a ground port with respect to the entire ASIC circuit, and the 6 1h pin is a port for outputting a result with respect to the fixing of the PLL frequency. A desired frequency is locked, a high logic level signal is outputted, and otherwise a low logic level signal is outputted.

The 7th pin is a port for receiving a 12.8MHz clock signal for providing a reference frequency with respect to the PLL in the ASIC, and the 81 pi, n i s a t e s port for testing whether the A.SAC chip operate normally, and the 9 pin is a port for outputting a signal through an antenna in the transmission mode and outputting a low logic level signal after a desired frequency is fixed.

The 10 pin is a reset signal input port for resetting the ASIC circuit unit in the initial operation mode. When the low level signal is inputted, the ASIC circuit unit is reset, and the 11 pin is a used as an analog signal input port for detecting whether the battery voltage is below a certain approvable level.

The 121h through 14t' pins are ports for receiving a user's key input signal, and the 151" and 16th pins are ports for outputting a common signal for a display on the LCD and are used as a detection signal output port for a key input detection, 14 and the 18 1h through 22th pins are ports for outputting a selection signal for selecting each segment on the LCID.

The 23th pin is a port for outputting a control signal for driving a LCD backlight unit. In the case that there is a user's key input, a high logic level signal is outputted for thereby turning on the back-light. The 24 pin Is a port for controlling the power supply at a certain time without affecting a valid signal input detection for minimizing the power consumption at the receiving terminals in the case that there is not a valid signal input for a certain time in the receiving mode. The 25 pin is a port for binding a speaker in the receiving mode and a microphone in the io transmission mode, and in the case that a high logic level signal is outputted, the binding operation is performed.

The 2T' pin is a port for outputting a pulse type tone signal or a beep signal, and the 2711 pin is a port for receiving an audio through a volume control block for adjusting the output level of the speaker of the audio signal, and the 28" pin is a port for outputting a volume-controlled audio signal.

The above-described FRS ASIC circuit requires an input signal such as a power onloff, P7T, channel-up, channel down, volume up, volume down, call, voice monitor and lamp onloff, key lock, etc. and o erates based on the following p characteristics with respect to each input.

1) Power key.- The power key performs a function for connecting or disconnecting the power of the FRS circuit. When the power is connected, (1) an initialization beep is outputted, (2) the LCID back light is turned on for 5 seconds, (3) all icons of the LCD are displayed for 3 seconds, (4) the volume control level is set to an intermediate value, and (E) the communication channel is adjusted as a first channel value.

2) Volume up/down key The volume up/down key. increases and decreases the audio volume level, and lo the entire volume level is formed of 8-steps and is increased and decreased by 3.5d1B with respect to the key input. At this time, the lowest volume level is set to have a non-tone. In addition, in the case that the volume up key is pushed in the highest volume level, two higher tones(2kHz) are generated as an alarm tone, and in the lowest volume level, when the volume down key is pushed, two lower tones(500Hz) are generated as an alarm tone.

The above-described keys are designed to operate in all modes except for the transrni-e-Sion mOlde. rAlt the i-noment when the power is connected, an intermediate level is obtained as an initial level, and the single level is increased or decreased with respect to the single input below 500ms. In the case of the key input above 500ms, the Volume level is decreased or increased at every 300ms until the key input is stopped. At this time, the beep is generated whenever the 16 initial key is pushed, and in the case that the volume level becomes a maximum/minimum level, even when the key input is continuously obtained, the volume level maintains the last level.

When the volume up/down key is inputted, the conversion speed of the s volume level is below 50is. At this time, noise is not generated due to the switching operation.

3) Channel up/down key The channel up/down key is directed to increasing pr decreasing the io transmission and receiving frequency and is increased or decreased by one -4 channel with respect to single key input below 500ms. The channel is clonvel Led until another key input is performed with respect to the key input above 500ms, and a scanning operation is performed with respect to the valid signal input. In the scanning operation, when the valid signal is inputted, and a busy signal is inputted, the operation is stopped for 7 seconds in the above channel, and an audio signal is outputted. After the audio signal is outputted, if there is not key input within 7 seconds, th,e current channel is changed to the next channel, and the scanning operation is continuously performed. The channel scanning mode is finished when (1) when the channel up/down key is pushed, (2) the PTT key is pushed, (3) when the call key is pushed, and (4) when the power is disconnected.

In addition, in the channel scanning mode, the volume and lamp key input 17 is performed. In this case, the scanning mode is continuously performed.

In the last channel, when the channel down key is pushed in the channel up key or initial channel, the, channel is moved to the initial channel and the last channel. Namely, in the case of the FRS, when the channel up signal is inputted in the channel number 14, the channel is moved to the channel 1, and when the channel down signal is inputted in the channel number 1, the channel becomes the channel number 14. In the case'of the RMR, when the channel up signal is inputted in the channel number 8, the channel I's moved to the channel number 1, and when the channel down signal is inputted in the channel number 1, the lo channel becomes the channel number 8.

At the time when the power 'Is connected, the cha,-,,-,ei number in which thle channel is first started is 1.

4) Call key The call key may be used in all cases except for the transmission mode. When the call key is pushed, the operation mode is converted in the current channel. At this time, the call s'i-&1-1C-21, is transmitted for only 2 seconds without an audio signal transmission. The call signal is formed of two tone frequencies. The transmission icon is displayed on the LCD while the call signal is transmitted.

5) communication(Push To Talk.. PTT) key 18 When the communication key is pushed, the current mode is changed from the receiving or standby mode to the transmission mode. While the communication key is being pushed, the transmission icon is displayed, and a transmission path is connected for transmitting the audio signal, and the receiving path is disconnected. 5 When the communication key input is stopped, the audio input path through the microphone is disconnected, and the transmission is finished after a Roger keep is outputted. 6) Monitorllight key 10 The monitor and light key is operable in the case that the power is connected except for the transmission mode- As shown in Figure 2, the 1 'D!;g", is turned on for 10 seconds with respect to the key input below 500ms. At this time, the continuous light key input toggles the current state. Namely, in the case that the light is turned on, when the light key is inputted, the light is turned off. In the 15 case that the LCD light is turned on, when another key is inputted except for a key input(for example, communication button, call button) related to the transmission and the R1ht key input, th,e LC.D lig"' is turned on for 10 seconds from the moment lit 1 L when the keyis inputted.

In the case that there is a key input above 500ms, the current mode is changed to the monitor mode, and the audio path of the receiving unit is opened irrespective of a value signal input, namely, a busy signal input until the key is not 19 inputted. When the monitor is pushed for more than 5 seconds, the mode is changed to an automatic monitor mode.

In the monitor mode, the receiving icon is displayed on the LCD. The automatic monitor mode is finished when (1) the channel up/down key Is pushed, (2) the monitor key is pushed for more than 500ms, and the power is disconnected.

In the automatic monitor mode, when the monitor key is inputted below 500ms, the key input is recognized as a light key input, and in the monitor mode, the LCID back light is turned on for 10 seconds.

7) Lock key In the case that the lock key is pushed for more than one second, the input L with respect to the channel up/down key is negilected. in the Key is locked, the channel movement including a channel scanning operation is prohibited. The lock key icon is displayed on the LCD so that the user confirms the key lock state.

In the key lock state, when the channel up/down key is inputted, as shown in Figure 5, two higher tones(2kHz) are generated as an alarm beep, and in order to release the key lock state, the key lock input must be performedfor more than 1 second. lln addition, in thte ASIC circuit unit 80, there is provided a PLL block for a frequency synthesizer. The PLL data is selected from an inner ROM with respect to an input such as a model selection, communication, channel up/down, channel scan, etc. The value is set to the programmable counter for thereby determining the VCO output frequency and the contents thereof are displayed on the LCID display unit as a channel. At this time, the input frequencies and data needed for the frequency setting operation are shown in Table 1.

Table 1 illustrates the frequencies for the PMR and FRS when the intermediate frequency is 21.4MHz, and the low injection is provided.

In addition, there is a limit for the VC] frequency feed-back input in the construction of the ASIC circuit, the VCO frequency may be multiplied twice times.

In this case, the VCO frequencies of the PMR and FRS are shown in Table 2. The data for controlling the programmable counter are stored in the inner ROM.

[Table 1]

PMR FRS No Frequency First receiving local Frequency First receiving frequency local frequency 1 446.00625MHz 424.6025MHz 462.5625MHz 441.1625MHz 2 446.01875MHz 424.6175MHz 462.5875MHz 441.1875MHz 3 44,r-.nv3,',25MHz 42144.6325MHz 462.6125MHz 441.2125MHz 4 446.04375MHz 424.6475MHz 462.6375MHz 441.2375MHz 446.05625MHz 424.6525MHz 462.6625MHz 441.2625MHz 6 446.06875MHz 424.6675MHz 462.6875MHz 441.2875MHz 7 446.08125MHz 424.6825MHz 462.7125MHz 441.3125MHz 21 8 446.09375MHz 424.6975MHz 467.5675MHz 446.1625MHz 9 467.5825MHz 446.1875MHz 467.6175MHz 446.2125MHz 11 467.6325MHz 446.2375MHz 12 467.6675MHz 446-2625MHz 13 467-6825MHz 446.2875MHz 14 467.7175MHz 446.3125MHz In addition, the operation frequency of the PMR and the FRS is selected based on a key input. In the case of the communication key, a transmission freauencv corresponding to the --- nt cl-anne:s selected, and in the case of the d --- the w i e channel up key, the channel of the frequency increased by the channel distance(PMR.- 12.5kHz, FRS.- 25kHz) rather than the frequency used by the current channel is selected. In the case of the last channel, when there are 8 times in the PMR and 14 times in the FRS, the channel is returned to the channel 1.

r-r_ L-A n 1 L I awle [Table 1 PMR FRS No Transmission Receiving Transmission Receiving 22 frequency frequency frequency frequency 1 223.0031251-1z 212.303125MHz 231.28125MHz 220.58125MHz 2 223.0093751-1z 212.309375MHz 231.29375MHz 220.59375MHz 3 223.015625MHz 212.315625MHz 231.30625MHz 220.60625MHz 4 223.0218751-1z 212.321875MHz 231.31875MHz 220.61875MHz 223.0281251-1z 212.328125MHz 231.33125MHz 220.63125MHz 6 223.0343751-1z 212.334375MHz 231.34375MHz 220.64375MHz 7 223.0406251-1z 212.340625MHz 231.35625MHz 220.65625MHz 8 223.0468751-1z 212.346875MHz 233.78125MHz 223.08125MHz 9 233.79375MHz 223.09375MHz 233.80625MHz 223.10625MHz 11 233.81875MHz 223.11875MHz 12 233.83125MHz 223.13125MHz 13 233.84375MHz 223.14375MHz 14 233.85625MHz 223.15625MHz In the case of the channel down, the channel of the frequency decreased by the channel distance compared to the current channel is selected, and in the case that the first channel is the number 1 channel, for example, in the case of the PRM, it is returned to the number 8, and in the case of the FRS, it is returned to the number 14.

23 The channel scan mode in which the valid signal input is searched by sequentially changing the channel at a certain time is started by pushing the channel up key or the channel down key based on 500ms.

In particular, when the channel up key is pushed, the scanning operation is performed in the direction that the channel is increased, and when the channel down key is pushed, the scanning operation is performed in the direction that the channel is decreased. When the scanning operation is performed, it is checked that whether there is a busy signal based on a valid signal input by changing the channel at every 300ms.

In the case that the channel busy signal is detected, the current channel is stopped for 7 seconds, and an audio signal iS outputted. In the case that the,re is not a key input after 7 seconds when the audio signal is outputted, the channel is moved to the next channel for thereby performing the scanning operation. In the case that the communication key is inputted, the transmission is performed on the current channel (displayed on the LCD), and the scanning mode is finished. In the case that the call key is inputted, the transmission is performed in the current dhannel, and 'the scanning mode is finished- in the case that the voiume and lamp key is inputted, the scanning mode is continued, and the volume and lamp function is performed, and in the case that the channel up/down key is inputted, the scanning mode is finished in the current channel, and in the case that the monitor key is inputted, the key input is not approved.

24 In addition, in the case that there is not a busy signal, the channel is moved to the next channel, and the scanning operation is performed. A this time, in the case that there is a channel up/down key input, the scanning mode is finished in the current channel. In addition, in the case that a communication key or call key is inputted, the key input is not approved. As shown in Figure 6, an alarm beep formed of two high tones is outputted. In this state, in the case that the volume and lamp key is inputted, and the scanning mode is continued, and the volume and lamp function is performed. The monitor key is not approved.

In addition, the condition for finishing the channel scanning mode is io implemented when the channel up/down key is pushed irrespective of the existence of the busy signal. In the case that there is -a busy signal, the ctlannel scanning mode is finished when the communication key and call key are pushed, and the power is disconnected.

The frequency generation unit for generating a certain frequency inPludes a divider formed in the ASIC circuit, a programmable frequency divider, a phase detection unit, an electric charge pump, a frequency fixing state detector, a loop filter as an external device, and a VCO.

When selecting the frequency, in order to obtain a quicker frequency fixing time, the circuit is formed so that the ASIC inner electric charge pump has enough current driving capacity The FRS ASIC circuit according to the present invention includes a circuit for the following additional functions.

1) Battery low voita( e detection As shown in Figure 7a, the voltage level of the batter is received at every 500ms and is compared with a certain reference voltage. In the case that the voltage level of the batter is; lower than the reference voltage, the battery low icon of the LCD is blinked at every 500ms. Namely, if 1In Vd&Vr, there is no change on the LCD. If lln Vdd<Vr, the battery low icon of the LCD is blinked at every 500ms. At this time, n represents a voltage divide ratio determined by a certain resistance for an ASIC input of the battery voltage, and r represents a reference voltage, and Vi- represents a reference voltage.

As shown in Fiaures 713 and 7C, the reference vo!tage of the ASICC cl lip for detecting the low voltage state of the battery is obtained by dividing the output of the constant voltage device and has an allowable error of 50mV In the case that the input voltage of the constant voltage device is decreased below a certain level due to the voltage drop of the battery, the output voltage of the device is decreased, and any effects are minimized when detecting the low voltage state of the batter,, In the case that the low voltage icon of the battery is indicated on the LCD, any change must be removed due to the voltage variation of the battery. Namely, in the case that the low voltage state of the battery is detected when the signal is transmitted or the maximurn audio signal is outputted, even when the battery 26 voltage is recovered from the transmission and audio maximum output, the low voltage state of the battery is maintained.

2) Volume control The level of the audio signal outputted from the intermediate frequency IC is adjusted by the volume control block of the ASIC circuit. At this time, the volume control block is formed of a resistor and an amplifier and has a non-tone and 8 steps. At this time, at each step, the volume is increased or decreased by 3.5based on the value of the resistance.

When a beep is outputted, an audio amplifier input is implemented through io the volume control block so that the output of the speaker is implemented based on the current audio level. The level of the beep tone Outputized from 'the control block has the same level as the intermediate frequency output audio level. The audio level inputted into the ASIC has the maximum value of 130mVi-ms. In the case that there is not a busy input signal, n audio output control circuit is provided based on a busy signal to prevent the output of the noise which may be outputted from the audio output pin of the intermediate frequency IC.

(1) In the case that there is a busy signal: The audio is outputted based on the current audio level, and the beep tone is not outputted.

(2) In the case that there is not a busy signal: No audio output(nontone), and the beep is outputted based on the current audio level.

27 3) Beep tone output,--Ontroi In the case that the beep tone is outputted in the receiving state, it is checked whether there is a busy signal, and the beep output is determined. In the case that there is an audio path, the beep tone is not outputted. When an error such as an audio level up and down is inputted in a state that there is a limit tone, namely, the audio level has the maximum value or minimum value, the beep is outputted in a state that the audio path is open.

In addition, a single beep tone of 1 kHz and 1 00ms is generated when there is not a busy signal with respect to all key inputs except for the call key.

As shown in Figure 9, the beep tone is generated when a key is inputted with respect to other input values except for th,e lamp Ir,\-Wy. In 'the case of the channel up/down, the audio tone becomes dead irrespective of the busy signal, and the beep tone is generated. As shown in Figure 10, in the case of the lamp key, when the key input is finished, the beep tone is generated.

As shown in Figure 11, the double beep tones of lkHz and 100ms outputted twice are outputted at the start of the channel scanning mode when the mode is changed from the manual monitor mode to the automatic monitor mode as shown in Figure 12. As shown in Figure 13, the double beep tone of 2kHz and 100ms which is outputted twice is generated when the volume up key is inputted in the maximum volume level, and as shown in Figure 14, the double beep tone of 500H and 1 00ms which is outputted twice is generated when the volume down key 28 is inputted in the minimum volume level.

As shown in Figure 15, the triple tone is generated when the power is increased.

4) Non-tonelpower save control In the receiving mode, if there is not a valid signal input, a power save signal is outputted for an audio non-tone and power save. In the transmission mode and power saving mode, a power save signal is outputted for preventing a power consumption. in the case that there is not a valid signal in the receiving mode, a transmission non-tone signal is outputted for preventing an audio input io through the microphone when the Roger beep tone is carried on the carrier signal when the transmission is completed. The audio non-tone control is pel-fiuji-tteU-,4 as follows.

In the receiving mode, when there is not a busy signal input, the mode is changed to the communication standby mode, and the audio output of the intermediate frequency [C is removed based on the volume control block of the ASIC so that the audio is not outputted for thereby preventing the input into the audio amplifier and a certain noise in the speaker output. The audio amplifier is non-activated using the non-tone signal output.

In the case that the mode is changed to the monitor mode, an audio signal is outputted from the volume control block based on the current volume level irrespective of the state of the busy signal input until the mode is finished. At this 29 time, the output of the non-tone signal is stopped, and the audio amplifier is activated.

In the receiving state, when outputting a beep tone, the non-tone signal output is stopped in a state, that there is not an audio signal output through the s volume control block in the case that there is not a busy signal, and then the audio amplifier is activated, and the tone is outputted.

The power save control will be explained.

When the communication standby mode is maintained for more than 10 seconds, the power save icon is blinked on the LC1) until a certain key is inputted or a signal is detected. At this time, in the case that there is not a busy signal and key input for more than 10 seconds in the standby mode, the system set is changed from the communication standby mode to the power saving mode.

In the case of the power saving mode, the power of the receiving circuit is controlled based on the Power save output for thereby minimizing the consumption of the battery. At this time, the power save output must be turned onloff at a certain timing so that a valid signal which is newly received in the power saving state is not lost.

In order to prevent a power consumption and malfunction in the transmission mode, the power of the receiving circuit is controlled using the power save pin output.

As shown in Figure.16, after 10 seconds of the communication standby time, the power saving time condition is 300ms at the on time, and the power saving time condition is 700ms at the off time. The above-described time interval is determined based on a frequency fixing and locking time.

The major timing used for the FRS ASIC circuit according to the present invention will be explained.

1) General contents As shown in Figure 17, the signal is inputted based on a key scan method using a 3x3 key matrix due to a limit in the ASIC input port at the input timing.

Therefore, three signals are sequentially scanned for every input port. So, it is needed to determine the scan timing. The key scan signal output is implemented by an output pin of the LC1) driving circuit for thereby determining the scan timing As shown in Figure 18, since a chattering problem occurs during an actual external key onloff operation, a chattering preventing circuit is used for preventing a malfunction. Since the above-described circuit is recognized at a continuous low or high level at a certain period with respect to a valid input state, determining the timing is very important. In addition, the definition with respect to the minimum key deteefion time, namely, the 'Ur-ne limit flor the input scanning timing must be considered. The above-described timing is determined based on the performance of each block provided during the fabrication of the ASIC.

2) Special key function The communication key is directed to a key input for a 31 transmission/receiving conversion. In the case that the communication key is inputted, the mode is changed from the receiving mode to the transmission mode. When the communication key input is completed, the transmission mode is completed after the Roger beep tone is transmitted. Figure 19 illustrates a timing of major circuits based on the communication button.

As shown in Figure 20, after the communication key is inputted, a transmission approval signal must be outputted at 1 0Oms. In this case, if the frequency locking and fixing time is extended, the output over time may be affected, and the transmission output power must reach at the last output power of io -1 dB within 1 Oms after the transmission approval signal is outputted. As shown in Figure 21, the frequency must be locked. In order to lock the frequency, the VCO frequency must be enough locked before the transmission approval signal is outputted.

Therefore, the PLL frequency fixing time must be quicker, and the VCO frequency must be locked before the transmission approval signal is outputted within 1 00ms. At this time, the timing for detecting the frequency fixing state must be accurately processed. As shOwn in Figure 22, in the case that the frequency is not fixed within 100ms after the PLL data is outputted, the system must be converted to the receiving state. in the receiving state, It is checked whether the frequency is fixed or not for 1 00ms.

In the case that the frequency is not fixed, the current channel is biinked 32 on the LCD at a period of 500ms for thereby displaying the frequency unlock state. Here, in the transmission state, if the frequency is locked and fixed, the PLL data is outputted, and the transmission approval signal is outputted.

In addition, the channel up/down key is directed to upwardly or downwardly adjusting the communication channel and is defined as a short input and long input based on the key input condition. As shown in Figure 23, the short input is a single input below 500ms and is increased or decreased by one channel with respect to the key input, and as shown in Figure 24, the long input is a single input above 500ms, and the channel scanning is performed with respect to the key io input.

As shown in Figure 25, the call function is directed to transmitting two different beep tones on the current channel for calling a certain opponent.

In addition, as shown in Figure 26, the frequency locking and fixing function is directed to determining whether the PLL frequency is locked and fixed when the key is inputted. As shown in Figure 27, in the state that the PLL frequency is fixed, a high level signal is outputted, and as shown in Figure 28, the frequency is unlocked, a low level signal is outputted. The above-described function indicates a frequency locking state with respect to a communication, channel up/down, call, scan input, and external disturbance. In addition, the transmission key such as the communication key and call key and the receiving key such as the channel up/down and scan keys must be frequency- iocked and - 33 fixed within 1 00ms after the PLL data is outputted. When the frequency is not locked, the following operation is performed.

First, in the case that the frequency is not locked during the transmission, the transmission frequency data is outputted, and if the frequency is not fixed within 1 00ms, the mode is changed to the receiving mode. Thereafter, the receiving frequency data is outputted, and if the frequency is not locked within 1 00ms, the current channel on the LCID is blinked at a period of 500ms for thereby indicating a frequency unlock state. The frequency fixing detection is continuously performed. In the case that the frequency is fixed, the indication of the frequency io unlock state is removed at the moment when the lock state is obtained. At this time, the conversion to the communication standby mode the power saving mode is not implemented during the frequency unlock state. When the frequency is fixed in the receiving state, the receiving state is continuously maintained on the current channel until another key is inputted.

In the case that the lock is released in the receiving state, first, the receiving frequency data is outputted. Fro this moment, if the frequency is not locked within 1 00ms, the current channel portion on the LC D is blinked at a period of 500ms for thereby indicating a frequency unlock state. Thereafter, the frequency fixing state is continuously checked. When the frequency is fixed, the indication of the frequency unlock state is stopped. In the case that the frequency is locked in the receiving state, the receiving state is continuously maintained on the current 34 channel until another key is inputted.

Here, in order to satisfy the over time during the transmission mode conversion, since the frequency must be enough locked within 100ms, a quick frequency fixing time is required. In the receiving mode, even when the frequency is unlocked, when a communication key or call key is inputted, the mode is converted to the transmission mode, and then the frequency fixing state is checked. The transmission Is normally performed when the frequency is fixed. When the frequency is unlocked, the routine is performed identically to the abovedescribed manner In addition, if the frequency is not locked due to an external disturbance in the transmission and receiving mode. when the frequency sunlock stale is continued for more than 100ms, the routine is performed in the above- described manner. Otherwise, it is neglected.

Figure 29 is a flow chart for processing the frequency unlock state in the transmission state. Figure 30 is a flow chart for processing the frequency unlock state in the receiving state.

Figure 31 illu-strates a wave florm, of a phase difference and a lock detection signal when an external disturbance is inputted in the state that the frequency is locked. As shown therein, in the case that the frequency unlock state is detected, the frequency lock detection signal becomes a low level, and when the phase difference is decreased to an allowable range, a high level signal is outputted for informing the frequency fixed state, As shown in Figure 32, when the frequency is in the unlock state due to an external disturbance, the I'LL data continuously outputs a value with respect to the current channel. When the frequency is not in the lock state within 100ms, a signal which indicates the frequency unlock state is applied to the LCID display unit. As shown in Figure 33, the LCID display unit includes a battery state icon which is blinked based on the state of the battery, a channel indication icon which is currently used, a scanning state icon which indicates the current channel scanning state, a lock state indication icon, a transmission state Icon, a receiving state Icon, an antenna tower icon, a power save mode icon, etc.

The ASIC circuit unit is implemented by 32 pins excen for 28 pins. The r-t difference therebetween will be explained.

Figure 34 illustrates a pin arrangement of the ASIC circuit unit of the FRS according to the present invention. The basic pin construction is the same as the construction of 28 pins except for 15' pin, 8" pin, 17"' pin, and 24" pin which are formed in the NC(Not connect) state. Namely, in the construction of 28 pins, the pin arrangement from 151 tn'"n. t o '281h pin 'Is '1m-ip',er,- ien'ted in the counterciockwise direction from the 25th pin in the 32-pin construction.

The second embodiment of the present Invention will be explained with reference to the accompanying drawings.

In the second embodiment of the present invention, a new function is 36 added based on the basic block circuit of the first embodiment of the present invention. Namely, the second embodiment according to the present invention is well adapted to an advanced FRS system and provides a performance implemented by 44-pin package.

The inner construction of the ASIC circuit unit and the neighboring circuits will be explained.

Figure 35 is a block diagram illustrating the construction of a circuit including an ASC circuit unit of the FRS according to the second embodiment of the present invention which includes a wireless receiving unit 110 for receiving an external wireless data, a wireless transmission unit 120 for transmitting a wireless data to a certain communication opponent, a frequency generation unit.

for generating a certain frequency for modulating and demodulating a voice signal and data, a voice input unit 130 for receiving a voice and converting it into an electrical signal, a power unit 140 for supplying a certain level power, a button input unit 150 formed in a 3-row and 3-column matrix form and selected by a user, a LCD display unit 160 for indicating an operation state and a function, a voice output unit 170 for a voice of an opponent as an audible frequency signal, and an ASIC circuit unit 180 for providing various functions and controls for the FRS system.

In addition, the ASIC circuit unit 180 includes an EEPROM 182 for storing a certain data, a clock signal generation unit(TCXO) for receiving a certain clock 37 signal, and a transistor for controlling the transmission and receiving circuit block.

In the second embodiment of the present Invention, the arrangement of the pins is different from that of the first embodiment of the present invention. In addition, different constructions will be explained in more detail.

In the second embodiment of the present invention, a tone generation function and tone detection function are provided for implementing a CTCSS(Continuous Tone coded Squelch System) which is coded by a series tones. In addition, a serial nterfacing function and a power control function are further provided except for a filtering circuit.

Generally, the frequency of the UCSS is known as a sub-audio frequency because it has a frequency lower than an audible frequency of human. In the transmission and receiving system, a CTUS tone is used for connecting with another system and is used for overcoming a certain interference or is used as a member for preventing the same. Since the CTWS tone is generated based on an output from the system, the user having a system capable of decoding the tones below an audible frequency can not here another interference of the channel.

The user who does not have l.,',,e alkJX^Jve-desci-g bed apparatus has an opened Squelch of the system.

Figure 36 Is a block diagram of a Squelch system using the CTICSS according to the second embodiment of the present invention. In the system, a voice signal is inputted through an external microphone and is amplified by an 38 amplifier The voice sig nal is transferred to a band-pass filter through a preemphasis system.

The tone signal supplied from the MSS tone generation unit is mixed with an output signal of the band-pass filter and is transmitted based on a wireless method.

When receiving a wireless signal, the tone signal is amplified by the amplifier and is transferred to an audio band-pass filter and sub-audio low pass filter The audio band-pass filter filters a signal having 300Hz303kHz frequency, and the sub-audio low pass filter filters a signal having a frequency below 300Hz.

The signal transferred from the audio band-pass filter is outputted through the speaker, and the signal transferred to the CTWS detection unit through the sub-audio low pass filter is outputted to the control block as a CTWS tone detection signal.

1) Sub-audio low pass filter The sub-audio low pass filter filters a tone signal from an audio signal generated by the intermediate frequency IC and removes a high frequency component from the signal generated by the %CTICSS 'Lone generation unit. In the case of the low pass filter adapted to the present invention. A capacitor filter which is capable of varying a cut-off frequency by more than 4 1h order from 1 0Hz to minimum 500Hz is used.

The clock signal applied to the low pass filter for determining the block 39 frequency is applied to the control block of the ASIC circuit unit based on a tone frequency, and the block frequency has a signal level decreased below 3d13. 2) CTCSS tone generation unit There are total 33 standard CT13SS generated by the CTiCSS tone 5 generation unit and has a range of 67Hz-250.3HzAs shown in Figure 37, in the transmission mode, the CTCSS tone is summed with the voice signal and is modulated by the carrier. The frequency component higher than 300Hz must be filtered to prevent any effect to the voice signal. 10 Therefore, in order to minimize the above- described components, the signals are generated in a step wave form rather than a rectangular wave fo,,r-, Thereafter, the high frequency components are removed by the sub-audio low pass filter. 15 [Table 31 No Frequency(hz) No Frequency(hz) No Frequency(hz) No Frequency(hz) 01 67.0 11 0-7.4 21 4136.5 31 192.8 02 71.9 12 100.0 22 141.3 32 203.5 03 74.4 13 103.5 23 146.2 33 210.7 04 77.0 14 107.2 24 151.4 34 218.1 79.7 15 110. 9 25 156.7 35 225.7 06 82.5 16 114.8 26 162.2 36 233.6 07 85.4 17 118.8 27167.9 37 241.8 08 88.5 18 123.0 28 173.8 38 250.3 09 91.5 19 127.3 29 179.9 94.8 20 131.8 30 186.2 In the case of the step wave form, there are provided 8 steps and 5 levels per period. The allowable frequency error of the UXSS is maximum 0.05%, and in the case of the low pass filter, there is a band pass filter of maximum 280Hz.

3) CTCSS tone detection unit U L U 1 L 1 11-e transmission In the case that the CTC,(:-,c-z is set. in order to detect in th signal, the components below 300Hz, namely, the sub-audio components is filtered from the audio output signal of the IF IC. The output of the low pass filter is converted into a logic level by the comparator. The period of the UCSS is io measured. The edge portion of the converted UCSS tone, namely, the rising or failing portion is detected. When the sampling time of the timer which is automatically loaded is set, it is possible to judge the UCSS tone frequency by measuring the number of samplings between two edges. At this time, the block frequency of the sub-audio low pass filter is re-set based on the MSS tone frequency. The audio block must be prevented based on the quality of the receiving data, namely, the MSS frequency, and the audio must become dead 41 without a Squelch tail, and the allowable range of the CTWS is within 2. 73%.

4) Serial interface An external data certain storing member such as he EEPROM is needed for obtaining a data used for an operation except for the operation state and initial set value of the ASIC circuit unit. A high speed communication using a serial interface is required for decreasing a space occupancy due to the input and output pins. The ASIC circuit unit may be adapted to a high capacity system and low capacity system. In order to distinguish the above-described two systems, it Is checked whether the CTCS.3 is used or not. In order to determine whether the WCSS I's used or not, a certain data may be externally set using the serial interface.

In addition, in the case that a power is applied to the system, the data used for determining an initial channel and volume level is read from the EEPROM, and the data is stored in the E.EPROM when finishing the system.

5) Power on/off controller The power onloff controller controls the power of the entire system using an output voitacie control nort. The oneration of 11111e sar-ne will be explained with reference to Figure 8.

Figuren39 is a block diagram for explaining a power onloff controller for the FRS ASIC according to the present invention. The operation in which the power is changed from the off state to the on state and the operation in which the 42 power is changed from the on state to the off state will be explained. First, the 43th pin of the ASIC circuit unit, namely the power onloff recognition terminal according to the present invention is in the pull down state and maintains a logically low level when the power switch is not connected. 5 1) in the case that the power is changed from the off state to the on state When the power switch is connected, a power is applied to the control terminal of the constant voltage device through the diode D1, and the constant voltage device outputs a certain level voltage. At this time, the power is supplied for enough time(about 2 seconds) for driving the ASIC circuit unit. The power 10 switch must be in the pushed state for the above-described time. The power on input is checked through the 43th pin which is the power onloff recognition terminal after the ASIC circuit unit is driven. The logic high level voltage is outputted through the 44" pin which is the constant voltage device control terminal, so that the ASIC circuit unit controls the operation of the constant 15 voltage device. 2) In the case that the power is changed from the on state to the off state When the power switch is pushed for a certain time in the state that the power is in the on state, the power off input is recognized through the 43th pin which is the power onloff recognition terminal, and the output voltage of the 44th 20 pin is removed, and the operation of the constant voltage IC is stopped. Here, the time required for the ASIC circuit unit to recognize the power 43 onloff signal Is 2 seconds.

The pin arrangements based on the input and output signals of the ASIC will be compared with respect to the first embodiment(28-pin structure) and the second embodiment(44-pin structure) according to the present invention with 5 reference to Table 4.

[Table 4]

No Pin name Pin definition Pin number 28-pin 44-pin package package 1 Busy Busy signal input 1 31 2 F-in VCO frequency input 2 34 3 VDD Power input 3 35 4 PLL-out PLL phase detector output 4 36 VSS Ground(GNID) 5 37 6 LD PLL frequency fixing 6 38 detector GUIpUl, 7 CLK Clock signal 7 40 input(12.8MHz) 8 Test Test pin 8 33 9 Tx-En Transmission approval 9 22 44 RESET Control block reset input 10 5 11 PWR On/Off Power onloff input - 43 12 Reg. Ctri Constant voltage device - 44 control output 13 Vsense Battery voltage input 11 1 14 SW-1n3 Button key input 3 12 8 SW-1n2 Button key input 2 13 7 16 SW-M Button key input 1 14 6 17 ComO LCID common output 0 15 10 18 Corril LCID common output 1 16 11 19 Com2 LCID common output 2 117 12 Com3 LCD common output 3 - 13 21 SegO LCID segment selection 18 14 output 0 22 Segl LCID segment selection 19 15 output 1 23 Seg2 LCD segment selection 20 16 output 2 24 Seg3 LCID segment selection 21 17 output 3 Seg4 LCID segment selection 22 18 output 4 26 Seg5 LCD segment selection 19 output 5 27 Seg6 LCD s-e21 gment selection - 20 output 6 28 Se97 LCD se259ment selection 21 output 7 29 BL LCD back light control 23 24 output PS Power save control output 24 25 31 Mute Audio/mic non-tone control 25 26 output 32 Beep Beep tone output 26 41 33 VoLout Audio volume input 27 34 Vol-in Audio volume output 28 - VDD2 Power input 2 23 36 VSS2 Grouncl 2"k'JN'U') 9 37 MOD Modulation signal input 39 38 Sub-audio Sub-audio output 42 out 39 ENABLE Serial interfacing approval 2 46 S-DATA Serial data input and output - 3 41 S-CLK Serial interfacing sync clock - 4 42 AGND Analog ground 28 43 Rx Audio In Receiving audio input - 29 44 Audio Out Volume controlled audio - 27 output Tx Audio in Transmission audio input - 30 46 Tx Audio out Transmission audio output - 32 In the present invention, a mass production is well adapted to any type of the product such a system having additional functions and a basic function product by implementing a single ASIC chip product- The volume and weight of the system may be decreased based on a hard wired programming technique. In addition, the present invention is implemented based on an enhanced communication quality by adapting the tone squelch system.

The advantages of the present invention will be explained.

First, the present invention is well adapted to any type of products by produci, -,g the sam le AS K0. ci rcuilt unit with respect to European type or 'Ul S type.

Second, in the present invention, there are many additional functions, and since the ASIC circuit unit is same to various low cost products, an easier upgrade is implemented by providing low cost parts, and it is possible to easily provide additional function upgrades.

47 Third, the universal type microprocessor Is not used. In addition, it is possible to prevent a resource consumption of the microprocessor. In addition, the volume and weight of the products are significantly decreased compared to the products which adapt the microprocessor.

As the present invention may be embodied in several forms without departing from the spirit or essential characteristics thereof, it should also be understood that the above-described embodiments are not limited by any of the details of the foregoing description, unless otherwise specified, but rather should be construed broadly within its spirit and scope as defined in the appended claims, lo and therefore all changes and modifications that fall within the meets and bounds of the claims, or equivalences of such meets and bounds are therefore intended to be embraced by the appended claims.

48

Claims (13)

What is claimed is.

1. In a family radio service circuit including a wireless communication unit, a voice input and output unit, a power unit, and a display unit, an ASIC circuit unit for controlling each component, comprising:

a memory for storing a data with respect to a channel frequency allocated during a wireless communication, a control block for outputting a control signal based on an inner program; a display drive for driving the display unit., an output level control block for controlling an output level of a received voice signal.' a divider for dividing an inputted frequency into a certain level frequency for providing a frequency synchronization.

a phase detection unit for detecting a phase of an inputted signal; an electric charge pump for controlling an oscillation frequency of an external oscillator based on a result of the detection by the phase detection unit, a frequency fixing detection unit for detecting whether the frequency is locked or unlocked.

a buffer for performing a buffering operation of an inputted clock signal; a reference divider for providing a reference of a phase comparison unit; and 49 a clock signal drive for receiving a certain clock signal and implementing a fan out of the same.

2. An ASIC circuit unit of claim 1, further comprising.

a communication busy signal input port,- a WO frequency input port, a power input port. a PLL signal output port- a ground signal input port. a frequency fixing display port. a clock signal input port; a test port; a transmission approval port; a reset signal applying port: a battery voltage detection port., a switching input port,1 st port through 8th ports for driving the LCID display unit- an onloff control signal io output port for a back light of the LCID display unit., a power save or receiving approval port. a beep tone output port- and a speaker volume control input and output port.

3. An ASIC circuit unit of claim 1, wherein said LCID display unit is driven by receiving a 5-bit segment input for classifying a display data and a 3-bit control signal which is a control instruction and displays a battery low state, a current channel, a frequency lock state, and a power save mode.

4. An ASIC circuit unit of claim 1, wherein said control block is formed of a plurality of logic. circuits programmed by a hard wide method.

5. An ASIC circuit unit of claim 1, wherein said signal inputted from the ASIC circuit unit is a power onloff signal, a communication button signal, a channel up and down button signal, a volume up and down button signal, a call button signal. A monitor/backlight and a button lock signal.

6. An ASIC circuit unit of claim 1, wherein a VCO transmission frequency stored in the memory is 231-233MHz, and a VCO receiving frequency is 220MHz-223MHz.

7. An ASIC circuit unit of claim 1, wherein a WO transmission frequency stored in the memory is 462467MHz, and a VCO receiving frequency is 441 MHz-446MHz.

8. An ASIC circuit unit of claim 1, wherein a WO transmission frequency stored in the memory is used by multiplying twice, and a PMR WO transmission frequency is 223MHz, and a PMR VCO receiving frequency is 212MHz.

9. An ASIC circuit unit of claim 1, wherein a PMR VCO transmission frequency stored in the memory is 446MHz, and a receiving frequency is 424MHz.

51

10. An ASIC circuit unit of claim 1, wherein a FRS(Family Radio Service) transmission frequency stored in the ASIC circuit unit is 462467MHz, a receiving frequency is 441-,96MHz, a PMR transmission frequency is 446MHz, and a receiving frequency is424MHz.

11. In a radio farnily service circuit including a wireless communication unit, a voice input and output unit, a button input unit, a power unit, a display unit, and a controller, said controller comprising- an audio band pass filter provided in an ASIC chip having a plurality of io terminals based on a hard wire programming method for selecting an audio signal band width,.

a sub-audio low pass filter for removing a noise having a frequency below an audible frequency, a CTCSS(Continuous Tone Coded Squelch System) tone generation unit for generating a CTWS tone., a CTWS tone detection unit for detecting a =SS tone generated by the CTCSS tone generation unit., a serial interface for 3 serial communication with the outside- and a power onloff controller for controlling the power of the entire system.

12. The controller of claim 11, wherein said MSS tone is 38 tone 52 frequencies selected in a range of 671-1z-250.3Hz.

13. The controller of claim 11, wherein said low pass filter is a capacitor low pass filter which is capable of varying a block frequency by more s than 4-order in a range of 10Hz to minimum 500Hz.

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