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GB2356287A - Apparatus and method for packaging different sized semiconductor chips on a common substrate - Google Patents

Apparatus and method for packaging different sized semiconductor chips on a common substrate Download PDF

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Publication number
GB2356287A
GB2356287A GB0017321A GB0017321A GB2356287A GB 2356287 A GB2356287 A GB 2356287A GB 0017321 A GB0017321 A GB 0017321A GB 0017321 A GB0017321 A GB 0017321A GB 2356287 A GB2356287 A GB 2356287A
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United Kingdom
Prior art keywords
pads
semiconductor
package
peripheral
chip
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
GB0017321A
Other versions
GB2356287B (en
GB0017321D0 (en
Inventor
Tarun Verma
Larry Anderson
Jon Long
Bruce Pedersen
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Altera Corp
Original Assignee
Altera Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Altera Corp filed Critical Altera Corp
Publication of GB0017321D0 publication Critical patent/GB0017321D0/en
Publication of GB2356287A publication Critical patent/GB2356287A/en
Application granted granted Critical
Publication of GB2356287B publication Critical patent/GB2356287B/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
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  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

A semiconductor package (20) has universal substrate (22) with substrate traces (28) connecting interior pads (24) with peripheral pads (26). The package may include internal package traces (30) connecting the interior (24) and peripheral (26) pads to package pins (32). The interior (24) and peripheral (26) pads are designed for configuration with semiconductor chips of different sizes (Figs. 4 to 6). The coupling of the interior (24) or peripheral (26) pads to the semiconductor chip may be by flip-chip pads (48, Fig. 4), or bonding pads (52, Fig. 5)

Description

2356287 "PARATUS A" METHOD FOR PACKAGING DIFFERENT SIZED SEMICONDUCTOR
CHIPS ON A COMMON SUBSTRATE
BRIEF DESCRIPTION OF THE INVENTION
This invention relates generally to the packaging of semiconductor chips.
More particularly, this invention relates to a technique for packaging different sized semiconductor chips on a common substrate.
BACKGROUND OF THE INVENTION
After a semiconductor is designed, a separate package is typically designed to house the serniconductor. The reliance upon a separate package for every semiconductor design leads to expensive and time-consuming package design efforts.
Accordingly, it would be highly desirable to reduce package design expenses.
SUMMLARY OF THE INVENTION A semiconductor package includes a universal substrate with interior pads, peripheral pads, and substrate traces positioned between the interior pads and the peripheral pads. The interior pads are configured for electrical interface with a first semiconductor chip. The peripheral pads are configured for electrical interface with a second semiconductor chip that is larger than the first semiconductor chip.
1 The invention reduces package design expenses by providing a universal package substrate that can receive semiconductor chips of different sizes. Thus, a single package can be used for a variety of devices. Pre-ferably, the substrate connections (e.g., power pins, data pins, control pins, and the like) are universally the same, regardless of the semiconductor that is positioned within the package. The invention reduces time to market by reducing substrate design times, reducing nonrecurring expenses, and reducing inventory costs.
BRIEF DESCRIPTION OF THE DRAWINGS
For a better understanding of the invention, reference should be made to the following detailed description taken in conjunction with the accompanying drawings, in which:
FIGURE I is a. cross-sectional view of a universal semiconductor package constructed in accordance with an embodiment of the invention.
FIGURE 2 illustrates a universal substrate used in accordance with an embodiment of the invention.
FIGURE 3 illustrates how different sized semiconductor chips can be positioned on the universal substrate of the invention.
FIGURE 4 illustrates the universal semiconductor package of the invention utilized with a semiconductor of a first size.
FIGURE 5 illustrates the universal semiconductor package of the invention utilized with a semiconductor of a second size.
FIGURE 6 illustrates the universal semiconductor package of the invention utilized with a semiconductor of a third size.
FIGURE 7 illustrates the universal semiconductor package of the invention utilized with a programmable logic device that is incorporated into a digital system.
Like reference numerals refer to corresponding parts throughout the drawings.
DETAILED DESCRIPTION OF THE INVENTION
Figure I is a cross-sectional view of a universM semiconductor package 20 constructed in accordance with an embodiment of the invention. The package 20 2 includes a universal substrate 22, which is used as a single interface to different sized semiconductor chips.
The universal substrate 22 includes interior pads 24, peripheral pads 26 and substrate traces 28 positioned between the interior pads 24 and the peripheral pads 26.
Internal package traces 30 link the interior pads 24 (or peripheral pads 26) to a set of package pins 32. For each substrate trace 28 between an interior pad 24 and peripheral pad 26 there is a single internal package trace 30. Thus, a semiconductor is attached to either the interior pad 24 or the peripheral pad 26 associated with a single substrate trace 28.
Figure.2 is a pan view of the universal substrate 22. The figure illustrates interior pads 24, peripheral pads 26, and a substrate trace 28 positioned between each interior pad 24 and each peripheral pad 26.
Figure 3 is a plan view of the universal substrate 22 showing how it can receive different sized semiconductor chips. In particular, the figure shows a first sized semiconductor chip 40.with Rip-chip pads 42. The figure. also illustrates a second sized semiconductor chip 44 larger than the first sized semiconductor chip 40, and a third sized semiconductor chip 46 larger Tlian the second sized semiconductor chip 44.
Figure 4 is a side view of the first semiconductor chip 40 positioned on the universal substrate 22. The first semiconductor chip 40 is flip-chip attached to the interior pads 24 via bond balls 48.
Figure 5 is a side view of the second semiconductor chip 44 positioned on the universal substrate 22. The second semiconductor chip 44 is attached via an insulating adhesive 50. Bond pads 52 of the semiconductor chip 44 are attached to the peripheral pads 26 of the substrate 22 via bond wires 54.
Figure 6 is a side view of a third semiconductor chip 46 positioned on the universal substrate 22. The third semiconductor chip 46 is flip-chip attached to the peripheral pads 22 via bond balls 60.
Preferably, the package pins have dedicated signal assignments (e.g., power pin, control pin, 1/0 pin, and the like) regardless of the type or size of semiconductor chip positioned on the substrate 22. In one embodiment, core connections are arranged in the center ofthe package with radial connections for power, ground, and expansion of signal lines aud associated power of various voltage levels.
3 The universal substrate 22 may be implemented exclusively for flip-chip connections, The universal substrate 22 may include intermediate pads positioned between the interior pads 24 and the peripheral pads,26.
Figure 7 illustrates a programmable logic device (PLD) positioned within the universal package 20 of the invention. PLDs (sometimes referred to as FALs, PLAs, FPLAs, PLDs, EPLDs, EEPLDs, LCAs, or FPGAs) are well-known integrated circuits that provide the advantages of fixed integrated circuits with the flexibility of custom integrated circuits, Such devices allow a user to electrically program standard, off-theshelf logic elements to meet a user's specific needs. See, for example, U.S. Patent Number 4,617,479, incorporated herein by reference for all purposes. Such devices are currently represented by, for example, Altera's MAX0 series of PLDs and FLEXO series of PLDs. The former are described in, for example, U-S. Patent Numbers 5,2241,224 and 4,871,930, and the Altera Data Book. June 1996, all incorporated herein by reference, The latter are described in, for example, U.S. Patent Numbers 5,258,668; 5,260,610; 5,260,611; and 5,436,575, and the Altera Data Book, June 1996, all incorporated herein by reference.
The PLD wid-dn package 20 forms a part of a data processing system 122. The data processing system 122 may include one or more of the following components: a processor 124, a memory 126, input/output circuitry 12 8, and peripheral devices 13 0.
These components are coupled together by a system bus 132 and are populated on a circuit board 134, which is contained in an end-user system 136.
The system 122 can be used in a wide variety of applications, such as computer networking, data networking, instrumentation, video processing, digital signal processing, or any other application where the advantage of using re-prograrnmable 25- logic is desirable. The PLD in the package 20 can be used to perform a variety of logic functions. For example, the PLD can be configured as a processor or controller that works in cooperation with processor 124. The PLD may also be used as an arbiter for arbitrating access to a shared resource in the system 122. In yet another example, the PLD can be configured as an interface between the processor 124 and one of the other components in the system 122.
The foregoing description, for purposes of explanation, used specific nomenclature to provide a thorough understanding of the invention. However, it will
4 be apparent to one skilled in the art that the specific details are not required in order to practice the invention. In other instances, well known circuits and devices are shown in block diagram form in order to avoid unnecessary distraction ftom the underlying invention. Thus, the foregoing descriptions of specific embodiments of the present invention are presented for purposes of illustration and description. They are not intended to be exhaustive or to limit the invention to the precise forms disclosed, obviously many modifications and variations are possible in view of the above teachings, The embodiments were chosen and described in order to best explain the principles of the invention and its practical applications, to thereby enable others skilled in the art to best utilize the invention and various embodiments with various modifications as are suited to the particular use contemplated. It.is intended that the scope of the invention be defined by the following claims and their equivalents..

Claims (19)

  1. )V_RAT IS CLAIMED I
    I. A semiconductor package, comprising:
    a universal substrate including interior pads, peripheral pads, and substrate traces positioned between said interior pads and said peripberal pads, said interior pads being configwed for electrical interface with a first semiconductor chip, and said peripheral pads being configured for electrical interface with a second semiconductor chip that is larger than said first semiconductor chip.
  2. 2. The semiconductor package of Claim 1,.wherein said universal substrate comprises a center portion and a peripheral portion, wherein said interior pads are located on said center portion, and wherein said peripheral pads are located on said peripheral portion.
  3. 3. The semiconductor package of Claim 1, wherein said universal substrate comprises substrate traces that couple said interior pads to said peripheral pads.
  4. 4, The semiconductor package of Claim 3, fin-ther comprising:
    package pins; and internal package traces that couple said interior pads to said package pins.
  5. 5. The semiconductor package of Claim 1, wherein said interior pads are configured for coupling to ftip-chip pads of said first semiconductor chip.
  6. 6. The semiconductor package of Claim 1, wherein said interior pads are configured for attaching to flip-chip pads of said first semiconductor chip by ond balls.
  7. 7. The semiconductor package of Claim 1, wherein said peripheral pads are configured for coupling to flip-chip pads of said second semiconductor chip.
  8. 6 8- The semiconductor package of Claim 1, wherein said peripheral pads are configured for attaching to flip-chip pads of said second semiconductor chip by bond balls.
  9. 9. The semiconductor package of Claim 1, wherein said peripheral pads are configured for coupling to bond pads of said second semiconductor chip.
  10. 10. The semiconductor package of Claim 1, wherein said peripheral pads are configured for attaching to bond pads of said'secorld semiconductor chip by bond wires.
  11. 11. A -semiconductor package, comprising:
    a universal substrate configured for electrical interface with one of a plurality of semiconductor chips including a first semiconductor chip and a second semiconductor chip, wherein said second semiconductor chip is larger than said first semiconductor chip.
  12. 12. The semiconductor package of Claim 11, wherein said universal substrate comprises:
    interior pads positioned on a center portion of said universal substrate, said interior pads being configured for coupling to said fint semiconductor chip; peripheral pads positioned on a peripheral portion of said universal substrate, said peripheral pads being configured for coupling to said second semiconductor chip; and substrate traces for coupling said interior pads to said peripheral pads.
  13. 13. The semiconductor package of Claim 12, Ruther comprising: package pins; and internal package traces that couple said package pins to said interior pads.
  14. 14. The semiconductor package of Claim 12, wherein said interior pads are configured for coupling to flip-chip pads of said first semiconductor chip.
  15. 7 is. The semiconductor package of Claim 12, wherein said interior pads are configured for attaching to flip-chip pads of said first semiconductor chip by bond balls.
  16. 16. The semiconductor package of Claim 12, wherein said peripheral pads are configured for coupling to flip-chip pads of said second semiconductor chip.
  17. 17. The semiconductor package of Claim 12, wherein said peripheral pads of configured fbT attaching to flip-chip pads of said second semiconductor chip by bond 10 balls.
  18. 18. The semiconductor package of Claim 12, wherein said peripheral pads are configured for coupling to bond pads of said second semiconductor chip.
  19. 19. The semiconductor package of Claim 12, wherein said peripheral pads are configured for attaching to bond pads of said second semiconductor chip by bond wires.
    9
GB0017321A 1999-07-15 2000-07-17 Apparatus and method for packaging different sized semiconductor chips on a common substrate Expired - Fee Related GB2356287B (en)

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DE10146306A1 (en) * 2001-09-19 2003-01-02 Infineon Technologies Ag Electronic component with semiconducting chip(s) has bearer substrate with at least sectionally parallel conducting tracks on surface facing chip(s) in contact with chip contact surfaces

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Publication number Priority date Publication date Assignee Title
CN113709970B (en) * 2021-07-16 2022-03-04 北京金百泽科技有限公司 Electronic equipment, PCB and chip packaging structure thereof

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US4195195A (en) * 1978-09-28 1980-03-25 The United States Of America As Represented By The Secretary Of The Army Tape automated bonding test board
GB2115607A (en) * 1982-02-05 1983-09-07 Hitachi Ltd Semiconductor device and a method of producing the same
EP0171232A2 (en) * 1984-08-09 1986-02-12 Minnesota Mining And Manufacturing Company Area-bonding tape
US5399903A (en) * 1990-08-15 1995-03-21 Lsi Logic Corporation Semiconductor device having an universal die size inner lead layout
US5637920A (en) * 1995-10-04 1997-06-10 Lsi Logic Corporation High contact density ball grid array package for flip-chips

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4195195A (en) * 1978-09-28 1980-03-25 The United States Of America As Represented By The Secretary Of The Army Tape automated bonding test board
GB2115607A (en) * 1982-02-05 1983-09-07 Hitachi Ltd Semiconductor device and a method of producing the same
EP0171232A2 (en) * 1984-08-09 1986-02-12 Minnesota Mining And Manufacturing Company Area-bonding tape
US5399903A (en) * 1990-08-15 1995-03-21 Lsi Logic Corporation Semiconductor device having an universal die size inner lead layout
US5637920A (en) * 1995-10-04 1997-06-10 Lsi Logic Corporation High contact density ball grid array package for flip-chips

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE10146306A1 (en) * 2001-09-19 2003-01-02 Infineon Technologies Ag Electronic component with semiconducting chip(s) has bearer substrate with at least sectionally parallel conducting tracks on surface facing chip(s) in contact with chip contact surfaces

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GB0017321D0 (en) 2000-08-30

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