GB2353677A

GB2353677A - Pulse shaping binary data into a baseband signal for a modulation scheme using a digital filter

Info

Publication number: GB2353677A
Application number: GB9919779A
Authority: GB
Inventors: Albert Shyu; Sheng-When Shyue
Original assignee: Winbond Electronics Corp
Current assignee: Winbond Electronics Corp
Priority date: 1999-08-21
Filing date: 1999-08-21
Publication date: 2001-02-28
Anticipated expiration: 2019-08-21
Also published as: GB9919779D0; GB2353677B

Abstract

A modulation system has a digital filter that receives serial binary data D<SB>i</SB> that is stored in shift register 815. The contents of the register are fed into a combinational logic circuit 812 along with the output of a counter 811 that is clocked at a multiple of the data bit rate. The combinational logic circuit outputs data representative of one of an optimised number of samples of the filters output in response to the binary data input (see figures 5-7 regarding the optimisation). This optimisation allows the decoder to be simplified. The decoder 813 then decodes this data into control data suitable for the DAC 82 which outputs an analogue signal representing the binary data signal subjected to the filter function. The DAC is selected with output levels to match the optimised sample points to reduce complexity and is therefore non linear. The analogue signal can then be filtered 83 and used as a modulating signal 84. The filter function is preferably a Gaussian low pass filter function (GLPF).

Description

2353677 DIGITAL MODULATOR

FIELD OF THE INVENTION

The present invention relates to a digital modulator, and more particularly to a Gaussian frequency shift key (G17SK) modulator based on a frequency modulated scheme for integrated circuit implementation.

BACKGROUND OF THE INVENTION

Cordless telephones have become more and more popular in homes and offices. A cordless telephone typically includes a base and a handset.

A transmitter is an important component needed by both the base and the handset for facilitating the transmission of voice signal between the base and the handset. Each transmitter includes a modulator for modulating voice signal into a modulated signal that is suitable for transmission.

The transmitter structure can be divided into two types. One uses the quadrattire modulator (IQ scheme, as shown in Fig. 1) and such an application has been disclosed in many patents, for example, US Patent No. 5,121,412, which describes a "Digital GMSK Modulator with Noninteger Bit Interval Handling", and US Patent No. 5,022,054, which describes an "AllDigital Quadrature Modulator". Another iinplei-nentation/architect-tire is based on frequency modulated (FM) scheme shown in Fig. 2.

Fig. 1 shows the generally functional blocks of a conventional quadrature modulator 1. More specifically, the quadrat-ure modulator 1 includes a logic 11 for receiving a clock signal CLK and data Di to be transmitted. The logic 11 provides address signals to a first channel and a second channel, respectively. The serial bit data Di is divided into a 1 1 sinusoidal function (the first channel) and a cosine function (the second channel) through the logic I I controlled by the clock signal CLK. The first channel includes a first read only memory (ROM) 12 1, a first digitalto-analog converter (DAQ 13 1, a first low-pass filter (LPF) 14 1, and a first inixer 15 1, all of which are electrically connected in series. The second channel, which is parallel to the first channel, includes a second read only ineinory (ROM) 122, a second DAC 132, a second LPF 142, and a second mixer 152, all of which are electrically connected in series. The first channel is designated as the I-channel, and the second channel is designated as the Q-channel. The output of the mixer 151, 152 are summed to generate a modulated signal s(t). It is noted that two channels are employed to increase the accuracy and quality of the data to be transmitted.

However, such a conventional modulator suffers from the following disadvantages. First, two channels have several saine circuits, thereby increasing the cost of the modulator and the overall cost to implement the transmitters. Moreover, since the ROMs 121, 122 are used to implement the waveforin s(t), both of them include the look-up tables for the sine and cosine carrier signals and the sine and cosine phase data signals, thereby making the size of the ROMs 121, 122 undesirably large. Since ROMs 121, 122 are typically unplemented as embedded ROMs, the space consideration is even more important.

Fig. 2 is a block diagram that illustrates a single channel modulator.

More specifically, Fig. 2 shows the function diagram of Gaussian freqiiency shift key (GFSK) transmitter using FM modulated scheme, The single channel modulator 2 includes a pulse shaping filter (PSF) 2 1, a 2 DAC 22, and an FM modulator 23, all of which are electrically connected in series. The PSF 21 receives a clock signal and transmitted data Di. Based on these inputs, the PSF 21 generates a digital version of a pulse shaping filter output b(t) by the result of convolution of input data Di and the pulse shaping filter g(t). The DAC 22 receives the digital output of PSF 21 and converts the output into a corresponding analog signal, which is commonly referred to as the pulse shaping filter output b(t). The FM modulator 23, which includes a voltage controlled oscillator (VCO), then generates a modulated signal s(t) based on the pulse shaping filter output b(t).

The pulse shaping filter 21 herein serves as a Gaussian low-pass filter (GLPF). Fig. 3 illustrates a circuit diagram of a GLPF 3 known by those of ordinary skill in the art. The GLPF 3 in Fig. 3 uses a scheme based on the conceptual block diagram shown in Fig.. e conventiona GLPF 3 includes a shift register 3 1, a counter 32, a control logic 33, an encoder 34, and a Gaussian low-pass filter table 35 embedded in an ROM. 3 bits data Di will be stored in the shift register 31 during one bit period. The encoder 34 perfornis an encoding procedure according to the data stored in the shift register 31 to obtain the corresponding address in the ROM of the Gaussian low-pass filter table 35. At this moment, the most significant bit (MSB) in the address bus is locked and the counter 3 is used to count the least significant bit (LSB) In the address bus so as to read several corresponding data in the ROM during one bit period and output them to the DAC 36. The DAC 36 converts data once after each reading. As a result, the DAC 36 will output an analog signal b(t) corresponding to the bit data Di filtered by the digital Gaussian filter. The 3 analog signal b(t) is then transferred to a modulator through a low-pass filter (LPF) 37.

The major shortcomings of the conventional Gaussian low-pass filter teclmique are as follows:

1. Since the Gaussian filter table must be stored in a memory, which is typically a ROM, it results in that a ROM has to be externally attached to an integrated circuit of GLPF and a few surface area is thus taken by the ROM on a circuit board.

2. If the ROM and GLPF are designed as the same integrated circuit, the design cost will be increased and the ROM will occupy some space in a chip of the integrated circuit.

3. A large volume ROM is required for an accurate calculation, i.e.

using more byte to store an index value in the Gaussian low-pass filter table.

4. The Gaussian ftuiction values stored in an ROM will be highly repeated in the Gaussian low-pass filter table, i.e. the same data will be stored in different addresses resulting in a waste of memory space.

Thus, it is tried by the applicant to deal with the situation encountered with the prior art.

SUNEVLARY OF THE INVENTION An object of the present invention is to provide an improved digital modulator that employs a single channel.

Another object of the present invention is to provide a novel digital modulator based on a frequency modulated scheme for integrated circuit implementation.

4 Another further object of the present invention is to provide a digital modulator that employs a Gaussian low-pass filter (GLPF) and a non linear Digit-to-Analog converter (DAC) with finite input levels so as to reduce the complexity of the synthesized circuit in comparison with a general purpose DAC following the GLPF.

In order to accomplish the objects of the present invention, a digital modulator is provided with a digital filter and a non-linear converter that perforrns a convolution operation between the input data and a filter function. The digital modulator has an input for receiving a serial bit data and an output for outputting an analog signal converted from the serial bit data corresponding to the filter function. The digital filter has a combined logic circuit for generating the filter function. The digital filter stores the serial bit data to generate a binary code, obtains an index value corresponding to the binary code, and decodes the index value to generate a decoded data. Then, the non-linear converter which is electrically connected to the digital filter converts the decoded data to the analog signal. The modulator of the present invention is designe to operate in a signal channel. By utilizing a signal channel modulator, circuit elements are not duplicated, thereby providing power, space and cost savings. In addition, the present invention provides a modulator based on a frequency modulated scheme so that the complexity of the synthesized circuit can be reduced in comparing with a general purpose DAC following the GLPF. In one preferred embodiment, the filter function is a Gau ssian filter ftinction, preferably a Gaussian low-pass filter ftinction. 25 Preferably, the digital filter is a digital Gaussian low-pass filter (GLPF).

In accordance with another aspect of the present invention, the digital filter flirther includes a counter electrically connected to the input and the combined logic circuit for receiving a clock signal and generating a certain number of sampling times during one bit period, a shift register electrically connected to the input and the combined logic circuit for receiving the serial bit data and storing the serial bit data to generate the binary code to be transmitted to the combined logic circuit, and a decoder electrically connected to the combined logic circuit for decoding the index value to generate the decoded data.

In accordance with another aspect of the present invention, the counter provides 12 sampling tlines during one bit period for the combined logic circuit to generate 12 index values dtinng one bit period. Preferably, the counter is a 4-bit interpolation counter with a modulus of 12 (N=12).

In accordance with another aspect of the present invention, the shift register is a 3-bit shift register for storing 3 bits serial bit data and providing a 3-bit binary code to the combined logic circuit. The combined logic circuit provides the index value to the non-linear converter corresponding to the binary code and the sampling time.

Preferably, the index value is a 5-bit index value having 30 different levels. The decoder decodes the 5-bit index value transmitted from the combliled logic circuit to a required control bits decoded data for the non-linear converter. Preferably, the 5-bit index value is decoded into a 20-bit decoded data by the decoder.

6 In addition, the digital filter further includes a register assembly for storing the decoded data. Preferably, the register is assembled from a plurality of flip-flops.

Preferably, the non-linear converter is a non-linear digital-to-analog converter (non-linear DAC).

Preferably, the digital modulator ftirther includes an analog post filter coupled to the non-linear DAC and an FM modulator (voltage controlled oscillator, VCO) coupled to the analog post filter.

A still ftirther object of the present invention is to provide an improved digital modulator. The improved digital modulator includes an input for receiving an input data including a serial bit data and a clock signal, an output for outputting an analog signal converted from the input data corresponding to a filter ftinction, a shift register electrically connected to the input for receiving the serial bit data and storing the serial bit data to generate a binary code, a counter electrically connected to the input for receiving the clock signal and providing a certain number of sampling times, a combined logic circuit electrically connected to the shift register and the counter for receiving the binary code from the shift register and a sampling number from the counter and generating an index value corresponding to the binary code and the sampling nuinber, a decoder electrically connected to the combined logic circuit for decoding the index value to a decoded data with a specific bit, and a non-linear converter electrically connected to the decoder for converting the decoded data to the analog signal.

In order to accomplish the objects of the present invention, a digital filter and a non-linear converter are employed to perform a convolution 7 operation between the input data and a filter ftinction. The digital filter utilizes a combined logic circuit to generate the filter ftinction. The digital filter stores the serial bit data to generate a binary code, obtains an index value corresponding to the binary code and a sampling number, and decodes the index value to generate a decoded data. Then, the non-linear converter converts the decoded data to the analog signal.

The present invention may best be understood through the following description with reference to the accompanying drawings, in which:

BRIEF DESCRIPTION OF TBE DRAWINGS

Fig. I is a schernatic diagram illustrating a conventional quadrature modulator; Fig. 2 is a schematic diagram illustrating a conventional GFSK transmitter based on FM scheme; Fig. 3 illustrates the pulse shaping filter of Fig. 2 in detail; Fig. 4 is a graph illustrating a unit pulse response of a Gaussian low- pass filter for BbT=0.5 in accordance with one embodiment of the present invention; Fig. 5 shows eight possible frequency variation trajectories corresponding to the variety of transmitting data bits in accordance with one embodiment of the present invention; Figs. 6 (a) and (b) are graphs showing overlapped eight possible ftequency variation trajectories for a GLPF having 68 output levels and 30 output levels, respectively; Figs. 7 (a) and (b) illustrate GLPF output levels and 30 output levels for Fig. 6(a) and Fig. 6(b), respectively; and 8 Fig. 8 is a block diagram of the digital modulator in accordance with one embodiment of the present invention.

DETAILED DESCRIPTION OF THE PR-EFERRED EMBODIMIENTS

The present invention will now be described more specifically with 5 reference to the following embodirnents. It is to be noted that the following descriptions of preferred embodirnents of this invention are presented herein for purpose of illustration and description only; it is not intended to be exhaustive or to be limited to the precise form disclosed.

The first straight forward digital iMplementation:

Fig. 4 is a graph of a unit pulse response g(t) versus t/T for BJ=0.5 that is employed in one embodiment of the present invention, where T is one bit period. The parameter BbT is used to define a particular type of GLPF. Since the unit pulse response extends to approximately 3-bit periods, the effect of the unit pulse response over these 3-bit periods must be accounted for. The signal b(t) will suffer firom intersymbol interface (ISI) due to adjacent transmitting data symbols, i.e., during a specific bit period, the b(t) signal results from three input data (a current transmitting bit D,,, a previous transmitting bit D,, and a next transmitting bit D,,+J.

The current, previous, and next transmitting data symbols or bits can be grouped together to form a binary code (Dn-1, Dii, Dn+l), where, the bit Dn-1 is the MSB and DnA is the MB. This code is referred to as the transmitting pattern number. The transmitting pattern number is ranged from 0 to 7 for data symbol with a binary positive polarity level, i.e., Di = 1 or 0. The b(t) signal corresponding to the variety of the transmitting pattern number is referred to as the frequency variation trajectory. Each 9 transmitting pattern number has a corresponding frequency variation trajectory or pulse response (i.e., a corresponding b(t) signal To reduce the number of GLPF output levels:

Fig. 5 illustrates 8 possible frequency variation trajectories and the 5 corresponding transmitting data numbers denoted in the graph as "Tx Pattern No.". The unit for the X-axis is the sampling number during a bit period. In this example, the sampling rate is 12/T.

As the 8 possible frequency variation trajectories are overlapped, it is noted that the trajectories are symmetric about the X-axis. Fig. 6(a) shows the overlapped frequency variation trajectories. The points denoted by a mark ",o" are the output values of the GLPF operating at 12/T frequency. Among these possible GLPF output values, there are 68 distinct values that are plotted in Fig. 7(a) and denoted by a mark "o". However, within a tolerance, some values in neighbor can be merged to a specific value which the following DAC can support. Once the number of GLPF output is reduced, a loose specification of DAC is enough. In this application, 30 levels of GUF output values are obtained from the original 68 levels. The modified GLPF output values are plotted by the mark ",o" in Fig. 7(b). The overlapped frequency variation trajectgries corresponding to the modified GUF output values are shown in Fig. 6(b).

To find the relationship between the GUF output and the transmitting data bits:

The modified GUF output values in ascending order correspond to an index value from 1 to 30. Thus, every point of the frequency variation trajectories of GLPF can be represented by the corresponding index number. It is possible to list the relationship between the transmitting data bits and the GLPF output values which correspond to an index value at every sampling time. This relationship is shown in Table 1.

Implementation of GLPF:

Fig. 8 is a block diagram illustrating the digital modulator configured in accordance with one embodiment of the present invention. The design of GLPF is based on the data listed in Table I and Fig. 7(b). The GLPF can be implemented by a counter 811, a shift register 815, a combined logic circuit 812, a decoder 813, and a flip-flop 814. The counter 811 includes an input for receiving a clock signal (CLK) and correspondingly providing the sampling number as shown in Table 1. A 3-stage shift register 815 is used to store the transmitting bit data which will be effective to the GLPF output during the current bit interval. Depending on the applications, transmitted data Di can be data provided from a personal computer (PC) or sampled voice signal from a speaker.

The combined logic circuit will provide the GLPF output corresponding to the effective transmitting data bits (contents of the 3 stage sla register) and the sampling time (counter value). Basically, the Gaussian low-pass filter 81 receives and stores 3-bit binary code (B4, B5, B6) in the 3-stage shift register 815. The combined logic circuit 812 Will output an index value YI corresponding to the binary codes (134, B5, B6) in accordance with the counting value of the counter 711 during one bit period. Since the maximum index value is 30, 5 bits are enough to represent the index values.

11 Transmitting Data Sampling No During. A Bit Interval Bits Dn-1 Dn Dn+l 1 2 3 4 5 6 7 8 9 10 11 12 0 0 0 (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) 0 0 1 (1) (1) (2) (3) (4) (5) (6) (8) (10) (12) (14) (15) 0 1 0 1(16) (17) (18) (20) (22) (24) (24) (22) (20) (18) (17) (16) 0 1 1 1(16) (17) (19) (21) (23) (25) (26) (27) (28) (29) (30) (30) 1 0 0 1(15) (14) (12) (10) (8) (6) (5) (4) (3) (2) (1) (1) 1 0 1 1(15) (14) (13) (11) (9) (7) (7) (9) (11) (13) (14) (15) 1 1 0 (30) (30) (29) (28) (27) (26) (25) (23) (21) (19) (17) (16) 1 1 1 (30) (30) (30) (30) (30) (30) (30) (30) (30) (30) (30) (30) CJ -1 Table 1

The output index value yl has to correspond to the Gaussian lowpass filter value of Fig. 7(b). Referring to Fig 7(b), it is noted that the distribution of the output values of the GLPF is not uniforin (i.e., nonlinear). Accordingly, the present invention utilizes a non-linear DAC 82 with finite levels to simplify the iinplementation of the modulator, So, a decoder 813 and a flip-flop 814 are eniployed to decode the 5-bit index value yl to 20-bit decoded data y3. The decoder 813 will convert the index values to the required control bits of finite levels DAC 82. The flipflop is required to avoid transient ambiguities (glitch effect) to the DAC 82 when the index value transition occurs.

Each bit of the decoded data y3 corresponds to an analog output value. As a result, it is possible to output a Gaussian low-pass filter ftinction corresponding to the index value yl and thus the desired analog signal b(t). Finally, the output analog signal is generally outputted to a frequency-modulated modulator 84 (FM modulator) through a low-pass filter 83. The modulated signal s(t) is a high-frequency signal that is suitable for transinission.

The algorithin of the combined logic circuit can be designed according to Table I and Fig. 7(b). The cominonly used design tools includes design software such as Cadence Verilog, etc., which is well known to those skilled in the art and will not be described in detail.

Furthermore, the BbT paranieter can be changed to other desired values instead of 0.5 illustrated in above descriptions. Of course, the unit response of Gaussian low-pass filter as shown in Fig. 4 and the corresponding frequency variation trajectories as shown in Fig. 5 will be adjusted along with the changed BbT value.

Thus, the present invention is characterized in utilizing a combined logic circuit and a non-linear converter to design a digital filter and achieve a function of simplifying the volume of a chip. Moreover, the present invention can reduce the cost as compared to conventional 5 techniques.

VAiile the invention has been described in terins of what are presently considered to be the most practical and preferred embodiinents, it is to be understood that the invention needs not be limited to the disclosed embodiment. On the contrary, it is intended to cover various modifications and similar arrangements included within the spirit and scope of the appended claims which are to be accorded with the broadest interpretation so as to encompass all such modifications and similar structures.

1 1 q-

Claims

WHAT IS CLAINMD IS:

1. A digital modulator having an input for receiving a serial bit data and an output for outputting an analog signal converted from said serial bit data corresponding to a filter ftinction, comprising:

a digital filter utilizing a combined logic circuit to generate said filter ftinction, storing said serial bit data to generate a binary code, obtaining an index value corresponding to said binary code, and decoding said index value to generate a decoded data; and a non-linear converter electrically connected to said digital filter for converting said decoded data to said analog signal.

2. The digital modulator according to clairn I wherein said filter ftinction is a Gaussian filter ftinction.

3. The digital modulator according to claim 2 wherein said Gaussian filter ftuiction is a Gaussian low-pass filter function.

4. The digital modulator according to claim I wherein said digital filter is a digital Gaussian low-pass filter (GLPF).

5. The digital modulator according to clairn I wherein said digital filter ffirther includes:

a counter electrically connected to said input and said combined logic circuit for receiving a clock signal and generating a certain number of sarnplMg times during one bit period; a shift register electrically connected to said input and said combined logic circuit for receiving said serial bit data and storing said serial bit data to generate said binary code to be transmitted to said combined logic circuit; and 1 ":) a decoder electrically connected to said combined logic circuit for decoding said index value to generate said decoded data.

6. The digital modulator according to claim 5 wherein said counter provides 12 sampling times during said bit period for said combined logic circuit to generate 12 said index values during said bit period.

7. The digital modulator according to claim 6 wherein said counter is a 4 bit interpolation counter with a modulus of 12(N=12).

8. The digital modulator according to claim 5 wherein said shift register is a 3-bit shift register for storing 3 bits said serial bit data therein and providing a 3-bit binary code based on said serial bit data to said combined logic circuit.

9. The digital modulator according to claim 5 wherein said combined logic circuit provides said index value to said non-linear converter corresponding to said binary code and said sampling time

10. The digital modulator according to claim 9 wherein said index value is a 5-bit index value having 30 different levels.

11. The digital modulator according to claim 10 wherein said decoder decodes said 5-bit index value to a required control bits decoded data for said non-linear converter.

12. The digital modulator according to claim 11 wherein said 5-bit index value is decoded mto a 20-bit decoded data by said decoder. 1

13. The digital modulator according to claim 5 wherein said digital filter ftirther includes a register assembly for storing said decoded data.

14. The digital modulator according to clann 6 wherein said register is assembled from a plurality of flip-flops.

p ( ( 4,

15. The digital modulator according to claim I wherein said non-linear converter is a non-linear digital-to-analog converter (non-linear DAC).

16. The digital modulator according to claim I wherein said digital modulator further includes an analog post filter coupled to said non- linear 5 converter (non-linear DAC).

17. The digital modulator according to clairn 16 wherein said digital modulator further includes a frequency- modulated modulator (FM modulator) coupled to said analog post filter.

18. A digital modulator having an input for receiving an input data including a serial bit data and a clock signal and an output for outputting an analog signal converted from said input data corresponding to a filter function, cornprising: a shift register electrically connected to said input for receiving and storing said serial bit data to generate a binary code; a counter electrically connected to said input for receiving said clock signal and providing a certain number of sainpling times; a combined logic circuit electrically connected to said shift register and said counter for receiving said binary code from said shift register and a sampling number from said counter and generating an index value corresponding to said binary code and said sampling nurtiber; a decoder electrically connected to said combined logic circult'for decoding said index value to a decoded data with a specific bits; and a non-linear converter electrically connected to said decoder for converting said decoded data to said analog signal.

19. The digital modulator according to claim 18 wherein said digital modulator further includes a flip-flop assembly electrically connected 17