GB2351194A - Voltage controlled oscillator - Google Patents

Abstract

A dual voltage controlled oscillator ("VCO") (5) suitable for use in clock and data recovery ("CDR") systems operating at 100s to 1.000s of MB/sec has variable delay cells (10) controlled by a modulation current; the modulation current is generated (16) from a combination of a direct current and a bang/bang modulation current (150/151), the ratio of the direct current and the bang/bang modulation current being determined by a ratio of resistors.

Description

2351194 VOLIA-M COMMUM The present relates to a method of controlling a

voltage controlled oscillator and in particular the bang/bang frequency of such an oscillator.

British patent application no. 9723930.5, of which this is a divisional application, covers a two mput voltage controlled oscillator as described herein.

In modem digital communications systems, the receiver must have a clock and data recovery ("CDR") system to decode and decipher data. Two standards for data transmission at bit rates ranging from I 00s of M[B/sec to more than I GB/sec make particular demands on the CDR system. These standards are SONET/SDH at 155 and 622 MB/sec and Fibre-Channel at 531.25 and 1062.5 MB/sec.

Earlier CDR systems have been implemented with surface acoustic wave("SAW") technology, which is difficult to use in integrated circuits("IC"s) and the resultant CDRs are therefore expensive. Recently, phase lock loop("PLL") designs have substantially reduced the cost of CDR systems. All PLL systems have a phase detector, some type of loop filter, and a voltage controlled oscillator("VCO").

For SONET/SDH data transufission environments, strict specifications are imposed on the CDR system in terms of jitter performance, including specified levels of jitter transfer, jitter tolerance, and jitter generation. These terms are defuried in The International Telegraph and Telephone Consultative Committee Recommendation G.958, "Digital Line Systems Based On The Synchronous Digital Hierarchy For Use On Optical Fibre Cables", incorporated herein for all purposes. With jitter transfer and jitter tolerance, the comer frequencies of phase modulation at the input of the CDR system are defined, and are directly related to the behavior of the PLL.

One known PLL architecture that has been successful in CDR systems operating at bit rates exceeding I GB/sec uses a special VCO. This architecture combines part of the loop filter function with the VCO by feeding the phase detector output directly into a "bang/bang" input of the VCO. A dual input VCO is therefore required. The first input is the commonly known analog voltage input, upon which analog voltage the VCO output frequency is monotonically dependent. The second input is a digital signal input. Depending upon a logic high or logic low signal, the VCO's output frequency alternates between two small but distinct "bang/bang" frequencies. This architecture stabilizes the overall PLL, provided that the phase change due to 2 the bang/bang frequency loop is larger than the phase change introduced by the loop filter.

In one known dual input VCO CDR system, the VCO is realized as a ring oscillator consisting of three variable delay cells and a bang/bang modulation delay cell. The variable delay cell interpolates between two paths, each path having a different delay. The bang/bang delay is achieved by modulating the bias current of an inverting gain stage biased below the peak fTcurrent.

This first known design has been improved by embedding the bangibang control within the variable delay cell, which provides the VCO with a larger frequency range.

In both known designs, the bang/bang delay is dependent on the inherent delays of inverters. This makes the bang/bang frequency sensitive to the process, temperature, and supply voltage variations inherent in the fabrication and operation of inverters. In known application, the bang/bang frequency is simply designed large enough to provide loop stability with ample margin.

Unfortunately, these two approaches do not give enough control over the bangfbang frequency to comply with strict SONET/SDH jitter requireme nts. The dual loop PLL CDR system can be adapted to meet the SONET/SDH jitter requirements provided that the bang/bang frequency of the VCO can be set with precision and then remain constant over temperature and supply voltage variations. The bang/bang frequency directly determines the jitter transfer and jitter tolerance comer frequencies and must be set to meet the corresponding SONETISDH requirements.

According to the present invention there is provided a method of controlling the bang/bang frequency in a voltage controlled oscillator which includes a plurality of variable delay cells coupled together in a ring configuration, the oscillator having a predetermined center operating frequency and a bang/bang signal input for shifting the center operating frequency up and down by a predefined bangibang frequency, the method comprising the steps of: controlling the delay time through the variable delay cells by means of a modulation current; and generating the modulation current from a combination of a direct current and a bang/bang modulation current, the ratio of the direct current and the bang/bang modulation current being determined by a ratio of resistors.

3 British patent application no. 9723930.5 covers a two input voltage controlled oscillator, the first input comprising an analog signal for adjusting the voltage controlled oscillator's output frequency around a predefined center output frequency and the second input comprising a digital signal which switches the voltage controlled oscillator's center output frequency between two bang/bang frequencies, wherein the time difference between the periods of the two bang/bang frequencies, is a constant fraction which is independent of the voltage controlled oscillator's supply voltage variations, its operating temperature variations, and its process variations.

The first preferred dual input VCO has sufficiently precise control over the bang/bang frequency to meet SONET/SDH jitter requirements. The VCO comprises a plurality of variable delay cells and bangibang modulation circuits. A first input to the VCO is an analog voltage signal which monotonically adjusts the VCO output frequency. The VCO's output frequency is called herein the operating frequency. A second input is a digital baxig/bang signal which modulates the VCO's operating frequency between rwo slightly different frequencies. The difference of the periods of the two bangy/bang 4 frequencies (bang/bang time) is a fixed fraction Of the W0's-operating frequency. When the VCO is used in a PLL, which PLL is locked onto a data steam of a fixed bit rate, the bang time becomes a constant ratio of the bit rate, and is independent of supply voltage, temperature, and process variations.

Fig. 1 is a block diagram of a first embodiment of voltage controlled oscillator; Fig. 2 is a circuit diagram of the variable delay cell shown in Fig. 1; and Fig. 3 is a circuit diagram of the bangibang modulation circuit shown in Fig. 1.

A block diagram of a first embodiment of voltage controlled oscillator is shown in Fig. 1. Dual input VCO 5 comprises N identical variable delay cells 10 connected in a ring oscillator configuration. In the first preferred embodiment, four delay cells 10 are used. Variable delay cel Is 10 each have an analog differential voltage V, input 12 and a digital unitary bang/bang modulation input 110. Cells 10 additionally have a differential V,,, input and a differential V,,, output. Bang/bang modulation input 110 is provided by bang/bang modulation circuits 16. The signals at the outputs of the cells could be tapped and buffered to provide the VCO outputs with different phases.

The delay of each delay cell 10 is determined by its controlling voltage. In this first embodiment, TJTd. + Wj,, where Td. is the delay when VjO, Vc is a differential analog controlling voltage, k is a factor in see/(volt-amp), and 1.. is the modulation current. As shown in Fig. 2, 1 has two components: l.= o + 'bb. where 1, is a DC current and 'bb is the bangg current controlled with a BB digital input 150 and 15 1 (see Fig. 3), with 'bb "" < 1, As shown in Fig. 1, one period P of the ring oscillator of delay cells 10 consists of two trips around the ring, with P=2riTjP,,+2rikV, do. 'bb 'S Purp 9+ibb), where Po =2nT osely made a fixed fraction mOf 1.. Or 'bb=+'-MI. Sothat P=P.+2nW.1.(1 +/- m). P can therefore be represented by two components: P=T+/-.5Ttbwhere T.=P,+ (2rikVj.), which is the nominal delay, and Tbb=(4nWcl.)m, which is the bang/bang time. For m<< 1, TjP and TbbTrnp.

When a PLL using the VCO described herein is locked onto an incoming data stream with a defined data rate, period P is a constant. Controlling voltage V, is continuously adjusted by the PLL to achieve and maintain this lock. With this, Tbb is defined only by a constant bit rate and the factor m, which is designed to be a ratio of resistors. The bang/bang frequency is simply the frequency corresponding to the difference between the two periods, with Fbb[ 1 /(TO+Tbv2)][1/(TO-Tbb/2)]. With Tbbthus defined and compensated for, the purpose of the present invention with regard to the stability of Fbbis achieved, Fig. 2 is a circuit diagram of variable delay cell 10. Identical transistors 50 and 51 and identical resistors 52 and 53 form the basic switching element. Inputs 60 and 6 1, together called V,,,, are fed into the bases of transistors 50 and 5 1, respectively, and the voltages at the collectors of transistors 50 and 51 are buffered by identical transistors 70 and 71, respectively, to provide outputs 80 and 8 1, together called V., The emitters of transistors 50 and 5 1 are driven from a current source provided by the collector of transistor 55 and resistor 58.

Nodes 56 and 57 have identical capacitive loads 72 and 73. Thus, these nodes generate time delays directly related to their voltage swings. V,c and V,, are DC voltages supplied to power delay cell 10 and Vc , is a DC voltage supplied to turn on the various current sources. These current sources include transistor 82 and resistor 83 and transistor 84 and resistor 85, which respectively act as current sources for transistors 70 and 7 1.

The delay modulation is controlled by transistors 90 and 91 and the variable current source provided by transistors 93, 94, 95, and 96 and resistors 97 and 98. Resistors 97 and 98 are identical. Transistors 90 and 91 are configured to retard the switching action of transistors 50 and 5 1. The controlling current In modulates the voltage swings of nodes 56 and 57, thereby controlling the delay.

Vc inputs 100 and 10 1 feed into the bases of transistors 94 and 93, respectively. These two transistors form a current steering circuit that defines the modulation current I,,,. The nominal current available to the steering circuit is provided by two current sources comprised of transistor 95 and resistor 103 and transistor 96 and resistor 104. Resistors 103 and 104 are identical. Together these current sources sum up to DC current 1,, and a trickle current through resistor 105. This trickle current through resistor 105 is digitally modulated by the bang/bang 6 input 110, which is driven by bang/bang modulation circuit 16, described below. This bang/bang modulation results in a delta current ibbappearing in the trickle current flowing through resistor 105. The DC component of the trickle current is designed to be much less than I. and can be ignored.

As previously stated, l.=1,+ibb. This current is steered by Vc, the voltage between nodes and 10 1 which forms the analog differential control input to the WO, which is applied across transistors 93 and 94, and modulates the delay between V,,, and V"u, through the cell.

Thus, Td=Td.+kVj,, where T,,. is the delay when Vc =0, V. is the analog controlling voltage, 1,, is the modulation current, and k is a factor in secl(volt-amp), which is a function of the load - resistance, capacitance, and process variables.

Fig. 3 is a circuit diagram of bang/bang modulation circuit 16. Differential digital inputs 150 and 15 1 ("BB") are coupled to the bases of transistors 152 and 153, respectively. Load resistors 154 and 155 are coupled from V,,, to the collector of transistor 152. The emitters of transistors 153 and 152 are coupled to the collector of transistor 156, which enables the bias current to activate the bang/bang function. When the disable input (1601161) is a logic 0, then the voltage at node 176 will toggle dependant on bang/bang inputs 150 and 15 1. The high and low levels at node 176 are V. - LO, ivithVLO equal to 1,(R154+RI55). Whenthe ,, and Vcc V disable input (1601161) is a logic high, as activated by signal lines 160 and 161, node 176 will have a D.C. value at Vc -1,R154, or 1/2(high level+low level). The states of transistors 156 and c 157 are set by the disable inputs 160 and 16 1, which inputs are level shifted by transistors 162 and 163. Together, transistors 156 and 157 act as a current switch. The emitters of transistors 156 and 157 are driven by a current source comprising transistor 165 and resistor 166. Three current sources, each comprised of a transistor and resistor, provide bias current to transistors 162, 163, and 173. Respectively, these current sources are transistor 169 and resistor 170, transistor 167 and resistor 168, and transistor 171 and resistor 172. Vcs is applied to each of these current sources, as well as the current source formed by transistor 165 and resistor 166. As in Fig. 2, V,, and V.

,. are the bang/bang modulation circuiCs power supplies.

The delta current ibbis a function of the voltage swing at the emitter output of transistor 7 173 (node 110), which follows the voltage swing at node 176. When node 176 is in its high state, then ibt, will have a negative polarity. When node 176 is in its low state, ibb will be positive. The amplitude of 'bb is V2of the voltage swing at node 176 divided by resistor 105. The dc component through R 105 is small compared to 1,, and can be ignored.

From Fig. 2, the voltage swing at node 176 is calculated to be I,defined as V. -V of cS be transistor 165, divided by resistor 166, multiplied by the load resistors RI 54 and RI 55. T'hus, 'bb is.5 (V,..,-VbJ/l66(RI54 + R155).

From Fig. 3, the D.C. current I. is defined by the currents of transistors 95 and 96, or 1,, =2 (V,,-Vb,)/RI03. The value of R103 is equal to thevalue of R104. Comparing 'bb to',,, and remembering that Vb, between transistors fabricated on the same die can be made to match very closely, the result is that iw/I,,=.5(V.-Vb, )/R166 R105) (RI54+RI55) divided by2(V,,.,- Vbr )/RI03, or ibWI.=.5Rl03(RI54 + R155)divided by 2 (R166 R105) = rn. These calculations show that 'bbis related to 1. by a factor in defined by a ratio of resistors, which resistors can be fabricated with great precision and repeatability.

In the first preferred embodiment, the bit rate is set to 622.08 MB/sec, which is defined to be OC- 12 by Sonet, or STM4 by SDH standards. The VCO comprises four identical stages. The bang/bang time is set to 0.60 pS/c ycl, to conform to the corresponding jitter transfer and jitter comer frequency tolerances. The VCO center operating frequency when V,=O is 621. 08 MHz and the bang/bang frequency is 0.037% of the center frequency or 232 KHz.

The present invention has several advantages over the known ar-L As the bang/bang frequency is defined by a ratio of resistors and the bit rate, the bang/bang frequency of the VCO is independent of environmental variations. With this compensation, the present invention's dual I oop PLL architecture can conform to the jitter tolerance and jitter transfer comer frequency requirements of SONET/SDH.

As the bangibang frequency is well controlled, the margin of stability for the dual loop PLL architecture is assured despite process and environmental variations. These benefits are not limited to only SONET/SDH applications, but are available at any bit rate.

Compared with previous CDR designs based on 2 path interpolation, the new variable 8 delay cell requires fewer circuit elements and consumes less power. The delay cell taught herein can achieve wider delay variations than the two earlier described known designs, resulting in a wider frequency range for the present invention's VCO.

The disable mode incorporated to disable the bang/bang behaviour of the VCO, which then reverts to a traditional single input analog controlled VCO, allows the PLL to let the VCO operate undisturbed as long bit streams of ones or zeroes are present. preventing the VCO from drifting off.

There is also provided a two input voltage oscillator 5. the first input 12 comprising an analog signal for adjusting the voltage controlled oscillators output frequency around a predefined center output frequency and the second input 110 comprising a digital signal which switches the voltage controlled oscillator's center output frequency between two bang/bang frequencies. wherein the time difference between the periods of the two bang/bang frequencies. divided by the period defined by the voltage controlled oscillator's operating frequency. is a constant fraction which is independent of the voltage controlled oscillator's supply voltage variations, its operating temperature variations, and its process variations.

The oscillator may also comprise a plurality of variable delay cells 10. each delay cell 10 having a first input and a first output, the first output of each variable delay cell coupled to a first input of a succeeding variable delay cell, the plurality of variable delay cells 10 thereby forming a ring, an odd number of variable delay cells having their first output inverted before the first output is coupled to a succeeding variable delay cell, each variable delay cell further comprising an analog signal input 12 for receiving the analog signal and a bang/bang signal input 110 for receiving a bang/bang signal-, and a plurality of bangibang modulators 16, each bang/bang modulator providing the bang/bang signal to a respective variable delay cell. each bangibang modulator having a disable signal input 160, 14 for receiving a disable signal and a digital signal input 150, 151 for receiving the first digital signal.

The total delay of the ring of variable delay cells may be determined by a modulation current, the modulation current having a first predetermined direct current component and a second bang/bang current component provided by the bang/bang signal from the bang/bang modulators.

9 The ratio of the bangfbang current component and the direct current component of the modulation current may be defined by a ratio of resistors in the variable delay cells and the bang/bang modulators.

Claims (2)

1. A method of controlling the bang/bang frequency in a voltage controlled oscillator which includes a plurality of variable delay cells coupled together in a ring configuration, the oscillator having a predetermined center operating frequency and a bang/bang signal input for shifting the center operating frequency up and down by a predefined bang/bang frequency, the method comprising the steps of: controlling the delay time through the variable delay cells by means of a modulation current; and generating the modulation current from a combination of a direct current and a bang/bang modulation current, the ratio of the direct current and the bang/bang modulation current being determined by a ratio of resistors.

2. A method of controlling a voltage controlled oscillator substantially as herein described with reference to each of the accompanying drawings.