GB2350467A

GB2350467A - Active matrix liquid crystal display

Info

Publication number: GB2350467A
Application number: GB0020848A
Authority: GB
Inventors: Chang-Wook Han; Kyoung Nam Lim; Byung-Chul An; Jeong Hyun Kim; Ki-Hyun Lyu
Original assignee: LG Electronics Inc
Current assignee: LG Electronics Inc
Priority date: 1996-05-23
Filing date: 1997-05-22
Publication date: 2000-11-29
Anticipated expiration: 2017-05-22
Also published as: GB0020848D0; GB2350467B

Abstract

An active matrix liquid crystal display includes gate bus lines (117) and gate electrodes (107) formed on a substrate (110). A gate insulating layer (109), a semiconductor layer (111) and an ohmic contact layer (112) are sequentially formed upon the gate bus lines, electrodes and substrate. Source electrodes (105), drain electrodes (106) and storage capacitor electrodes (130) are then formed on the ohmic contact layer, and are used as etching masks to etch the ohmic contact layer. An insulating passivation layer (113a) is deposited so as to cover all previously deposited layers, and is etched along with the semiconductor layer and the gate insulating layer so that the edges of these three layers are substantially aligned.

Description

2350467 ACTIVE MATRIX LIQUID CRYSTAL DISPLAY AND METHOD OF MAKING THE SAME

The present invention relates to a method for manufacturing an active matrix liquid crystal display ("AMLCD"), and to a structure of the AMLCD manufactured by such a method.

In general as depicted in Figures 1 and 2, the AMILCD comprises a substrate ("first substrate") 3 on which a plurality of pixel electrodes 4 are arrayed in a matrix form. Each pixel electrode 4 on the first substrate 3 is bounded by two gate bus lines 17 and two source bus lines 15, each gate bus line 17 being perpendicular with each source bus line 15. The gate bus lines 17 are horizontally formed, and a plurality of gate electrodes 7 perpendicularly branch out from the gate bus lines 17. The source bus lines are vertically formed, and a plurality ofsource electrodes 5 perpendicularly branch out from the source bus lines 15.

Thin film transistors (TFTs) are formed near the crossing points of the gate bus lines 17 and the source bus lines 15 and are electrically connected with the pixel electrodes 4. An alignment film (not depicted) which sets the initial orientation of liquid crystal is formed on the TFTS and the pixel electrodes 4.

The A-MICD also comprises another substrate ( "second substrate") 2 on which a color f ilter layer (not depicted), common electrodes (not depicted) and an alignment film (not depicted) are formed. The first and second substrates 3 and 2 are joined facing each other, and liquid crystal is injected into the space between the alignment films of the first and second substrates 3 and 2. The first and second substrates 3 and 2 have polarizing films 1A and 1B on their outer sides. The A.MLk--D is manufactured by combining the above mentioned constituents.

2 Having the above mentioned constituents, a conventional method for manufacturing a first substrate is described below with reference to the drawings.

As shown in Figure 3A, a Cr layer is deposited on a transparent glass substrate 10. A photo--resist is coated on the Cr layer and the photo-resist is developed into a desired pattern by using a mask. A gate bus line 17 and a gate electrode 7 which is branched out from the gate bus line 17, are formed by etching a portion of the Cr layer along the developed pattern of the photo-resist (Figure 3A)-. Afterward, a SiN. film (from which a gate insulating layer 9 is formed later), an amorphous silicon ("a-Si") film (from which a semiconductor layer 11 is formed later) and an n a-Si film (from which an ohmic contact layer 12 is formed later) are sequentially deposited on the substrate including the patterned Cr layer (Figure 3B).

Subsequently, a photo-resist is coated on the n' a-Si film and the photoresist is developed into a desired pattern by using a mask. An ohmic contact layer 12 and the semiconductor layer 11 are formed by' etching the n' a-Si film and the a- Si film at the same time along the developed pattern of the photo-resist (Figure 3C).

Then, Cr is deposited by sputtering on the surface covering the gate insulating layer 9, the ohmic contact layer 12 and the semiconductor layer 11. A photo-resist is coated on the Cr layer and the photo-resist is developed into a desired pattern by using a mask. A source bus line 15 (functioning as a signal line), a source electrode 5 (which branches out from the source bus line 15) and a drain electrode 6 (functioning as an output electrode) are formed by etching the Cr layer along the developed pattern of the photo-resist. The middle of the olunic contact layer 12 is etched by using the source and drain electrodes as etching masks, so that the ohmic contact layer 12 is separated into two parts (Figure 3D).

Thereafter, a passivation layer 13 is coated on the surface covering the gate insulating layer 9, the source bus 3 line 15, the source electrode 5, the drain electrode 6, the ohmic contact layer 12 and the semiconductor layer 11. A photo-resist is coated on the passivation layer 13 and the photo-resist is developed into a desired pattern by using a mask. A contact hole 16 is formed in a portion of the passivation layer 13 on the drain electrode by etching the passivation layer 13 along the developed pattern (Figure 3E).

An ITO (Indium Tin Oxide) layer is formed by sputtering onto the passivation layer 13 and the drain electrode 6 (at the contact hole). A photo-resist is coated on the ITO layer and the photo-resist is developed into a desired pattern by using a mask. A pixel electrode 4 is formed by etching the ITO layer along the developed pattern of the photo-resist (Figure 3F).

As described above, in the conventional method for manufacturing the AMLCDs, the patterning process needs to be used five times in order to manufacture the first substrate including the pixel electrode 4.

-20 The patterning process comprises the steps of depositing a film on a substrate and rinsing the surface of the film, coating a photo-resist on the rinsed surface of the film, exposing and developing the photo-resist by using a mask, etching the film along the developed pattern of the photo-resist and removing the photo-resist on the patterned film.

As described above, the patterning process is not only complicated but also takes much time and results in relatively high rate of defects. Accordingly, if possible, it is preferable to reduce the number of the patterning processes because defects are increased in proportion to the number of patterning processes.

Furthermore, as shown in Fig. 3F, level -dif f erences e, non-planar portions) exist in the- completed TFT - As a result, defects during a subsequent rubbing operation can occur.

4 One object of the present invention is to provide a method for fabricating an active matrix liquid crystal display having a minimal number of masking steps.._._ An 9 t-h-e-r object of the present invention is to provide an active matrix liquid crystal display panel with a reduced number of rubbing defects.

According to one aspect of the present invention, there is provided a method for manufacturing an active matrix liquid crystal display comprising the steps of: forming gate bus lines and gate electrodes on a substrate; forming a gate insulating layer on the surface covering said gate bus lines, said gate electrodes and said substrate; forming a semiconductor layer on said gate insulating layer; forming an ohmic cotact layer on said semiconductor layer; forming source bus lines, source electrodes and drain electrodes on said ohinic contact layer; etching said ohmic contact layer by'using said source electrodes and said drain electrodes as an etching mask; forming a passivation layer on the surface covering said source bus lines, said drain electrodes, said semiconductor layer and said gate insulating layer; forming a second passivation layer over said substrate; selectively removing said passivation layer to form contact holes which expose said drain electrodes; and forming pixel electrodes in contact with said drain electrodes via said contact holes.

According to another aspect of the present invention, there is provided an active matrix liquid crystaL-. display (AMLCD) comprising: a substrate; gate bus lines and gate electrodes formed on said substrate; a gate insulating layer formed on said substrate, said gate bus lines and said gate electrodes; a semiconductor layer formed on said gate insulating layer; an ohmic contact layer formed on said semiconductor layer; source bus lines, source electrodes, and drain electrodes formed on said ohmic contact layer; a first passivation layer covering said semiconductor layer, said source bus lines, said source electrodes and said drain electrcdes; a second passivation layer covering said first passivation layer and said substrate, and said first and second passivation layers having contact holes formed therein to expose said drain electrodes; and pixel --,-electrodes formed on at least said drain electrodes.

The foregoing and other objectives of the present invention will become more apparent from the detailed description given hereinafter. However, it should be understood that the detailed description and specific examples, while indicating preferred embodiments of the invention, are given by way of illustration only, since various changes and modifications within the spirit and scope of the invention will become apparent to those skilled in the art from this detailed description.

For a better understanLng of the present invention embodiments will now be described by way of example, with reference to the accompa'hying drawings in which:

Figure 1 is a three-dimensional delineation showing a part of a conventional AMLCD; Figure 2 is a_ plan view showing a part of the conventional AMLCD; Figures 3A to 3F are diagrammatic cross-sectional views showing the manufacturing process of the conventional AMLCD, taken along III-III of Figure 2; Figure 4 is a plan view showing a part of an A1MLCD according to the present invention; Figures 5A to 51 are diagrammatic cross-sectional views showing the manufacturing process according to a first exemplary embodiment of the present invention, taken along V-V of Figure 4; and Figures 6A to 6B are diagrammatic cross-sectional views showing the manufacturing process according to a second exemplary embodiment of the present invention, taken along VI-VI of Figure 4.

According to a first exemplary embodiment of the present invention, beginning as shown in Figure 5A, a first metal layer, e.g., Cr, is deposited on a transparent glass substrate 110. A photo- resist is coated on the first metal layer and the photo-resist is developed into a desired pattern by using a mask. The first metal layer is etched by a wet-etching method along the developed pattern of the photo-resist, arid thereby a gate bus line 117 and a gate electrode 107 (which is branched out from the gate bus line 117) are formed (Figure 5A).

Afterwards, a SiN,, film (from which a gate insulating layer 109 is formed later), an a-Si film (from which a semiconductor layer 111 is formed later), an n- a-Si film (from which an ohmic contact layer 112 is formed later) and a Cr layer (from which a second metal layer 140 is formed later) are sequentially deposited (Figure 5B) - Therefore, a photo-resist is coated on the second metal layer 140 and the ph6to-resist is developed into a desired pattern by using a mask. The second metal layer 140 is etched by a wet-etching method along the developed pattern of the photoresist, and thereby the source bus line 115 (functioning as a signal line), the source electrode 105 (which branches out from the source bus line 115), the drain electrode 106 (functioning as an output electrode) and a storage capacitor electrode 130 are formed. The storage capacitor electrcde overlaps a part of the gate bus line 117 (Figure 5C).

Then, the n' a-Si film is etched by using the source bus line 115, the source electrode 105, the drain electrode 106 and the storage capacitor electrode 130 as etching masks, and thereby an ohmic contact layer 112 is formed (Figure 5D).

A first passivation layer 113a, e.g., made of an inorganic insulating material such as SiN, or SiO2, is deposited on the surface covering the semiconductor layer 111, the edges of the ohmic contact layer 112, the source bus line 115, the source electrode 105, the drain electrode 106 and the storage capacitor electrode 130 (Figure 5E).

A photo-resist is coated on the first passivation layer 113a, and the photo-resist is developed by us-ing a mask so that the photo-resist covers a part, of the stcrace caoaci-= electrode II-10, the drain e.'Iectrcde 106, a part of the a-Si 7 1 - ch se.mccr.ductor laY:::: '11 is f the fil-m rrm w.i- source '1.'lus line 1-15 and the s,-urce electrode 10.5 The first cass --,7at--ion layer 113a, the a--ci i!-m, ( f r, m which DT:z - i 1 in r,:)m sem--;:-conductor laver 11-1 is forined) and the S, L_ w h _J c h. the gate insulat-ing- layer 109 15:c=ned) are simultaneously etched by a dry- atching method along the develc-ped pattern of the photo ---as is t, and thereby a!a77e-.- ill and a cate insulating!a-7er 109 are forimed (F-'. aure SF).

Af ter- tion layer 113b is fo=ed ejards, a second passivat--- by coating, e.g., an organic material such as fluorinated polyi.m.ide, fluorinated parylene, teflon (RTM), cytop (RTM), f luarope"L,va--ylether, perfluarocyclobutane (PFCB) or benzacyclobutene (BCB), on the surface c over..A-n the si.:Ccstra--e 110, the edges of the gate insulating layer 109, the edges of the semiconductor layer 111 and the first pass-vation'laye= 113a (Figure SG).

Chemical structux-es for these matetials may be as follows:

W f luc2:2Ana-.ed CO polyimide.: N- Y C71 f!,-,or in a ted 1 71- CF1 C -i- CF _CF - ze-E-'cn (RT.M) J= 0- C -0 i /1, \ i C.7.: --- 1 --- 1 1. (-- i - 8 CytCp (RTIM) - L CF2-CF / (CR)X\ CF- (CR) 1 f luaro- WF -L i - PC Y O- (D arvlether \ FF F J Cb C-L- BCB 1 - ' -1 1 0. G c-;_- 1 MC- &{c In the case that the second passivation layer 113b is formed with an organic material, such as fluorinated polyL-nide, fluorinated parylene, teflon (RTIM), cytop (RTM), f luoropolyary-leth. er, PFCS cr BC3, as described above, level-d-ifference is not formed on the surface of the organic second passivaticn laver 113b when the organic material is coated on any pcrtians hav-ng lelTel-diff-ference such as the source bus line 1!5. the pixel electrode for.-ned on the organic second rass-.'--,7at-;cn Laver 1113b can be formed evs.nly, and defects -in r-ubbincr az the portions having leve-1-d---f- ferance can be reduced.

9 As a result thereof, defects in rubbing at the step of the source bus line 115 do not occur although the pixel electrode is formed to overlap the source bus line 115.

Therefore, the aperture ratio of the liquid crystal display can be improved.

Then, a photo-resist is coated on the second passivation layer 113b and the photo-resist is developed into a desired pattern by using a mask. The second passivation layer 113b and the first passivation layer 113a are etched along the developed pattern of the photo-resist, and thereby contact holes 116 and 116' are f ormed to exposed the drain electrode 106 and the storage capacitor ,lectrode 130 (Figure 5H).

Thereafter, an ITO layer, a transparent conductive layer, is deposited by sputtering an the surface covering the first and second passivation layers 113a and 113b, drain electrode 106 and the storage capacitor electrode 130. A photo-resist is coated on the ITO layer and the photo-resist is developed into a desired pattern by using a mask. The ITO layer is etched along the developed pattern of the photo-resist, and thereby a pixel electrode 104 is formed to be electrically connected with a part of the storage capacitor electrode 130 and a part of the drain electrode 106 (Figure 51).

The manufacturing steps of the second exemplary embodiment of the present invention are the same as the steps of the first exemplary embodiment depicted in Figures 5A to 5E.

In Figure 6A, a photo-resist is coated on the first passivation layer 113a and the photo-resist is developed into a desired pattern by using a mask. The first passivation layer 113a is etched along the developed pattern of the photo-resist, and thereby a contact hole 116 is formed on the drain electrode 106 and a portion of the storage capacitor electrode 130 is exposed (Figure 6A).

Then, an ITO layer, a transparent conductive layer, is deposited on the surface covering the substrate 110, the - edges of the gate insulating layer 109, the edges of the semiconductor layer ill, an edge of the ohmic contact layer 112, the passivation layer 113a and the drain electrode 106. A photo-resist is coated on the ITO layer and the photo-resist is developed into a desired pattern by using a mask. The ITO layer is etched along the developed pattern of the photo-resist, and thereby a pixel electrode 104 is formed to be electrically connected with a' part of the storage capacitor electrode 130 and a part of the drain electrode 106 (Figure 5B).

According to the first and second exemplary embodiments of the present invention, the numbers of the patterning process can be reduced, e.g., from five times in the conventional Figures 3A-3F down to four times in the second exemplary embodiment of the present invention. As a result of this, the defects arising from the patterning process can he reduced, and also the manufacturing yield can be improved.

The invention being thus described, it will be obvious that the same may be varied in many ways. Such variations are not to be rega. rded as a departure from the spirit andil scope of the invention, and all such modifications as would be obvious to one skilled in the art are intended to be included within the scope of the following claims.

This application is a divisional application related to parent application No. GS 9710603.3 (GB 2 313 466). We incorporate herein by reference the subject matter of the parent application as published.

Claims

Claims:

1. A method for manufacturing an active matrix liquid crystal display comprising:

forming gate bus lines and gate electrodes on a substrate; forming a gate insulating layer on said gate bus lines, said gate electrodes and said substrate; forming a semiconductor layer on said gate insulating layer; forming an ohmic contact layer on said semiconductor layer; forming source bus lines, source electrodes and drain electrodes on said ohmic contact layer; forming a passivation layer covering said semiconductor layer, said source bus lines, said source electrodes and said drain electrodes; etching said passivation layer, said semiconductor layer and said gate insulating layer so that the edges thereof are substantially aligned; selectively removing said passivation layer to form contact holes which expose said drain electrodes; and forming pixel electrodes on said drain electrodes and said passivation layer.

2. The method as in claim 1, wherein said step of forming said passivation layer forms said passivation layer from an organic material; and wherein the organic material includes at least one of fluorinated polyimide, fluorinated parylene, polytetrafluoroethylene, fluoropolyarylether, PFCB, BCB and a 12 material having the chemical formula:

CF, CF (C F2), \ (CF--) 7 /!-' I

3. A method as in claim 1 or 2,comprising forming a second passivation layer over said substrate.

4. The method as in claim 3, wherein said steps of forming said gate insulating layer, forming said semiconductor layer, forming said ohmic contact layer, and forming said source bus lines, said source electrodes and said drain electrode comprise: sequentially depositing a material for said gate insulating layer, a material for said semiconductor layer, a material for said ohmic contact layer, and a material for said source bus lines, said source electrodes and said drain electrodes.

5. The method as in claim 4, wherein said step of forming said source bus lines, said source electrodes and said drain electrodes comprises: forming storage capacitor electrodes of storage capacitors on said ohmic contact layer.

6. The method as in claim 3, 4 or 5, wherein said step of forming said step of forming said second passivation layer forms said second passivation layer from an organic material; and wherein the organic material includes at least one of fluorinated polyimide, fluorinated parylene, polytetra- 13 fluoroethylene, fluoropolyarylether, PFCB, BCB and a material having the chemical formula:

CF: CF C F - (C -E-Z) = I -

7. The method as in claim 1 or 2, wherein said step of forming pixel electrodes forms said pixel electrodes on said passivation layer.

8. The method as in claim 3, 4, 5 or 6, wherein said step of forming pixel electrodes forms said pixel electrodes on said second passivation layer.

9. An active matrix liquid crystal display (AMLCD) comprising: a substrate; gate bus lines and gate electrodes formed on said substrate; a gate insulating layer formed on said substrate, said gate bus line and said gate electrodes, a semiconductor layer formed on said gate insulating layer; an ohmic contact layer formed on said semiconductor layer; source bus lines, source electrodes, and drain electrodes formed on said ohmic contact layer; a passivation layer covering said semiconductor layer, said source bus lines, said source electrodes and said drain electrodes, and said passivation layer having contact holes formed therein to expose said drain electrodes; and 14 pixel electrodes formed on said drain electrodes and said passivation layer; wherein the edges of said passivation layer, said semiconductor layer and said gate insulating layer are substantially aligned.

10. The AMCLD as in claim 9, further comprising:

storage electrodes of storage capacitors formed on said ohmic contact layer; and wherein said pixel electrodes are formed on said storage electrodes.

11. The AMLCD as in claim 9 or 10 wherein said passivation layer includes an organic material; and whrein the organic material inlcudes at lesat one of fluorinated polyimide, fluorinated parylene, polytetrafluoroethylene, fluoropolyarylether, PFCB, BCB and a material having the chemical formula:

(CF2) CF- CF (Ca, i is

12. The AMLCD as in claim 9, 10 or 11 comprising a second passivation layer covering said passivation layer and said substrate.

13. The AMLCD as in claim 12, wherein said second passivation layer is an organic material; and wherein the organic material includes at least one of fluorinated polyimide, fluorinated parylene, polytetrafluoroethylene, fluoropolyarylether, PFCB, BCB and a material having the chemical formulae; CF--, CF (C;7,) -Y

14. The AMLCD as in claim 8, 9, 10 or 11 wherein said pixel electrodes are also formed on said passivation layer.

15. The AMLCD as in claim 12 or 13 wherein said pixel electrodes are also formed on said second passivation layer.

16. The method as in any one of claims 1 to 8, or the AMLCD as in any one of claims 9 to 15, wherein said passivation layer includes at least one of the chemical structures illustrated hereinbefore.