GB2324899A - Active matrix display - Google Patents

Abstract

An active matrix light modulator, such as a thresholdless antiferroelectric active matrix liquid crystal display, comprises an active matrix of control elements 18 disposed at intersections of data lines and scan lines, and an array 10 of pixels which are selectively addressable by data and scan signals applied to the control elements 18 by a data driver 12 and a scan driver 14. Such addressing is controlled so that a voltage is applied to each pixel during a corresponding addressing frame by the application of data and scan signals to an associated one of the control elements 18 in order to select the optical level of the pixel for each frame, and bipolar switching is applied to control the voltage applied to the pixel during successive subframes such that, when one optical level is selected for the frame, a positive voltage is applied to the pixel during one subframe of the frame and a negative voltage of equal magnitude but opposite polarity is applied to the pixel during another subframe of the frame and, when another optical level is selected for the frame, an intermediate voltage (preferably zero voltage) is applied to the pixel during both of the subframes of the frame, so as to provide DC balancing within the frame. Because of such DC balancing within each frame, the required grey level within each frame is accurately reproduced and is substantially independent of the previous state of the pixel.

Description

2324899 1 Active Matrix Light ModulatorC This invention relates to active

matrix light modulators and is concerned more particularly, but not exclusively, with active matrix liquid crystal devices, such as antiferroelectric liquid crystal displays (AFLCUs), in which accurately reproducible grey levels can be obtained.

It should be understood that the term "light modulators" is used in this specification to encompass both light transmissive modulators, such as diffractive spatial 10 modulators, and light emissive modulators, such as conventional liquid crystal displays.

AFLCUs and related liquid crystal devices exhibit field tunable, in-plane switching behaviour which is capable of being exploited to provide greyscale and wide viewing angle in both passively driven and active matrix driven devices. Such liquid crystal devices have the property that, when the liquid crystal director switches to a different state in response to an applied transverse DC voltage, the director remains substantially parallel to the boundary plates for all applied switching voltages. Typically, in a transmissive device, the liquid crystal cell is disposed between crossed polarisers arranged such that the maximum dark state of the device is obtained at an applied voltage of zero volts. Such an arrangement typically corresponds to the case in which the alignment directions of the boundary surfaces are substantially parallel to one another and to the transmission axis of one of the two polarisers. On application of a DC 2 voltage of either polarity to the cell, the optic axis of the liquid crystal material is rotated so that it is no longer parallel to the transmission axis of either polariser, and the light transmission of the device is increased.

Alternatively the liquid crystal cell may be arranged between two polarisers arranged with their axes parallel to one another such that the bright state is obtained when a voltage of zero volts is applied. On applying a DC voltage of either polarity to the cell, the device is switched to a darker state. However a switching angle of 45 degrees is required in order to obtain a maximum dark state. Accordingly it is possible for two such cells to be arranged in series between two polarisers having parallel axes such that the device as a whole is in the bright state when a voltage of zero volts is applied to each cell, and such that, when voltages of opposite polarities are applied to the cells, the optic axes of the cells arerotated in opposite directions such that the light transmission of the combined device decreases. When the angle between the two optic axes reaches 45 degrees, the device is in its maximum dark state, so that each cell is required to switch through an angle of only 22.5 degrees to reach the maximum dark state. An equivalent reflective device utilising a single polariser can be formed utilising a single liquid crystal cell and a quarter wave plate disposed between the cell and a reflective surface such that, in the zero voltage state, the optic axis of the cell is parallel to the polariser axis and the axis of the quarter wave plate, and the maximum dark state is reached when the cell is switched to +/- 22.5 degrees.

3 Such devices may be fabricated from antiferroelectric liquid crystal (AFLQ materials, or alternatively from materials exhibiting the deformed helix ferroelectric (DEF) effect, the short pitch bistable ferroelectric (SBF) effect or the electroclinic (EC) effect.

As disclosed by Y. Yamada, N. Yamamoto, M. Yamawaki, 1. Kawamura and Y. Suzuki Proc. Japan Display 1992, p. 57, in relation to a passive AFLCD driving scheme, it is possible to avoid ghosting due to ionic build up in idealised surface stabilised AFLC's by means of a passive addressing arrangement in which the pixels are switched between equal and opposite ferroelectric states +F or -F by the application of positive and negative voltages during successive addressing frames. A sharp voltage threshold must be overcome to switch the AFLC into either of these states, and voltages with magnitudes typically between 20 and 40 volts are required to fully switch the material into the required state. On removal of the applied voltage, the liquid crystal material relaxes to the more stable antiferroelectric (AF) state by way of the corresponding hysteresis curve, as shown in the graph of Figure I a which shows ideal (symmetrical) voltage-transmission characteristics of an AFLC on switching to and from each of the ferroelectric states, where the transn- dssion is denoted byr and the applied voltage is denoted by V. Accordingly a holding voltage must be continuously applied to the AFLC in order to maintain the device in one of the ferroelectric states +F or - F. If a voltage less than that required to give full switching is applied, an intermediate grey level is obtained and, on removal of the voltage, the device relaxes to the AF state by way of the 4 corresponding shallower hysteresis curve shown in broken lines in Figure I a. As the F to AF relaxation can be quite slow, a reset period is usually required before the next fi-ame is addressed in order to ensure that the transmission level in the next frame is not affected by the transmission level of the previous frame. Figure lb shows typical (asymmetrical) voltage-transmission characteristics of an AFLC on switching to and from each of the ferroelectric states, from which it YAN be seen that the light transmission characteristics of the ferroelectric states are generally different in a typical AFLC.

As is well known, a passive addressing scheme for a liquid crystal display 10 commonly uses row and column electrodes which intersect one another at the pixels of the display, and a data driver for supplying display data to the column electrodes in synchronism with scan pulses supplied to the row electrodes by a scan driver in a cyclicafly repeating sequence so that the rows of pixels are refreshed one at a time until all of the rows have been refreshed to complete refreshing of a frame of display data.

The process is then repeated for the next frame of data. Figure 2a shows a suitable scan waveform for addressing the passively addressed AFLCD as described above in which the polarity of the applied voltage is reversed from frame to frame. Such a waveform comprises, during each addressing frame, a select (strobe) period 1, a non-select (holding voltage) period 2 and a reset period 3. The polarity of these periods is reversed from frame to frame in order to maintain the net DC balance of the pixels along the rows, and Figure 2a shows the waveforms of scan pulses applied during two successive fi-ames, of such a passive addressing scheme. Furthermore DC balanced data pulses are applied to the column electrodes which, when combined with the select (strobe) period I of the scan pulses applied to the row electrodes, determine the optical state (F, AF or intermediate) of the pixel during the non-select (holding voltage) period 2. Figure 2b shows typical DC balanced bipolar data pulses which may be applied to the column electrodes in such a passive addressing scheme corresponding respectively to an ON signal and an OFF signal for selection of the F state or the AF state in the select period I of the positive polarity pulse of Figure 2a, and an ON signal an OFF signal for selection of the F state or the AF state in the select period I of the negative polarity pulse of Figure 2a. Since the data pulses (but not the resultant pulses obtained by combined of the data and strobe pulses) are DC balanced during one line address time in such a passive addressing scheme, this results in application of a high frequency to the display at all times and leads to high power consumption.

j M. Yamawaki, Y. Yamada, N. Yamamoto, K. Mori, H. Hayashi, Y. Suzuki, Y.S. 15 Negi, T. Hagiwara, I. Kawamura, H. Orihara and Y. Ishibashi, Japan Display 1989, p. 26-9 discloses a passive addressing scheme for an AFLCD in which two addressing frames of opposite polarity are used for one display picture in order to effect DC balancing. As in the previously described passive addressing scheme the scan waveform comprises, during each addressing frame, a select (strobe) period and a non-select (holding voltage) period, and, during the select period, an ON data signal or an OFF data signal selects the F state or the AF state of a pixel as the case may be, this state being maintained by the application of the holding voltage within the following non- 6 select period. In the subsequent frame the polarity of the periods is reversed in such a manner that the pixel is switched to the opposite F state where an ON signal is applied or is maintained in the AF state where an OFF signal is applied. In this manner the transmission level is kept the same in the two addressing frames of opposite polarity used to display a single picture whilst providing DC balancing. However, as in the passive addressing scheme already described, a holding voltage must be applied in order to maintain the device in one of the ferroelectric states with consequent implications for power consumption. Furthermore, since conventional AFLC's with suitable switching thresholds require a voltage in the range of between 20 to 40 volts to switch, relatively high voltages are necessary in such a passive addressing scheme. There is no disclosure in this reference of greyscale.

S. Quentel, C. Rodrigo, J.M. Oton, Journal of the SID, 4/1, 1996, p. 19 discloses an AFLCI) passive addressing scheme using scan waveforms as shown in_Figure 2a combined with unipolar data pulses. Since the polarity of the scan waveform is reversed from frame to frame, the polarity of the data pulses is also changed from frame to frame. However, since different data is applied in each frame, the device is only statistically DC balanced, and it is still possible for a net DC voltage to be applied to some pixels for long periods such that any ionic build-up in these periods results in certain grey levels being unobtainable. A further disadvantage of this addressing scheme is that the AFLCD must be arranged between crossed polarisers in order to optimise the symmetry of the switching so that positive and negative voltages of the same amplitude result in similar 7 light transmission levels, and it is not possible to ensure that such symmetry is obtained for all voltages as asymmetry is a function of voltage. For example, if the device is set to give equivalent maximum bright states, the maximum dark state'%Nill not be obtained at zero volts.

European Patent Publication No. 0586155A.2 discloses an active matrix addressing circuit for a liquid crystal display in which each pixel includes a thin film transistor JFT) switching element and a pixel capacitance. The gate terminal of the switching element is connected to the scan electrode such that, when an appropriate scan pulse is applied to the scan electrode, the switching element is turned on in order to transfer a data pulse applied to the data electrode to the pixel capacitance. In this way an image is displayed based on the applied data, and the image is maintained even after the switching element is turned off due to the maintenance of charge by the pixel capacitance under the effect of the applied electric field. However such an active matrix addressing scheme is not capable of providing accurately reproducible grey levels when used with conventional ferroelectric liquid crystal materials. Furthermore such an addressing scheme is not suitable for addressing a conventional AFLC material since such materials require 2040 volts to switch and TFT switching elements can operate at only up to about 20 volts (and preferably operate at substantially less than 20 volts).

British Patent Application No. 9609064.2 discloses a polycrystalline silicon active matrix addressing for a circuit in which each pixel includes a TFT switching 8 element having a data input for receiving data pulses from the data electrode and a scan input connected to the scan electrode, a storage capacitor connected to the output of the switching element and a buffer amplifier connected between the output of the switching element and the pixel. Such a circuit allows substantially constant voltage addressing of the display so that, during each frame, a continuous voltage of one or other polarity is applied to each pixel, thus reducing the power requirement of the display. However, as with the previous reference, such all active matrix addressing scheme is not suitable for an AFLC material.

It is an object of the invention to provide an active matrix light modulator, such as an AFLC1) for example, which allows repeatable grey levels to be obtained and addressing asymmetry, where present, to be substantially eliminated.

According to the present invention there is provided an active matrix light 15 modulator comprising a plurality of data lines, a plurality of scan lines, an active matrix of control elements disposed at intersections of the data lines and scan lines, an array of pixels which are selectively addressable by data and scan signals applied to the control elements by way of the data and scan lines so as to be set to a first optical transmission state in response to a positive applied voltage of a particular magnitude, a second optical state in response to an intermediate applied voltage and a third optical state in response to a negative applied voltage of equal magnitude, but opposite polarity, to said positive applied voltage, addressing means for addressing each pixel during a corresponding 9 addressing frame by the application of data and scan signals to an associated one of the control elements in order to select the optical level of the pixel for each frame, and voltage inversion means for controlling the voltage applied to each pixel during successive subframes of each frame such that, when one optical level is selected for the fi-ame, said positive voltage is applied to the pixel during one subfirame of the frame and said negative voltage is applied to tht pixel during another subfirame of the frame and, when another optical level is selected for the frame, said intermediate voltage is applied to the pixel during both of the subfirames of the frame, so as to provide DC balancing within the frame.

Such an active addressing arrangement makes the use of AFLCD's, for example, much more feasible since repeatable grey levels can be obtained due to the provision of DC balancing within a single addressing frame by virtue of the fact that the frame consists of the two sub-frames driven by voltages of opposite polarity. Such DC balancing avoids long term build up of ionic effects which would otherwise result in degradation of grey levels with time. Such an arrangement is also compatible with existing polysilicon active matrix drive circuitry providing low power addressing for materials with a high spontaneous polarisation and ensuring that the state of each pixel is held during the frame time without requiring application of a constant holding voltage. Thus the use of AFLCD's with their inherent features of wide viewing angle, low power consumption and possible reflective use becomes feasible in a wide range of applications high quality desk top publishing displays. Additionally such an arrangement can compensate for the asymmetrical voltage-transrnission characteristics typically possessed by some AFLC materials by taking the temporal average of two subfirames driven by voltages of opposite polarity so that any optical difference (intensity or chromaticity) between the positively and negatively driven subfi-ames is averaged by the observer and is unimportant. Preferably the intermediate applied voltage is zero voltage. However it will be appreciated that, where the intermediate applied voltage is not zero, an opposite polarity voltage is required to provide DC balancing within the frame. Furthermore, although it is preferred that the positive and negative voltages are applied in the same order in each frame, it is also possible for the order of these voltages to be reversed in alternate frames.

In one embodiment the first and third states are symmetrical in that they exhibit substantially the same optical level in response to said positive and negative applied voltages, and the voltage inversion means is adapted to apply said positive and negative voltages to the pixel during the two successive subfi-ames when said one optical level is selected such that the same optical level is obtained during the two subfirames.

In an alternative embodiment the first and third optical states are asymmetrical in that they exhibit different optical levels in response to said positive and negative applied voltages, and the voltage inversion means is adapted to apply said positive and negative voltages to the pixel during the two successive subfirames when said one optical 11 level is selected such that different optical levels are obtained during the two subfrarnes.

The voltage inversion means may be adapted to modulate addressing of each pixel by the addressing means by means of a voltage inversion switching waveform having 2N portions for addressing 2N subframes within the frame, where N is an integer greater than zero and consecutive portions have voltages of equal magnitude and duration but opposite polarity.

Furthermore the voltage inversion means may be adapted to supply a voltage inversion switching waveform consisting of two portions having voltages of equal magnitude and duration but opposite polarity which follow one another substantially inunediately. In an alternative embodiment the voltage inversion means may be adapted to supply a voltage inversion switching waveform comprising portions having voltages of equal magnitude and duration but opposite polarity and a further portion of zero voltage.

In one embodiment each of the pixels may be addressable so as to be set to one of a plurality of first optical states in response to a selected one of a plurality of different positive applied voltages or one of a plurality of third optical states in response to a selected one of a plurality of different negative applied voltages, and the voltage inversion means may be adapted to apply said selected positive voltage to the pixel during one subframe of the frame and said selected negative voltage to the pixel during 12 another subframe of the frame in order to select one of a plurality of possible optical levels for the frame whilst maintaining DC balancing within the frame.

Preferably the active matrix incorporates a respective control element coupled to each pixel and having a data input for receiving data signals from a corresponding one of the data lines and a control input for receiving scan pulses from a corresponding one of the scan lines in order to switch the control element to supply a voltage to the pixel. Most preferably a storage capacitor is coupled to the output of the control element, and a buffer is connected between the output of the control element and the pixel.

is Where the light modulator is a light transmissive liquid crystal device the array is disposed between polarisers arranged with their axes transverse to one another such that said first and third optical states are bright states and said second optical state is a dark state. Alternatively the array may be disposed between polarisers arranged with their axes substantially parallel to one another such that said first and third optical states are dark states and said second optical state is a bright state. In a further alternative the array may be disposed in series with a further array of similar form between polarisers arranged with their axes substantially parallel to one another, and the addressing means may be adapted to simultaneously apply addressing signals of opposite polarity to the arrays such that a dark level is obtained when one of the arrays is in said first optical state and the other array is in said third state and a bright level is obtained when both arrays are in said second optical state. In a further alternative the array may be disposed 13 between a polariser and a reflective surface with a quarter wave retarder being disposed between the array and the reflective surface such that a dark level is obtained when the array is in one of said first and third optical states and a bright level is obtained when the array is in said second optical state.

Where the light modulator is a diffractive spatial light modulator, the active matrix may incorporate a set of first elongate electrodes on one side of the array, a set of second elongate electrodes interdigitated with the set of first elongate electrodes on said one side of the array, and a set of pixel electrodes on the other side of the array each of which overlaps a plurality of first and second electrodes, the first and second electrodes being connected to respective supply lines for continuously applied voltages and each of the pixel electrodes being addressable by the addressing means for switching between a diffractive mode and a non-diffractive mode, wherein the voltage inversion means is adapted to invert the voltages applied to the first and second electrodes about a predetermined voltage between the two subframes at the same time as inversion of the voltages applied to the pixel electrodes.

In order that the invention may be more fully understood, reference will now be made, by way of example, to the accompanying drawings, in which:

Figures la and lb show ideal (symmetrical) voltage-transmission characteristics of an AFLC and typical (asymmetrical) voltage-transmission characteristics of an AFLQ Figures 2a and 2b show the scan and the data waveforms used in a prior art

14 AFLCD addressing scheme, Figures 3a and 3b show a bipolar pulse and a bipolar pulse with gap for use in an addressing scheme of a device in accordance with the present invention; Figures 4a and 4b show typical voltage-transmission characteristics of an AFL for use in an AMICD in accordance with the present invention.

Figures 5, 6 and 7 show measured waveforms used in accordance with the present invention for addressing a thresholdless AFLC, SBFLC and DEIFLC respectively; c Figures 8 and 9 diagrammatically show two active matrix drive circuits which may be used in an AMILCD in accordance with the present invention; Figures 10 and 11 show a portion of an AMLM in accordance with the present invention and a voltage diagram showing the voltages applied to such a portion; Figures 12a and 12b show liquid crystal transmission characteristics with respect to time on application of a bipolar pulse with gap at a high temperature and at a low temperature respectively; Figure 13 diagrammatically illustrates an addressing scheme used in a diffractive light modulator in accordance with the present invention; Figure 14 diagrammatically shows the electrode arrangement of such a diffractive light modulator; Figures 15a, 15b and 15c show three addressing waveforms which may be used in devices in accordance with the present invention; and Figures 16, 17 and 18 show measured waveforms used in accordance with the present invention for addressing a thresholdless AFLC and SWLC.

A preferred addressing scheme to be used in an active matrix liquid crystal display (AMILCD) in accordance with the present invention will now be described. Such 5 an addressing scheme requires use of a liquid crystal material exhibiting voltagemission characteristics which are free or almost free of hysteresis. Such materials include thresholdless antiferroelectric liquid crystal (TAFLC) materials, deformed helix ferroelectric liquid crystal (DHFLC) materials or short-pitch bistable ferroelectric liquid crystal (SBFLC) materials. The addressing scheme also requires the use of an active matrix incorporating switching elements which are preferably in the form of thin film transistors (M) or thin film diodes (TFD), such as is disclosed, for example, in British Patent Application No. 9609064.2 referred to above.

Furthermore the addressing scheme makes use of bipolar switching within each addressing fl-ame so that the voltage applied across a pixel is of the form shown in either Figure 3a or Figure 3b, in order to provide voltage inversion between successive subframes within a single addressing frame and to thereby provide DC balancing within the addressing frame. A gap may be provided between the positive and negative parts of the switching waveform, as shown in Figure 3b.

In the case of the bipolar switching waveform of Figure 3a, the voltage V apphed across the pixel as a function of time t (0:5 t < T), during a frame of period T satisfies 16 the requirement:

V(t + T12) = - V(t) for 0:5 t < In the case of the bipolar switching waveform of Figure 3b having an intermediate gap of duration tI, the voltage V applied across the pixel satisfies the requirements.

V = 0 for - 1 -< t < t 1 T - t T + 2 2 V(t + 11+T V(t) for 0 -< t < + 2 T - t, 2 In each case each frame is made up of 2N consecutive subframes, where N is an integer, consisting of N subframes of one polarity alternating with N subframes of the opposite polarity but with a voltage of the same magnitude but opposite sign to the voltage of the subframes of the one polarity Because such an addressing scheme makes use of two (or more) subframes within each addressing frame, the switching waveform being of opposite polarity in the two subframes and passing through zero between each pair of adjacent subframes, so that DC balancing is provided within each frame, the required grey level within each frame is accurately reproduced and is rendered substantially independent of the previous 17 state, without requiring a reset period.

Figure 4a shows the light transmission r of a TAFLC, which may be used in the AMLCD of the invention, as a function of the applied voltage, showing the antiferroelectric (AF) maximum dark state at zero volts and the ferroelectric (+F and -F) bright states symmetrically positioned relative to the AF state. On switching of such a device, a smooth transition is obtained between the AF and F states and only narrow hysteresis is observed on returning to the AF state by comparison with the case of AFLC's exhibiting appreciable hysteresis as shown in Figures I a and I b. A. Fukuda, Asia Display 1995, p. 61-64 describes such a TAFLC. Furthermore full switching is obtained at much lower voltages, for example at voltages of the order of 5V as compared with such AFLUs. Such low voltages imply that TAFLC's can be addressed by an active matrix, such as a TFT matrix for example. However TAFLC's possess a large spontaneous polarisation which makes the use of conventional amorphous silicon TFT's difficult. Nevertheless such difficulties can be overcome by making use of an active matrix circuit utilising polysilicon TFT's, such as that disclosed in British Patent Application No. 9609064.2 for example. Figure 4b shows the corresponding voltagetrarisrnission characteristics of a further TAFLC, which may be used in the AMIM of the invention, in which the ferroelectric (+F and -F) bright states are asymmetrically positioned relative to the anitferroelectric (AF) state.

Conventional AFLC materials with wide hysteresis and large voltage thresholds 18 would not generally be suitable for the device of the invention in that they require larger voltages to switch which are incompatible with active matrix addressing, and they tend to have a hysteresis curve which rises sharply over a narrow voltage range up to maximum transmission, thus allowing for fewer grey levels. Also, since their hysteresis 5 loop is wide, they take a long time to relax to the AF state and such relaxation may not occurwrithin the available frame time, with the result that the subsequent grey level will be affected by the previous state. By contrast TAFLC materials tend to have a narrow hysteresis loop and a steeper hysteresis curve up to maximum transmission, thus allowing faster driving and more grey levels to be accessible Before describing in detail possible active matrix circuits which may be implemented for carrying out the addressing scheme used in the device in accordance with the present invention described above, three examples will be described with reference to Figures 5, 6 and 7 of experiments conductedwith TAFLC, SWLC and DEFLC materials utilising such an addressing scheme.

Example I

Experiments were conducted in a 2pm thick antiparallel aligned cell filled with thresholdless AFLC material. The cell was rotated between crossed polarisers to give minimum transmission with zero volts applied. Because of the particular materialalignment combination chosen, the cell showed asymmetric transmission behaviour, that is the light transmission obtained from the application of voltages of the same magnitude 19 but opposite polarity was not equivalent. The cell was addressed using a bipolar frame of 20 milliseconds duration, made up of two subframes of equal but opposite voltage, as shown in the upper part of Figure 5. The total light transmission for each frame, as shown in the lower part of Figure 5, was composed of two unequal contributions from each subframe, the total brightness being determined by the voltage applied. As each frame was DC balanced and the AF state was reached before addressing the next frame, there was no ion build up and therefore reproducible grey levels could be achieved without requiring an ionic reset pulse. Therefore the cell could be addressed by continually applying bipolar pulses of varying voltage (0-5V) and the level of grey was reproducible, being essentially independent of the previous state. A suitable TAFLC material which may be used in such an example is MELC0076 as disclosed by S.S.

Seomun et al, "Electrooptic Property of a Binary Mixture of Ferroelectric and Antiferroelectric Chiral Compounds Showing Threshholdless V-shaped switching", Third International Display Workshops, Lcp 1-4 (1996), p. 6164.

Example 2

Experiments were conducted in a 21im thick antiparallel aligned cell filled with a SBFLC matefial. The cell was rotated between crossed polarisers to give minimum transmission with zero volts applied. The cell showed substantially symmetfic transmission behaviour, that is the light transmission obtained from the application of voltages of the same magnitude but opposite polafity was approximately equivalent. The cell was addressed using a bipolar frame of 20 milliseconds duration, made up of two subframes of equal but opposite voltage, as shown in the upper part of Figure 6. The total light transmission for each frame, as shown in the lower part of Figure 6, was composed of two equal contributions from each subframe, the total brightness being determined by the voltage applied. As each frame was DC balanced and the relaxed state was reached before addressing the next frame, there was no ion build up and therefore reproducible grey levels could be achieved without requiring an ionic reset pulse. Therefore the cell could be addressed by continually applying bipolar pulses of varying voltage (0-3V) and the level of grey was reproducible, being essentially independent of the previous state. A suitable SBFLC material which may be used in such an example is FLC6430 supplied by F. Hoffmann - La Roche and disclosed by J. FiLinfschilling, Japanese Journal of Applied Physics, vol. 40, No. 4, p. 741-746 (1991).

Example 3

Experiments were conducted in a 2gm thick antiparallel aligned cell filled with 15 a DI-IFLC material. The cell was rotated between crossed polarisers to give minimum transmission with zero volts applied. The cell showed asymmetric transmission behaviour, that is the light transmission obtained from the application of voltages of the same magnitude but opposite polarity was not equivalent. The cell was addressed using a bipolar frame of 20 milliseconds duration, made up of two subframes of equal but opposite voltage, as shown in the upp.er part of Figure 7. The total light transmission, as shown in the lower part of Figure 7, for each frame was composed of two unequal contributions from each subframe, the total brightness being determined by the voltage 21 applied. As each frame was DC balanced and the AF state was reached before addressing the next frame, there was no ion build up and therefore reproducible grey levels could be achieved without requiring an ionic reset pulse. Therefore the cell could be addressed by continually applying bipolar pulses of varying voltage (O-W) and the level of grey was reproducible, being essentially independent of the previous state. A suitable DI1FLC material which may be used in such an example is FLC 10 150 supplied by ROLIC and disclosed by G. Cnossen et al, SID 96 Digest, p. 695-698 (1996), In order to implement the addressing scheme in an AMELCD utilizing TAFLC, SBFLC or DIHFLC material in accordance with the present invention described above, it is necessary to apply a substantially constant voltage across the liquid crystal material during each of the subframes of the bipolar switching waveform shown in Figure 3a or 3b, and the application of such a voltage can be achieved in two different ways. In a first embodiment shown in Figure 8, a regular rectangular active matrix array 10 of pixels comprises column electrodes addressed by a data driver 12 and row electrodes addressed by a scan driver 14, the active circuit 16 associated with each pixel comprising a polysilicon thin film field effect transistor 18 connected by its gate to the scan electrode and by its drain to the data electrode 22, and a fixed storage capacitor 24 connected to the source of the transistor 18 in parallel with the pixel capacitance 26. When the electrode 20 receives a scan pulse from the scan driver 14, the transistor 18 is turned on in order to cause the voltage on the data electrode 22 applied by the data driver 12 to charge up the storage capacitor 24. When the scan pulse is removed from the scan 22 electrode 20, the transistor 18 is turned off in order to isolate the storage capacitor 24 from the data electrode 22 so that the light transmission of the pixel corresponds to the voltage across the storage capacitor 24 until it is refreshed during the next frame. Since the spontaneous polarisation of the liquid crystal modes used is high, it is necessary to apply a large amount of charge to the pixel, and accordingly a large storage capacitor 24 is required to effect the charge transfer at substantially constant voltage. However the charge must be transferred within a scan line period and this requires considerable peak currents to flow, thereby dissipating considerable power. Furthermore a large storage capacitor would have a deleterious impact on the aperture ratio of the display.

An alternative active circuit 16' for use in the AMLCD of the present invention is shown in Figure 9 and includes, in addition to the components already referred to, a buffer amplifier 28 having unity voltage gain connected between the storage capacitor 24 and the pixel capacitance 26. The buffer amplifier 28 has a very high input impedance and a relatively low output impedance so that, when the transistor 18 is turned off, the output of the amplifier 28 follows the voltage across the storage capacitor 24 whereas the current supplied to the input of the amplifier 28 is negligible so that discharge of the storage capacitor 24 is much slower than in the previous circuit arrangement. Accordingly the storage capacitor 24 can be a relatively small capacitor which can be easily charged up to the desired voltage on turning on of the transistor 20. The pixel connected to the output of the amplifier 28 receives a constant voltage equal to the voltage on the storage capacitor 24, and, since the charge is supplied at the rate 23 at which the liquid crystal material switches, the circuit consumes less dynamic power than the previously described active circuit. The buffer amplifier can also implement the subframe inversion required in the addressing scheme of the invention in order to achieve repeatable grey levels as described above.

In order that the operation of such a circuit can be fully understood, reference,%rill now be made to Figure 10 which shows four pixels A, B, C and D disposed at the intersections of two scan electrodes 20a, 20b and two data electrodes 22a, 22b,. A corresponding voltage diagram is provided in Figure I I showing the scan voltages applied to the scan electrodes 20a and 20b, the data voltage applied to the data electrode 22a, and the voltages Vs, and VLCI applied to the storage capacitor 24 and the pixel capacitance 26 of the pixel A during two subframes of the addressing frame.

Referring to Figure 11, beginning at t = 0, a scan voltage of, say, 12V is applied 15 to the scan electrode 20a in order to turn on the transistor 18 of pixel A, the voltage being maintained for the duration of the line time after which the voltage on the scan electrode 20a is OV for the rest of the half-frame. The turning on of the transistor 18 causes the voltage + Vd.,, on the data electrode 22a to charge up the storage capacitor 24 as well as the pixel capacitance 26. The pixel voltage is thereby changed from Vp,,A., the voltage level of the previous address line, to the applied data voltage Vda which will vary in magnitude depending on the state selected for the pixel. The same voltage is then held on the storage capacitor 24 (Vsl) and the pixel capacitance (VLcj) 24 for the rest of the half-frame. At the start of the second half-frame, the same scan voltage is applied to the scan electrode 20a, but a negative data voltage -V,, is applied to the data electrode 22a with the result that the voltages held on the storage capacitor 24 and the pixel capacitance 26 are changed to Vd.,, and are held for the rest of the second half-frame. It will accordingly be appreciated that the voltage applied to the pixel A will be inverted between successive half-frames within the addressing frame in order to provide DC balancing within the frame.

The data voltages applied to the data electrodes such as 22a and 22b are 10 continuously applied during each half-frame, and a scan voltage is applied to the scan electrode 20b during the line time following the line time in which the scan voltage was previously applied to the scan electrode 20a in order to turn on the transistor 18 of the next pixel C to be addressed in the half-frame. This sequence is repeated for all the pixels of the display, and, following voltage inversion, addressing of the pixels is then effected in similar manner during the second half-frame except that the data voltages are inverted. In an alternative drive scheme, the voltage on the storage capacitor is the same in the two half-frames, but the buffer amplifier 28 of each pixel is caused to invert the polarity of the signal applied to the pixel during the second half-frame.

It will be appreciated that the above described addressing scheme produces a bipolar switching waveform without gap as shown in Figure 3a. However a bipolar switching waveform with gap as shown in Figure 3b can be produced in a similar manner except that, instead of each frame being divided into two half-frames with a positive data voltage + Vd., being applied to the data electrode 22a in the first half-frame and a negative data voltage Vd., being applied to the data electrode 22a in the second halfframe, each frame is divided into three part-frames with a positive data voltage being applied to the data electrode 22a in one part-frame, a negative data voltage being applied to the data electrode 22a in another part-frame, and zero voltage being applied to the data electrode 22a in a futher part-frame which may be intermediate the other two partfl-ames or at the beginning or end of the frame. The duration of the positive and negative voltage part-frames should be equal (x/3 of frame period), whereas the duration of the zero voltage part-frame will typlcdy be substantially less (y/3 of frame time, where 2x/3 + y/3 = 3/3 = 1 and y << x). Similar scan voltages are applied to the scan electrodes 20a and 20b at the start of the positive and negative part-frames (but not at the start of the zero voltage part- fi-ame) as are applied at the start of the two half-frames in the bipolar switching waveform without gap addressing scheme already described. Thus a bipolar switching waveform is produced comprising portions having voltages of equal magnitude and duration but opposite polarity and a further portion of zero voltage.

Whilst the above described circuit arrangements can be implemented with an addressing scheme based on a bipolar switching waveform without gap as shown in Figure 3a or a bipolar switching waveform with gap as shown in Figure 3b, a potential advantage of using a bipolar switching waveform with gap is that it will tend to average the light transmission obtained if the material viscosity changes with temperature. As 26 shown in Figure 12a, the lower viscosity of the material which is typically obtained at higher temperatures allows the material to respond more quickly to an electric field, and this is reflected in the form of the corresponding transmission characteristic against time. On the other hand, the viscosity of the material typically increases with decreasing temperature, thus leading to a decrease in the response of the material. However, by increasing the length of the gap of the bipolar switching waveform as shown in Figure 12b, the transmission characteristic can be altered so as to compensate for changes in temperature.

Such an addressing scheme can also be applied to an AFLCD comprising two AFLC cells arranged in series between a pair of polarisers, having parallel axes and set such that the display as a whole is in the bright state at zero volts and the application of voltages of opposite polarities to the cells causes the respective optic axes of the cefls to rotate in opposite directions so that the light transmission of the display becomes darker. In this case each of the two cells is addressed by a similar bipolar addressing scheme. Furthermore the bipolar addressing scheme may be applied to a single polariser reflection AFLCD incorporating a quarter wave plate with its axis parallel to the polariser axis so that the bright state is obtained at zero volts and the transmission becomes darker when a voltage of either polarity is applied to the display.

Such an addressing scheme is also applicable to an active matrix liquid crystal grating panel constituting a diffractive spatial light modulator (SLM) such as is disclosed 27 in British Patent Application No. 9611993.8. Such a diffiractive SLM, which may have a transmission geometry or a reflection geometry, comprises top and bottom substrates made of glass and ferroelectric liquid crystal material disposed between the substrates. The top substrate carries two sets of interdigitated transparent electrodes 20 and 21, as shown in broken lines in Figure 14, with the electrodes of each set being connected together and interdigitated with the electrodes of the other set so that only two connections are required to opposite sides of the top substrate. The bottom substrate 2 carries a rectangular array of pixel electrodes 23 3, as shown in solid lines in Figure 14, each pixel electrode 23 facing a plurality of interdigitated electrodes 20 and 21.

By applying suitable voltages to the various electrodes, each pixel can be switched between a non-diffiactive mo0e in which light is transmitted or reflected in the zeroth order of diffaction, and a diffractive mode in which the pixel forms a phase-only diffraction grating and light is diffracted in non-zeroth orders of diffraction. In the diffractive mode, each pixel comprises a plurality of strip regions of liquid crystal material in which adjacent regions are in different states such that light beams passing through adjacent strip regions undergo a relative phase shift of 180 degrees. In the nondiffiractive mode, all light passing through the pixel is subject to substantially the same phase change. By collecting light diffracted in the first order of diffraction for example for display, each pixel will appear dark in the non-diffiractive mode and light in the diff-ractive mode.

Furthermore each pixel may be addressable by way of an active circuit 24 associated with each pixel electrode 23 and shown diagrammatically on an enlarged scale in Figure 14. In the arrangement illustrated, each pixel electrode 23 is connected to the source of a polysilicon thin film field effect transistor, and the drains of the transistors of each column of pixels are connected to a respective column or data electrode 25, whereas the gates of the transistors of each row are connected to a respective row or scan electrode 26. The pixels are thus enabled one row at a time so that data for a complete row are written simultaneously.

British Patent Application No. 9702076.2 discloses an addressing scheme for switching between the diffractive and non-diffractive modes of the pixels in which, in order to provide a net voltage across each strip region when averaged over time which is equal to zero, all the electrode voltages are reversed about an arbitrary voltage Varb during alternate addressing frames. Thus, during a first frame (FRAME 1), the pixel ON mode (the diffractive mode) is defined by continuous voltages VI and V2 applied to the interdigitated electrodes 20 and 21 and a write voltage V.. i,, applied to the pixel electrode 23 such that V,,,, is between VI and V2. This causes adjacent strips of liquid crystal material to be switched oppositely such that the pixel acts as a phase-only diffraction grating. The pixel OFF mode (the non-diffractive mode) is defined by the same continuous voltages V I and V2 applied to the interdigitated electrodes 20 and 21 and an erase voltage V,,., applied to the pixel electrode 23 such that V.

. is below VI and V2. This causes adjacent strip regions to be switched to the same state and means 29 that light passing through the strip regions is subjected to the same phase shift so that the pixel does not diffiract light. In a second frame (FRAME 2), the ON and OFF modes of the pixel are similarly defined except that the continuous voltages applied to the interdigitated electrodes 20 and 21 are (Varb - V I) and (Varb - V2), the write voltage applied to the pixel electrode 23 is (Varb - V,,,i,e and the erase voltage applied to the pixel electrode 23 is (Varb - Ve,,.c ) so that the electric field directions are reversed for the ON and OFF modes of the pixel as compared with FRAME I in order to provide DC balancing over a large number of frames. Because the image data generally changes with time, such DC balancing relies on statistical averaging over a period of time, and perfect DC balancing over short periods of time is not of course possible with such an addressing scheme.

By contrast, the addressing scheme applied to the SLM in accordance with the invention, which is illustrated diagrammatically in Figure 13, provides DC balancing within each addressing frame, rather than relying on statistical averaging over a period of time. In this case all the electrode voltages are inverted about an arbitrary voltage Varb, which may be for example 5 volts, during successive subframes within a single addressing frame. Thus, in the example given in Figure 13, the ON mode of the pixel in a first subframe, SUBFRAME la, is defined by continuous voltages VI and V2, of 15 volts and 5 volts for example, applied to the interdigitated electrodes 20 and 21 and a write voltage V,,. of 10 volts for example, applied to the pixel electrode 23 such that V,,,i. is between VI and V2, whereas the OFF mode of the pixel is defined by the same voltages VI and V2 applied to the interdigitated electrodes 20 and 21 and an erase voltage V. of 0 volts for example, applied to the pixel electrode 23 such that V. is below V I and V2. In a second subfi-me of the same frame, SLJBFRAMEE I b, the ON mode of the pixel is defined by continuous voltages (Varb - V 1) and (Varb - V2) applied 5 to the interdigitated electrodes 20 and 21 and a write voltage V',,,i,, equal to (Varb V.,i,,) applied to the pixel electrode 23, whereas the OFF mode of the pixel is defined by the same voltages (Varb - VI) and (Varb - V2) applied to the interdigitated electrodes 20 and 21 and an erase voltage V',,..,, equal to (Varb - V,.,) applied to the pixel electrode 23.

Such an addressing scheme provides DC balancing within a single addressing frame whilst simultaneously ensuring that the optical properties of the phase grating remain identical during the two subframes. The grating is written by applying a write voltage V,,,t, to the pixel electrode 23 which overlaps a plurality of the interdigitated electrodes 20 and 21 to which continuous voltages are globally applied which are reversed between successive subfi-ames as described above, whereas erasing is achieved by applying a voltage V. to the pixel electrode 2') which lies sufficiently below both VI and V2 as to ensure full switching of the pixel into the non- diffactive mode. In each case both the write voltage and the erase voltage are alternated between successive subframes as described above.

Such an addressing scheme relies on driving the device using two subfrarnes and 31 performing a voltage inversion at the mid point of the frame between the two subfi-ames. The addressing scheme may be implemented using a standard SRAM pixel architecture since the globally applied voltages on the interdigitated electrodes and the voltages applied to the pixel electrodes can then be inverted simultaneously (which is not possible with DRAM pixel architecture). In practice, all the voltages might be inverted about the mean of the voltage range accessible by the SRAM (as shown in the example of Figure 11). It is to be noted that there is no theoretical difference in the optical appearance of a phase diffraction grating and its inverse in such a device so that true intra-frame DC balancing is provided whilst maintaining the optical appearance. Furthermore, where the device is to be used to obtain analogue greyscale, such an addressing scheme enables analogue grey levels to be obtained whilst avoiding any significant historical dependence of such grey levels caused by ionic memory.

Figures 15a, 15b and 15c show three bipolar switching waveforms which may 15 be applied to a TAFLC or S13FLC material in an addressing scheme in accordance with the invention. In the case of Figure 15a, voltage inversion occurs between successive subframes as described above with reference to Figures 3 a and 3b, and there is a polarity change between successive frames A and B so that the voltage passes through zero between each successive frame. In the case of Figure 15b and 15c, however, whilst voltage inversion is still provided between successive subframes in each frame, the first subframe is not of the same polarity in each frame so that the second subframe of the frame A is of the same polarity as the first subframe of the following frame B and the 3 32 voltage does not pass through zero between successive frames. In each case, the voltage magnitudes of the pulses in the frames A and B are given as 0.5V and LOV by way of example only.

Figures 16, 17 and 18 show examples of the addressing of thresholdless AFLC material with switching waveforms of the general type shown in Figure 15a (in the case of Figure 16) and of a general type shown in Figures 15b and 15c (in the case of Figures 17 and 18). The total light transmission for each frame as shown in the upper part of each figure, was composed of two unequal contributions from each subframe, the total brightness being determined by the voltage applied as in the case of the earlier examples described. The same level of reproducibility of grey levels was obtained utilising the waveforms of Figures 15b and 15c as with the waveform of Figure 15a, but the additional advantage was obtained with the waveforms of Figures 15b and 15c that the transmission level for a particular voltage was increased. This was around a 20% increase for the thresholdless AFLC material, and would probably somewhat lower in the case of a SBFLC material due to the faster svAtching.

1 " J.)

Claims (24)

1. An active matrix light modulator comprising a plurality of data lines, a plurality of scan lines, an active matrix of control elements disposed at intersections of the data lines and scan lines, an array of pixels which are selectively addressabl by data and scan signals applied to the control elements by way of the data and scan lines so as to be set to a first optical transmission state in response to a positive applied voltage of a particular magnitude, a second optical state in response to an intermediate applied voltage and a third optical state in response to a negative applied voltage of equal magnitude, but opposite polarity, to said positive applied voltage, addressing means for addressing each pixel during a corresponding addressing frame by the application of data and scan signals to an associated one of the control elements in order to select the optical level of the pixel for each frame, and voltage inversion means for controlling the voltage applied to each pixel during successive subframes of each frame such that, when one optical level is selected for the frame, said positive voltage is applied to the pixel during one subframe of the frame and said negative voltage is applied to the pixel during another subframe of the frame and, when another optical level is selected for the frame, said intermediate voltage is applied to the pixel during both of the subframes of the frame, so as to provide DC balancing within the frame.

2. A light modulator according to claim 1, wherein said intermediate applied voltage is zero voltage.

3 4 3. A light modulator according to claim I or 2, wherein the first and third optical states are symmetrical in that they exhibit substantially the same optical level in response to said positive and negative applied voltages, and the voltage inversion means is adapted to apply said positive and negative voltages to the pixel during the two successive subframes when said one optical level is selected such that the same optical level is obtained during the two subframes.

4. A light modulator according to claim I or 2, wherein the first and third optical states are asymmetrical in that they exhibit different optical levels in response to said 10 positive and negative applied voltages, and the voltage inversion means is adapted to I apply said positive and negative voltages to the pixel during the two successive subframes when said one optical level is selected such that different optical levels are obtained during the two subfi-ames.

5. A light modulator according to any preceding claim, wherein the voltage inversion means is adapted to modulate addressing of each pixel by the addressing means by means of a voltage inversion switching waveform having 2N portions for addressing 2N subfi-ames; -within the frame, where N is an integer greater than zero and consecutive portions have voltages of equal magnitude and duration but opposite polarity.

6. A fight modulator according to claim 5, wherein the voltage inversion means is adapted to supply a voltage inversion switching waveform consisting of two portions having voltages of equal magnitude and duration but opposite polarity which follow one another substantially immediately.

7. A light modulator according to claim 5, wherein the voltage inversion means is 5 adapted to supply a voltage inversion switching waveform comprising portions having voltages of equal magnitude and duration but opposite polarity and a further portion of zero voltage.

8. A light modulator according to claim 5, 6 or 7, wherein the voltage inversion means is adapted to supply voltage inversion switching waveforms in successive fi-ames such that the polarity of the last subframe of a first of the frames is the same as the polarity of the first subframe of a second of the frames following the first frame.

9. A light modulator according to any preceding claim, wherein each of the pixels is addressable so as to be set to one of a plurality of first optical states in response to a selected one of a plurality of different positive applied voltages or one of a plurality of third optical states in response to a selected one of a plurality of different negative applied voltages, and the voltage inversion means is adapted to apply said selected positive voltage to the pixel during one subfi-ame of the frame and said selected negative voltage to the pixel during another subfi-ame of the frame in order to select one of a plurality of possible optical levels for the frame whilst maintaining DC balancing within the frame.

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10. A light modulator according to any preceding claim, wherein the control elements are polysilicon switching elements.

11. A light modulator according to claim 9, wherein the polysilicon switching 5 elements are polysilicon thin film transistors or diodes.

12. A li ht modulator according to any preceding claim, wherein the active matrix 9 C) incorporates a respective control element coupled to each pixel and having a data input for receiving data signals from a corresponding one of the data lines and a control input for receiving scan pulses from a corresponding one of the scan lines in order to switch the control element to supply a voltage to the pixel.

13. A light modulator according to claim 12, wherein a storage capacitor is coupled to the output of the control element, and a buffer is connected between the output of the control element and the pixel.

14. A light modulator according to any preceding claim, which is a light transmissive liquid crystal device.

15 A light modulator according to claim 14, wherein the array is disposed between polarisers arranged with their axes transverse to one another such that said first and third optical states are bright states and said second optical state is a dark state.

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16. A light modulator according to claim 14, wherein the array is disposed between polarisers arranged with their axes substantially parallel to one another such that said first and third optical states are dark states and said second optical state is a bright state.

17. A light modulator according to, claim 14, wherein the array is disposed in series with a further array of similar form between polarisers arranged with their axes substantially parallel to one another, and the addressing means is adapted to simultaneously apply addressing signals of opposite polarity to the arrays such that a dark level is obtained when one of the arrays is in said first optical state and the other array is in said third optical state and a bright level is obtained when both arrays are in said second optical state.

18. A light modulator according to claim 14, wherein the array is disposed between a polariser and a reflective surface with a quarter wave retarder being disposed between the array and the reflective surface such that a dark level is obtained when the array is in one of said first and third optical states and a bright level is obtained when the array is in said second optical state.

19. A light modulator according to any preceding claim, which is a diffractive spatial light modulator.

20. A fight modulator according to.claim 18, wherein the active matrix incorporates 38 a set of first elongate electrodes on one side of the array, a set of second elongate electrodes interdigitated with the set of first elongate electrodes on said one side of the array, and a set of pixel electrodes on the other side of the array each of which overlaps a plurality of first and second electrodes, the first and second electrodes being connected to respective supply lines for continuously applied voltages and each of the pixel electrodes being addressable by the addressing means for switching between a diffractive mode and a non-diffractive mode, wherein the voltage inversion means is adapted to invert the voltages applied to the first and second electrodes about a predetermined voltage between the two subfi-ames at the same time as inversion of the voltages applied 10 to the pixel electrodes.

21. A light modulator according to any one of claims 1 to 20, which is an antiferroelectric liquid crystal device.

22. A light modulator according to claim 2 1, which is a thresholdless antiferroelectric liquid crystal device.

23. A light modulator according to any one of claims 1 to 20, which is a deformed helix ferroelectric liquid crystal device.

24. A light modulator according to any one of claims 1 to 20, which is a short pitch bistable ferroelectric liquid crystal device.