GB2321121A

GB2321121A - Microprocessor has DSP functions

Info

Publication number: GB2321121A
Application number: GB9722595A
Authority: GB
Inventors: Osamu Ujimori
Original assignee: NEC Corp
Current assignee: NEC Corp
Priority date: 1996-10-24
Filing date: 1997-10-24
Publication date: 1998-07-15
Anticipated expiration: 2017-10-24
Also published as: GB2321121B; JP2845844B2; JPH10124309A; GB9722595D0

Abstract

A microprocessor has an instruction decoder 12 for decoding instructions of a program to output a series of instructions, and a control signal 23,24; a pointer instruction memory 15 controlled by the control signal for consecutively supplying address data; a memory pointer 14,16 receiving the address data to consecutively specify memory addresses; a data memory 13,17 addressed by the memory addresses and storing data for an arithmetic calculation; and an arithmetic logic unit 22 for receiving an instruction from the instruction decoder to execute the arithmetic calculation based on data supplied from the data memory. A flowchart (Figure 5) shows that RAM addresses, subsequent to the first one accessed, are changed by effecting XOR processing, with the control signal, of the least significant four bits of the address, and ROM addresses, subsequent to the first access, are changed by five decrementing operations. The microprocessor achieves a high speed calculation without a digital signal processor (DSP).

Description

2321121 MICROPROCESSOR The present invention relates to a microprocessor

device and, more particularly, to a microprocessor having a digital signal processor (DSP) function.

A general-purpose microprocessor is used not only for a general data processing but also for a digital signal processing in an equipment control. Fig. 1 is a block diagram of a conventional general-purpose microprocessor.

In Fig.1, a ROM (read-only memory) 17 or a RAM (random access memory) 13 for data memories, stores arithmetic element or delay data, which are supplied to the microprocessor for executing arithmetic calculation by using the data stored. In the conventional technique, the data from a register 21 or an instruction decoder 12 is supplied through an internal bus 25 temporarily to a corresponding RAM address register 26 or a ROM address register 27 for address designation through the data ROM 17 or the 2 data RAM 13. Then, the data is transferred from the ROM 17 or RAM 13 to the multiplier 18 or ALU (arithmetic logic unit) 20 through the internal bus 25 for executing arithmetic calculation. In the microprocessor, during frequently executed data address designation, the internal bus 25 is often busy for address data transfer, or the ALU 20 is requested for address designation. There is a problem in that other instructions cannot be perf ormed during such a period and the throughput of arithmetic calculations or multiplying process ing is decreased accordingly.

As a typical example of digital processing, the processing steps of the conventional general-purpose microprocessor is recited herein with reference to a biquadratic type IIR filter program which is most frequently used.

Eig.2 is an example of a flowchart for processing the secondary biquadratic IIR (Infinite Impulse Response) filter wherein rn (n=l to 6) represents a general-purpose register. Each steps from S1 through S14 in Fig.2 is used for revising data address designation. For example, in step SI, data stored in general- purpose register r3-1 is supplied to general-purpose register r3. The flowchart 3 instructions designated by S and serial numbers out of total 36 instructions dedicated to data address designation, which involves a problem in that data signaling rate cannot be enhanced.

As a solution for such a problem in the conventional general-purpose microprocessor, DSP is developed as a discrete processor having a circuit suitable for digital signal processing, which is particularly used for real-time signal processing as an essential component. In general, the DSP has, in addition to a hardware multiplier, a data bus and a program bus separately provided, wherein address areas are senarately provided for simultaneous accessing to the data and the program. In another configuration, a data memory pointer is provided instead, which is capable of processing for revising data address designation parallel with other functions to improve the ALU efficiency. The data memory pointer has many other functions including address calculation such as two-dimensional arrangement and butterfly arithmetics frequently used in a signal processing.

Most of DSPs have a storage area for storing instructions for data memory pointer parallel to other instructions in the same instruction block, and 4 they are synchronously executed for preventing the DSP from dedicating only for revising address designation in the processing.

Fig.3 shows a flowchart for a typical example of a program using this type of DSP to realize an IIR f ilter operation equivalent to the operation in Fig. 2 The flowchart of Fig.3 has 10 instructions including 5 multiplication/addition operations wherein the operations within each block are executed in one instruction cycle. That is, the number of instructions are reduced down to below 1/3 compared to Fig.2.

It is to be noted that the DSP has been specially developed for the improvement of arithmetic performance and efficiency by specifying the instruction set and circuit configuration for their executiononlyto adapt for digital signal processing, which limits the usage of the DSP. Specifically, the DSP has limited functions in I/0 port control, interrupt processing, and logical operation. Accordingly, it is generally considered that the DSP is not suitable as a replacement for the generalpurpose mi--ro::)rocessor for controlling an external circuit.

On the other hand, the application of the data memory pointer to realize a parallel processing in the general-purpose microprocessor reduces an efficient use of the instruction memory due to the addition of an area for the data memory pointer instructions parallel to the other instructions because the data memory pointer is less frequently used in other than the arithmetic signal processing. Particularly, it is considered impractical because the integration' of tChe DSP function in the general-purpose microprocessor causes the loss of compatibility with the conventional microprocessors and their software.

Although a microprocessor having a hardware multiplier is available recently for enabling multiplication/addition processing in one instruction cycle, due to the aforementioned reason, the integration of the data memory pointer in the general-purpose microprocessor as used in the DSP is still not realized. Hence, the conventional general-purpose microprocessor often lacks performance -for a real-time application even in a small system.

In view o'L the above, the combination of a discrete DSP and the generalpurpose microprocessor, or a host computer, is requested for constructing a real-time 6 signal processing system disregarding the scale of a system in almost all applications.

It is therefore an object of at least the preferred embodiment of the present invention to provide a microprocessor, which is capable of reducing the time length required for revising data address designation during digital signal processing without causing the loss of compatibility with software for the general-purpose microprocessor, only by adding a comparatively minor circuit with some expanded instruction set, thereby expanding the use of the microprocessor in the digital signal processing system area.

Accordingly, the present invention provides a microprocessor comprising means for decoding a series of instructions of a program to output a series of instructions and a control signal, address-supplying means controlled by said control signal for consecutively supplying address data stored therein, means for receiving said address data to consecutively specify memory addresses, data storing means adapted to be addressed by said memory addresses for storing data for an arithmetic calculation, and means for receiving an instruction from said decoding means to execute the arithmetic calculation based on data supplied from said data storing means based on said memory addresses.

In a preferred embodiment, a microprocessor comprises an instruction decoder for decoding a series of instructions of a program to output a series of instruction signals and a control signal, a pointer instruction memory controlled by the control signal for consecutively supplying address data stored in the pointer instruction memory, a memory pointer for receiving the address data to consecutively specify memory addresses, a data memory addressed by the memory addresses and storing data for an arithmetic calculation, and an arithmetic 7 logic unit for receiving instruction signals from the instruction decoder to execute the arithmetic calculation based on data supplied from the data memory addressed based on the memory addresses.

The parallel integrated digital signal processing function in the conventional general-purpose microprocessor can reduce the time length for data address designation for processing arit=etic operation, such as a digital filter program, by using the function of the address designation similar to the conventional DSP. The necessity of using the combination of a discrete DSP and the conventional microprocessor can be eliminated by the improvement of processing efficiency.

The microprocessor of the present invention can be realized with the addition and modification of the minor circuit, without losing software compatibility, whereby the existing softwares can be applicable for the microprocessor of the present invention.

Preferred features of the present invention will now be described, purely by way of example only, with reference to the accompanying drawings, in which:- 8 Fig. 1 is a block diagram of a conventional microprocessor; Fig.2 is a flowchart of a conventional biquadratic type IIR filter program; Fig.3 is a flowchart of a conventional digital signal processor (DSE1) compatible with the conventional IIR filter program of Fig.2; Fig. 4 is a block diagram of an embodiment of a microprocessor; and, Fig.5 is a flowchart of a biquaratic type IIR filter program routine for the microprocessor of Fig.4, equivalent to the program of Figs.2 and 3.

Referring to Fig.4, a microorocessor according to an embodiment of the present invention comprises an instruction memory 11, an instruction decoder 12, a data RAM 13, a data ROM 17, and an ALU block 22 having 9 multiplier 18 and an ALU 20, a RAM pointer 14 and ROM pointer 16 for addressing the data RAM 13, and the data ROM 17, respectively, and a printer instruction memory 15 for the RAM pointer 14 and ROM pointer 16. The instruction decoder 12 decodes arithmetic instructions supplied from the instruction memory 11, and supplies the address data for the RAM 13 and ROM 17 for reading the data stored therein for the calculation.

The ROM 17 and RAM 13 stores arithmetic coeficients and delay data, respectively, which are supplied to the multiplier 18 or ALU 20 through the internal bus 25 for executing the arithmetic calculation by using the data stored.

A pointer instruction enable signal 23 is supplied from the instruction decoder 12 to the pointer instruction memory 15. The pointer instruction enable signal 23 is kept at "1" between the execution of the start instruction of the pointer instructions and the execution of the end instruction of the pointer instructions. During the other interval, the pointer instruction enable signal 23 is kept at "'0"'.

A pointer instruction transfer signal 24 is also supplied from the instruction decoder 12 to the pointer instruction memory 15. The transfer signal 24 is kept at "1" during the time interval when the instruction decoder 12 executes memory transfer instruction, and is kept at "0" during the other interval.

The RAM pointer 14 and the ROM pointer 16 execute pointer instructions word by word when the AND of the pointer instruction enable signal 23 andthepointer instruction transfer signal 24 is "1", and stop the execution of the pointer instruction during the other interval. Thus, the pointer instruction is executed at a suitable timing during the execution of arithmetic operation.

The RAM pointer 14 has a 16-bit word length and its address area is of 65, 536 words. The address area can be optionally defined, when necessary, up to the upper limit of the data RAM capacity to be actually installed. The higher 12 bits out of the 16 bits are assigned for executing 0 clear, immediate addressing, and increment/decrement from the current address, and, a carry addition or a non-carry addition of an additional 4-bit data to the current 12-bi., -- address. By using a bit-by-bit XOR processing between the remaining 4 bits in the current address and the additional 4-bit data, the address can be re- designated.

The ROM pointer 16 has a 16-bit word length and its address area is of 65, 536 words. The address area can be optionally defined, when necessary, up to the upper limit of the data ROM capacity to be actually installed. The address is updated by executing 0 clear, immediate addressing, and increment /decrement from the current address. When a data trans f er ins true-Lion and a pointer instruction are executed in a single operating cycle for the data RAM 13 or the data ROM 17, the result of the pointer instruction is made valid after the data transfer.

The pointer instruction memory 15 can be implemented by either a RAM or ROM. If the pointer memory 15 is implemented by a RAM, prior to the execution of the pointer instruction, a requested length of pointer instructions stored in the instruction memory 11 in advance is transferred to the pointer memory 15 through the internal bus 25.

If the pointer instruction memory 15 is implemented by a ROM, operating steps for transferring the pointer instruction from the instruction memory 11 to the pointer instruction memory 15 can be omitted In this case, the pointer instructions should be stored in the ROM in advance.

12 Referring to Fig.5, a typical flowchart of program steps of processing and data transfer is shown by us ing the I IR f ilter program. wh ich f unct- ions similarly to Figs.2 and 3.

The process instruction and the pointer instruction are executed in a single step. Specifically, the RAM address is changed after an immediate addressing for the RAM address by executing XOR processing for the least significant 'Lour bits and one increment for the most significant four bits as detailed below.

In Fig. 5, in step 101, an initial RAM, address is set at dp for reading data from the RAM 13 for the arithmetic operation for a IIR filter, and an initial ROMaddress is also set at rp for reading a coefficient from the ROM 17 for the arithmetic operation, in step 102. Then, in step 103, the coefficient data from the ROM address designated in step 101 is stored in register r3, and immediately thereafter, the designated ROM address rp is updated by decrement. The data stored in registe-- ri is delivered to register r2 in step 104, and multiplication of data stored in register r2 by the data stored in register r3 is effected in step 105 to be stored in register ml, which is provided to store data after 13 multiplication. Then, the data stored in register rl is cleared in step 106.

Subsequently, the data from the ROM- address designated in step 103 is delivered to register r3, and immediately thereafter, the ROM address is updated by decrement in step 107. The data from the RAM address designated by the step 101 is then delivered to register r2, and immediatel -L y thereafter, the lower four bits of the RAM address (dpl) is X0Red with "1" to be toggled in step 108 for updating the four bits of the RAM address to thereby designating a RAM address storing the other of two series of the delay data for the arithmetic calculation. The data stored in register rl is added to the data stored in register m! to be stored in register rO, which is provided for storing summed data after multiplication, and immediately thereafter multiplication of the data stored in register r2 by the data stored in register r3 is effected to store the resultant data in register ml in step 109. The data from the ROM address designated in step 107 is delivered to register -3, and immediately therea-LE-Ler, ROM address is updated by decrement, in step 110.

The data from the RAM address designated in step 108 is delivered to register r2, and immediately 14 thereafter, the lower four bits of the RAM address is X0Red with "l" for updating to read delay data of the initially designated series, in step 111. The data stored in register rl is added to the data stored in the register ml to be stored in register rO, and data stored in register r2 is multiplied by the data stored in register r3 to be stored in register ml in step 112. The data from the ROM address designated in step 110 is delivered to register r3, and immediately thereafter, the ROM address is updated by decrement in step 113.

The data stored in register ml in step 112 is added to the data stored in register rO in step 109 to be stored in register rO, and immediately thereafter, the data stored in register r2 is multiplied by the data stored in register r3 to be stored in register ml in step 114. The data from the ROM address designated in step 113 is delivered to register r3, and immediately thereafter, the ROM address is updated by decrement, in step 115. The RAM address designated in step 111 is delivered to register r2 in step 116. The data stored in register ml is added to the data stored in register rO to be stored in register rO, and immediately thereafter, the data stored in register r2 is multiplied by the data stored in register r3 to be stored in register ml in step 117. The data from the RAM address designated in step 111 is delivered to register r4, in step 118.

The final data stored in register rO is then delivered to the RAM address designated in step ill and stored therein, and immediately thereafter, the lower four bits of the RAM address is X0Red with "1" forupdatinginstepl.19. The data stored in register r4 is then stored in the RAIM address designated in st--p 119, the lower four bits of the RAM address is X0Red with "1',' for updating, and the higher four bits of the RAM address is incremented for designating a next initial RAM address, in step 120. Finally, register r4 is cleared in step 121 for the next calculation.

In the manner as described above, the data stored in the RAM 17 are multiplied by the respective coef f icients stored in the ROM 13 to be consecutively added to form a sum/product data for the IIR filter.

In the above process after the initial coefficient data is designated by immediate accessing to the ROM 17, five times of decrements are processed for revising the ROM address after the immediate address designation.

16 In both the data RAM 13 and the data ROM 17, the address updating process following the designation of an immediate-address corresponds to a single request call from sub-routine steps of the secondary biquadratic type HR filter. Moreover, higher-order bits of the RAM address of the UR filters can be updated by repeating sub-routine processes in synchrony with the address transfer in the data RAM 13 and the data ROM 17.

Since the above embodiments are described only for examples, the present invention is not limited to the above embodiments and various modifications or alterations can be easily made therefrom by those skilled in the art without departing from the scope of the present invention.

Each feature disclosed in this specification (which term includes the claims) a.nd/or shown in the drawings may be incorporated in the invention independently of other disclosed and/or illustrated features.

specification.

The text of the abstract filed herewith is repeated below as part of the A microprocessor has an instruction decoder for decoding instructions of a program to output a series of instructions and a control signal, a pointer instruction memory controlled by the control signal for consecutively supplying address data, a memory pointer receiving the address data to consecutively specify memory addresses, a data memory addressed by the memory addresses and storing data for an arithmetic calculation, and an arithmetic logic unit for receiving an instruction from the instruction decoder to execute the arithmetic calculation based on data supplied from the data memory. The microprocessor achieves a high speed calculation without a digital signal processor.

17

Claims

A microprocessor comprising means for decoding a series of instructions of a program to output a series of instructions and a control signal, addresssupplying means controlled by said control signal for consecutively supplying address data stored therein, means for receiving said address data to consecutively specify memory addresses, data storing means adapted to be addressed by said memory addresses for storing data for an arithmetic calculation, and means for receiving an instruction from said decoding means to execute the arithmetic calculation based on data supplied from said data storing means based on said memory addresses.

2. A microprocessor comprising an instruction decoder for decoding a series of instructions of a program to output a series of instructions and a control signal, a pointer instruction memory controlled by said control signal for consecutively supplying address data stored in said pointer instruction memory, a memory pointer for receiving said address data to consecutively specify memory addresses, a data memory adapted to be addressed by said memory addresses and for storing data for an arithmetic calculation, and an arithmetic logic unit for receiving an instruction from said instruction decoder to execute the arithmetic calculation based on data supplied from said data memory addressed based on said memory addresses.

A microprocessor according to Claim 2, wherein said pointer instruction memory is a RAM.

A microprocessor according to Claim 2, wherein said pointer instruction memory is a ROM.

18 5.

A microprocessor according to any of Claims 2 to 4, wherein said control signal includes a pointer instruction enable signal for activating said pointer instruction memory and a pointer instruction transfer signal for instructing data transfer from said data memory.

6. A microprocessor according to Claim 5, wherein said pointer instruction memory is adapted to operate synchronously with said pointer instruction transfer signal.

7. A microprocessor substantially as herein described with reference to and as shown in Figure 4 of the accompanying drawings.