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GB2318663B - Hierarchical interconnect for programmable logic devices - Google Patents

Hierarchical interconnect for programmable logic devices

Info

Publication number
GB2318663B
GB2318663B GB9718147A GB9718147A GB2318663B GB 2318663 B GB2318663 B GB 2318663B GB 9718147 A GB9718147 A GB 9718147A GB 9718147 A GB9718147 A GB 9718147A GB 2318663 B GB2318663 B GB 2318663B
Authority
GB
United Kingdom
Prior art keywords
programmable logic
logic devices
hierarchical interconnect
hierarchical
interconnect
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
GB9718147A
Other versions
GB9718147D0 (en
GB2318663A (en
Inventor
Srinivas Reddy
Manuel Mejia
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Altera Corp
Original Assignee
Altera Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US08/840,113 external-priority patent/US5883526A/en
Application filed by Altera Corp filed Critical Altera Corp
Publication of GB9718147D0 publication Critical patent/GB9718147D0/en
Publication of GB2318663A publication Critical patent/GB2318663A/en
Application granted granted Critical
Publication of GB2318663B publication Critical patent/GB2318663B/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/17736—Structural details of routing resources
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/17704—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form the logic functions being realised by the interconnection of rows and columns
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/1778—Structural details for adapting physical parameters
    • H03K19/17796—Structural details for adapting physical parameters for physical disposition of blocks

Landscapes

  • Physics & Mathematics (AREA)
  • Mathematical Physics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Logic Circuits (AREA)
GB9718147A 1996-10-25 1997-08-27 Hierarchical interconnect for programmable logic devices Expired - Fee Related GB2318663B (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US2787496P 1996-10-25 1996-10-25
US08/840,113 US5883526A (en) 1997-04-17 1997-04-17 Hierarchical interconnect for programmable logic devices

Publications (3)

Publication Number Publication Date
GB9718147D0 GB9718147D0 (en) 1997-10-29
GB2318663A GB2318663A (en) 1998-04-29
GB2318663B true GB2318663B (en) 2000-06-28

Family

ID=26702975

Family Applications (1)

Application Number Title Priority Date Filing Date
GB9718147A Expired - Fee Related GB2318663B (en) 1996-10-25 1997-08-27 Hierarchical interconnect for programmable logic devices

Country Status (2)

Country Link
JP (1) JPH10233676A (en)
GB (1) GB2318663B (en)

Families Citing this family (24)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6100715A (en) * 1998-12-15 2000-08-08 Vantis Corporation Methods for configuring FPGA's having variable grain blocks and logic for providing time-shared access to interconnect resources
US6154051A (en) * 1998-11-05 2000-11-28 Vantis Corporation Tileable and compact layout for super variable grain blocks within FPGA device
US6163168A (en) * 1998-12-09 2000-12-19 Vantis Corporation Efficient interconnect network for use in FPGA device having variable grain architecture
EP1465345A3 (en) * 1999-03-04 2006-04-12 Altera Corporation Interconnection resources for programmable logic integrated circuit devices
JP2002538633A (en) 1999-03-04 2002-11-12 アルテラ・コーポレーション Interconnect resources for programmable logic integrated circuit devices
US6628140B2 (en) * 2000-09-18 2003-09-30 Altera Corporation Programmable logic devices with function-specific blocks
US7249242B2 (en) 2002-10-28 2007-07-24 Nvidia Corporation Input pipeline registers for a node in an adaptive computing engine
US7325123B2 (en) 2001-03-22 2008-01-29 Qst Holdings, Llc Hierarchical interconnect for configuring separate interconnects for each group of fixed and diverse computational elements
US7653710B2 (en) 2002-06-25 2010-01-26 Qst Holdings, Llc. Hardware task manager
US7962716B2 (en) 2001-03-22 2011-06-14 Qst Holdings, Inc. Adaptive integrated circuitry with heterogeneous and reconfigurable matrices of diverse and adaptive computational units having fixed, application specific computational elements
US7489779B2 (en) 2001-03-22 2009-02-10 Qstholdings, Llc Hardware implementation of the secure hash standard
US7752419B1 (en) 2001-03-22 2010-07-06 Qst Holdings, Llc Method and system for managing hardware resources to implement system functions using an adaptive computing architecture
US6836839B2 (en) 2001-03-22 2004-12-28 Quicksilver Technology, Inc. Adaptive integrated circuitry with heterogeneous and reconfigurable matrices of diverse and adaptive computational units having fixed, application specific computational elements
US7400668B2 (en) 2001-03-22 2008-07-15 Qst Holdings, Llc Method and system for implementing a system acquisition function for use with a communication device
US7046635B2 (en) 2001-11-28 2006-05-16 Quicksilver Technology, Inc. System for authorizing functionality in adaptable hardware devices
US6986021B2 (en) 2001-11-30 2006-01-10 Quick Silver Technology, Inc. Apparatus, method, system and executable module for configuration and operation of adaptive integrated circuitry having fixed, application specific computational elements
US8412915B2 (en) 2001-11-30 2013-04-02 Altera Corporation Apparatus, system and method for configuration of adaptive integrated circuitry having heterogeneous computational elements
US7602740B2 (en) 2001-12-10 2009-10-13 Qst Holdings, Inc. System for adapting device standards after manufacture
US7215701B2 (en) 2001-12-12 2007-05-08 Sharad Sambhwani Low I/O bandwidth method and system for implementing detection and identification of scrambling codes
US7403981B2 (en) 2002-01-04 2008-07-22 Quicksilver Technology, Inc. Apparatus and method for adaptive multimedia reception and transmission in communication environments
US7493375B2 (en) 2002-04-29 2009-02-17 Qst Holding, Llc Storage and delivery of device features
US7478031B2 (en) 2002-11-07 2009-01-13 Qst Holdings, Llc Method, system and program for developing and scheduling adaptive integrated circuity and corresponding control or configuration information
US7609297B2 (en) 2003-06-25 2009-10-27 Qst Holdings, Inc. Configurable hardware based digital imaging apparatus
JP2018042197A (en) 2016-09-09 2018-03-15 株式会社東芝 Semiconductor device

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2300951A (en) * 1995-05-17 1996-11-20 Altera Corp Programmable logic array with overlapping interconnection conductors

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2300951A (en) * 1995-05-17 1996-11-20 Altera Corp Programmable logic array with overlapping interconnection conductors

Also Published As

Publication number Publication date
GB9718147D0 (en) 1997-10-29
GB2318663A (en) 1998-04-29
JPH10233676A (en) 1998-09-02

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Legal Events

Date Code Title Description
732E Amendments to the register in respect of changes of name or changes affecting rights (sect. 32/1977)
PCNP Patent ceased through non-payment of renewal fee

Effective date: 20150827