GB2314673A

GB2314673A - Semiconductor device with quantum wires

Info

Publication number: GB2314673A
Application number: GB9613491A
Authority: GB
Inventors: Jeremy Henley Burroughes; Riichi Katoh
Original assignee: Toshiba Cambridge Research Centre Ltd; Toshiba Corp
Current assignee: Toshiba Europe Ltd; Toshiba Corp
Priority date: 1996-06-27
Filing date: 1996-06-27
Publication date: 1998-01-07
Anticipated expiration: 2016-06-27
Also published as: JPH1022498A; GB9613491D0; GB2314673B

Abstract

A cell for a semiconductor device comprises input means 69, 71 for causing the number of carriers in a first part 67 of a predetermined region to be different from the number of carriers in a second part 65 of the predetermined region. Output means 73,75 is provided for producing an electrical output dependent upon the relative difference in numbers of carriers between the first and second parts of the predetermined region. The input and output structures are formed as mesas and the carrier-producing region comprises a pair of quantum wires on an oblique facet of a GaAs multi-layer substrate with alternate n- and p-type layers . The cell can function as an inverter.

Description

SEMICONDUCTOR DEVICE The present invention relates to a semiconductor device in which carriers are confined within predetermined regions. There have been many proposals for devices in which carriers are trapped in a discrete puddle, e.g. at about 100 electrons. Such a puddle is commonly referred to as a "quantum dot" or "quantum box", although the carriers may exhibit classical or quantum behaviour, depending on confinement conditions. There are several ways in which quantum dots may be isolated.

Typically, a discrete region of a two-dimensional electron gas (2DEG) may be isolated by depleting-out surrounding areas using an appropriate gate arrangement.

Recently, it has been proposed (Craig S. Lent et al., "Quantum Cellular Automata" Nanotechnology, Vol. 4, pp. 49-57) that a logic circuit may be assembled without using three-terminal transistors such as bipolar transistors, but instead based on a cellular quantum dot arrangement.

Figure 1A and 1B of the accompanying drawings show an inverter circuit devised according to the aforementioned proposal, which is called "cell-connected inverter circuit." This comprises six quantum dot cells labelled C1 to C6. A 5quantum dot cell has five quantum dots D1 to D5, two of which contain one electron each, as illustrated in Figures 2A and 2B of the accompanying drawings. It can assume two recognisable, stable ground states T1 and W2 since the two electrons undergo Coulomb interaction and repel each other, trying to acquire a lower energy level.

The way in which this cell-connected inverter circuit operates will now be described with reference to Figures 1A and 1B. If an input of logical "1" is supplied to the quantum dot cell C1, cell C1 assumes the ground state T 1 Then, C2 will also assume the ground state T i since this means it electrically stable with respect to the cell Cl. Cell C3 likewise assumes the ground state T1 i since this is also electrically stable with respect to cell C2. On the other hand, C4 assumes ground state T2 in order to be electrically stable with respect to cell C3, and C5 then also assumes ground state T2 to be electrically stable with respect to cell C4. Finally, cell C6 assumes the ground state T2 to be electrically stable with respect to cell C5. As a result, the cells C 1 and C6, which are the input and output cells, respectively, assume different ground states. The cell-connected inverter circuit therefore outputs "0" when it receives an input of "1".

This cellular arrangement is relatively complicated to manufacture since each cell consists of five discrete quantum dots, as shown in Figures 2A and 2B. However, the present invention works upon a different principle whereby the distribution of carriers in one or more predetermined regions is influenced by the relative potentials applied to inputs of a cell. Thus, a first aspect of the present invention now provides a cell for a semiconductor device, the cell comprising means for isolating carriers within a predetermined region, means for causing the number of carriers in a first part of the predetermined region to be different from the number of carriers in a second part of the predetermined region, and output means for producing an electrical output in dependence upon the relative difference in numbers of carriers between the first and second parts of the predetermined region.

As described in more detail hereinbelow, an individual cell may comprise first and second predetermined regions, each respectively for isolating a group of carriers.

The input means can be arranged to determine the relative difference in numbers of carriers between the first and second parts of one of these predetermined regions and that in itself, causes a relative difference in the numbers of carriers between first and second part of the other predetermined region which is adjacent. The output means is then responsive to the relative difference in numbers of carriers between the first and second parts of this other predetermined region.

Conveniently, such pairs of predetermined regions isolating respective groups of carriers are elongate and are preferably arranged parallel to one another. In a described embodiment hereinbelow, each of these regions is preferably a onedimensional quantum wire of finite length. In any event, these pairs of regions of trapped carriers can be considered to be "quantum bars". The way in which such a pair of quantum bars may be used in a cell 1 according to the present invention, is shown in Figure 3 of the accompanying drawings.

A first quantum bar 3 and a second quantum bar 5 are arranged parallel to one another and relatively close, separated by a small gap 7. A first input 9 is arranged relatively close to one end 11 of the first quantum bar 3. A second input 13 is arranged close to the other end 15 of the first quantum bar 3. A second output terminal 17 is arranged close to a first end 19 of the second quantum bar 5 and a second output terminal 21 is arranged close to the other end 23 of the second quantum bar5.

As shown in Figure 3, a potential difference is applied across the input terminals 9, 13 so that the first terminal 9 is negative relative to a positive potential on the second terminal 13. This causes the carrier distribution in the first quantum bar 3 to be changed so that the first end 11 of the first quantum bar 3 becomes relatively positive, influenced by the negative charge on the first input terminal 9. Similarly, the second end 15 of the first quantum bar 3 becomes relatively negative under the influence of the positive charge on the second input terminal 13. As shown in Figure 3, the electron density in the quantum bars 3, 5 is indicated by heavier shading.

The relatively positive charge at the first end 11 of the first quantum bar 3 induces a relatively negative charge at the first end 19 of the second quantum bar 5.

Similarly, the relatively negative charge at the second end 15 of the first quantum bar 3, induces a relatively positive charge at the second end 23 of the second quantum bar 5.

As a result, the relatively negative charge at the first end 19 of the second quantum bar 5 induces a relatively positive charge on the first output terminal 17.

Similarly, the relatively positive charge at the second end 23 of the second quantum bar 5 induces a negative potential on the second output terminal 21. Thus, the cell 1 as illustrated can function as a simple inverter.

It is preferable for efficient transmission via the quantum bars if the quantum bars have a width of less than 2,em in a direction other than that of elongation. It is more preferable if this width is less than 1 cut. It is even more preferable if this width is of the order of the de Broglie wavelength of the trapped carriers. In this case the carriers will be confined in a purely 1 dimensional state and optimum transmission characteristics will be obtained.

The present invention also extends to a particular regrowth technology suitable for realising such quantum bar arrangements. Thus a second aspect of the present invention provides a method for producing a cell for a semiconductor device according to any preceding claim, the method comprising the steps of forming a first pair of mutually separated mesas for defining one of the input means and the output means, forming a semiconductor layer structure including at least one layer for defining the means for isolating carriers within the predetermined regions, forming a second pair of mutually separated mesas on top of the said semiconductor layer structure for defining the other of the input means and output means, etching the said semiconductor layer structure to reveal an oblique facet intersecting the layers of the structure, and forming a regrowth structure capable of supporting a two-dimensional electron gas.

Accordingly, the respective means for isolating the carriers within the first and second predetermined regions may be formed in an etched semiconductor wafer and the first and second predetermined regions are formed as respective regions of a semiconductor structure formed over the etched wafer. The means for isolating the carriers within the first and second predetermined regions may then be mutually separated layers of semiconductor material, different from the semiconductor material of those parts of the etched wafer with which they are in contact. These different types of semiconductor material may respectively be, semiconductor materials of different conductivity types or of different forbidden bandgaps. For example, they may be respectively formed of n-doped and p-doped. Which material has which conductivity type will depend on whether the majority carriers are electrons or holes. Instead of differently doped materials, there may be provided a semiconductor material of a relatively large forbidden bandgap, for example GaAs and instead of the n-doped material, there may be provided another semiconductor material of relatively small forbidden bandgap, e.g. AlGaAs in place of the p-doped material. Of course the device is not restricted to GaAs based heterostructures, for example, SiGe/Si or Si/SiO2 may be used as well.

The predetermined regions forming the quantum bars are in this way formed as isolated strips of a 2DEG which, under the appropriate conditions, may actually exhibit true 1D quantum wire behaviour. In any event, they may be formed as isolated strips of a high electron mobility transistor (HE MT) structure or any other appropriate structure capable of supporting a 2DEG. Here, the term "2DEG" is used to refer to all systems, where the majority carriers are either holes or electrons. Preferably, the structure formed over the etched wafer is such that a 2DEG can be formed within 100 A of the regrowth interface.

The input and output means can be defined by an underlying strip of semiconductor material (e.g. of appropriate conductivity type or forbidden bandgap) which is formed by growth and selective etching prior to formation of the other layers of the remaining aforementioned wafer which is then etched as mentioned above, prior to formation of the regrowth structure in which the quantum bars are to be induced.

Higher-order logic functions can be provided by more complex arrangements of quantum bars than the simple inverter arrangement shown in Figure 3. For example, mutually separated pairs of quantum bars may be arranged end-to-end by provision of another regrowth stage. Large mesas can be formed, each containing a respective pair of quantum bars. These are then separated by a region of the wafer which cannot support an electron gas. The quantum bars and input/output as appropriate, are then formed on each large mesa area, by the sequence of regrowth steps referred to above.

The present invention will now be explained in more detail, by way of the following description of a preferred embodiment and with reference to the accompanying drawings in which: Figures 1A and 1B show an inverter circuit devised according to a known proposal, based on a series of multiple quantum dot cells; Figures 2A and 2B show details of the quantum dots within the cells of the circuit shown in Figures 1A and 1B; Figure 3 shows the basic quantum bar arrangement for explaining a simple inverter cell according to the present invention; Figure 4 shows the layer structure of a wafer before a first regrowth step, for manufacturing a cell according to the present invention; Figure 5 shows a cross-sectional view through a mesa of the wafer shown in Figure 4, after a first etch step; Figure 6 shows a cross-sectional view between the mesas of the wafer shown in Figure 5; Figure 7 shows a plan view of the patterned wafer shown in Figure 5; Figure 8 shows a plan view of the wafer of Figures 5 to 7, after a first regrowth step; Figure 9 shows a cross-section through the n-GaAs mesas of the structure shown in Figure 8; Figure 10 shows an equivalent cross-section to that shown in Figure 9, but between the n-GaAs mesas; Figure 11 shows the plan view of the structure of Figure 8, after etching the top layer to produce two upper n-GaAs mesas; Figure 12 shows a cross-section through the n-GaAs mesas of the structure shown in Figure 11; Figure 13 shows a cross-section equivalent to that shown in Figure 12 but between the n-GaAs mesas; Figure 14 shows the structure of Figure 11 after a further etching step; Figure 15 shows a cross-section through the n-GaAs mesas of the structure shown in Figure 14; Figure 16 shows a cross-section equivalent to that shown in Figure 15 but between the n-GaAs mesas; Figure 17 shows the structure of Figure 14 after a further regrowth step; Figure 18 shows a cross-section through the n-GaAs mesas of the structure shown in Figure 17; Figure 19 shows a cross-section equivalent to that shown in Figure 18 but between the n-GaAs mesas; Figure 20 shows a sectioned perspective view of the completed device according to the present invention, as produced by the steps shown in Figures 4-19; Figure 21 shows schematically, a quantum bar arrangement for a typical higher level logic function; and Figure 22 shows in plan view, details of the mesa/regrowth arrangement for producing the kind of higher logic level function shown in Figure 20.

Turning now the Figure 4, there is shown a cross-section through a layer arrangement for producing a device cell according to the present invention. On a substrate 31, is produced a p±GaAs layer 33, on top of which is produced a n-GaAs layer 35. As shown in Figures 5 to 7, this is etched to produce n-GaAs mesas 37, 39 which are mutually separated and surrounded by the exposed surface 41 of the p+ GaAs layer 33.

Next as shown in Figures 8 to 10, over the patterned wafer as shown in Figures 5 and 6, is produced a first regrowth structure 43 which comprises, in order of formation, a p-GaAs layer 45, an n-GaAs layer 47 a further p-GaAs layer 49, a further n-GaAs layer 50 a final p-GaAs layer 51 and a final n-GaAs layer 52. The n-mesas 37, 39 cause corresponding raise portions 54, 56 to be formed in the upper n-GaAs layer 52.

Next as shown in Figure 11, the upper n-GaAs layer 52 is etched to produce respective upper n-GaAs mesas 58, 60 which are parallel to each other and extend above, and parallel to, the remnant lower n-GaAs mesas 37, 39, the space between and surrounding the upper mesas 58, 60 exposes the upper p-GaAs layer 51.

After formation of the upper n-GaAs mesas 58, 60 the wafer is subjected to a final etch as shown in Figures 14-16, to expose the remnant lower n-GaAs mesas 37, 39 and to form an oblique facet 53 intersecting the horizontal p-GaAs layers 45, 49, 51 and the horizontal n-GaAs layers 47, 50. The right hand portions of the upper n-GaAs mesas 58, 60 remain, above the termination at the oblique facet 53.

After this last etch, as shown in Figures 17-19, a second regrowth structure 55 is formed over the wafer. In order of formation, this second regrowth structure 55 comprises a barrier layer 57, and a HEMT structure 59 which includes a quantum well.

In use, the n-GaAs regions define the extent of free carriers within the structure.

Figure 18 shows a cross-section through the n-mesas 37, 60 and Figure 19 shows a cross-section corresponding to Figure 18, but taken between the n-GaAs mesas 37, 39 and 58, 60 respectively.

The completed device cell is shown in Figure 20. The n-GaAs layers 47, 50, define mutually separated quantum bars. The n-GaAs mesas additionally define respective inputs 69, 71 and outputs 73, 75 having the geometry shown in Figure 3 but with the quantum bars 65, 67 extending laterally across the inclined upper surface 77 of the second regrowth structure 55. The input regions 69, 71 are respectively contacted by shallow ohmic contacts with contact pads 77, 79. Similarly, the output regions (strips) 73, 75 are contacted by respective shallow ohmic contacts with contact pads 81, 83.

Turning now to Figure 21, there is shown a diagram corresponding to the basic quantum bar schematic shown in Figure 3. The same reference numerals are used as for the inverter circuit 1. However, in this case, in line with the quantum bars 3, 5 are arranged two further quantum bars 2, 4. Additional outputs 6, 8 are shown adjacent to the second of these further quantum bars 4, with the same spacing and orientation of outputs 17, 21 with respect to quantum bar 5. It will be seen that the alteration of charge distribution follows the same principle as that explained with reference to Figure 3.

The kind of structure shown in Figure 11 may be made by introducing a further regrowth stage to the basic method explained with reference to Figures 8-9. This is explained with reference to Figure 22. On a wafer 91, two structures are fabricated, each comprising a respective pair of quantum bars 93, 95 and 97, 99. Two pairs of lower mesas 101, 103 and 105, 107 are shown in broken line form. Corresponding upper mesas 109, 111, and 113, 115 are shown as solid lines. However, another etch/regrowth stage is carried out so that each respective pair of quantum bars 93, 95 and 97, 99 exist separately on a respective intermediate mesa 117, 119. The etch to form the oblique facet is shown as "E".

Since no electron gas is sustained in the intermediate zone 121 between the intermediate mesas 117, 119, the two pairs of quantum bars 93, 95 and 97, 99 are effectively separated, corresponding to the arrangement shown in Figure 11.

In a variant of the preferred embodiment described above, the p-GaAs layers 45, 49, 51 of the first regrowth 43 could be formed of AlGaAs and the interspersed n-GaAs layers 47, 50 could be formed of GaAs. Moreover, in the third regrowth stage, the HEMT structure 55 could be preceded by a thin (eg < 200A) GaAs layer grown directly over the inclined facet 33. The input and output n-GaAs layers 54, 56, 58, 60 could be replaced by respective ohmic contacts to the electron gas.

In the light of this disclosure, modifications of the described embodiment, as well as other embodiments, all within the scope of the present invention as defined by the appended claims, will now become apparent to persons skilled in this art.

Claims

1. A cell for a semiconductor device, the cell comprising means for isolating carriers within a predetermined region, input means for causing the number of carriers in a first part of the predetermined region to be different from the number of carriers in a second part of the predetermined region, and output means for producing an electrical output in dependence upon the relative difference in numbers of carriers between the first and second parts of the predetermined region.

2. A cell according to claim 1, wherein the predetermined region in which carriers are isolated is a first predetermined region, further means being provided for isolating carriers within a second predetermined region, whereby the input means functions to determine the relative difference in numbers of carriers between the first and second parts of the first predetermined region which determines the relative difference in numbers of carriers between first and second parts of the second predetermined region so that the output means produces the electrical output in dependence upon the relative difference in numbers of carriers between the first and second parts of the second predetermined region.

3. A cell according to claim 2, wherein each of the first and second predetermined regions is elongate.

4. A cell according to claim 3, wherein each of the first and second predetermined regions is a one-dimensional quantum wire of finite length.

5. A cell according to any of claims 2 to 4, wherein the respective means for isolating carriers within the first and second predetermined regions are formed in an etched semiconductor wafer and said first and second predetermined regions are respective regions of a semiconductor structure formed over the etched semiconductor wafer.

6. A cell according to claim 5, wherein the respective means for isolating carriers within the first and second predetermined regions are mutually separated layers of semiconductor material which is different from the semiconductor material of those parts of the etched semiconductor wafer with which they are in contact.

7. A cell according to claim 6, wherein the mutually separated layers are formed of a semiconductor material of a first conductivity type and the semiconductor material of those parts of the etched semiconductor wafer with which they are in contact is of a second conductivity type.

8. A cell according to claim 6, wherein the mutually separated layers are formed of a semiconductor materiai having a first forbidden bandgap and the semiconductor material of those parts of the etched semiconductor wafer with which they are in contact has a second forbidden bandgap.

9. A cell according to any of claims 5 to 8, wherein the said semiconductor structure is a high electron mobility transistor structure.

10. A cell according to any of claims 5 to 9, wherein the input means and the output means are defined by regions of semiconductor material buried within the said etched semiconductor wafer.

11 A cell for a semiconductor device, the cell being substantially as hereinbefore described with any of Figures 3-12 of the accompanying drawings.

12 A method for producing a cell for a semiconductor device according to any preceding claim, the method comprising the steps of forming a first pair of mutually separated mesas for defining one of the input means and the output means, forming a semiconductor layer structure including at least one layer for defining the means for isolating carriers within the predetermined regions, forming a second pair of mutually separated mesas on top of the said semiconductor layer structure for defining the other of the input means and output means, etching the said semiconductor layer structure to reveal an oblique facet intersecting the layers of the structure, and forming a regrowth structure capable of supporting a two-dimensional electron gas.

10. A cell- according to any of claims 5 to 9, wherein the input means and the output means are defined by regions of semiconductor material buried within the said etched semiconductor wafer.

11. A cell for a semiconductor device, the cell being substantially as hereinbefore described with any of Figures 3-12 of the accompanying drawings.

12. A method for producing a cell for a semiconductor device according to any preceding claim, the method comprising the steps of forming a first pair of mutually separated mesas for defining one of the input means and the output means, forming a semiconductor layer structure including at least one layer for defining the means for isolating carriers within the predetermined regions, forming a second pair of mutually separated mesas on top of the said semiconductor layer structure for defining the other of the input means and output means, etching the said semiconductor layer structure to reveal an oblique facet intersecting the layers of the structure, and forming a regrowth structure capable of supporting a two-dimensional electron gas. Accordingly, the respective Amendments to the claims have been filed as follows CLAIMS 1. A cell for a semiconductor device, the cell comprising means for isolating carriers within a predetermined region, input means for causing the number of carriers in a first part of the predetermined region to be different from the number of carriers in a second part of the predetermined region, and output means for producing an electrical output in dependence upon the relative difference in numbers of carriers between the first and second parts of the predetermined region.

8. A cell according to claim 6, wherein the mutually separated layers are formed of a semiconductor material having a first forbidden bandgap and the semiconductor material of those parts of the etched semiconductor wafer with which they are in contact has a second forbidden bandgap.