GB2310940A - Inverting refresh circuit for an amplifying DRAM cell in an FPGA - Google Patents

Description

DYNAMIC MEMORY INTEGRATED CIRCUIT STRUCTURE is 2310940

The present invention relates to the field of semiconductor devices and methods of operating such devices. More sp;ecif ically, in one embodiment the invention provides a field programmable logic device with dynamic memory control.

The expense of designing integrated circuits for special applications has ser-ved as an incentive to develop several ways of using standard circuits that may be modified by a user to perform particular functions. Gate arrays are an example of an integrated circuit that may be modified to satisfy a special user need using, for example, laser programming. This solution is still too expensive for many limited production runs and in prototype design. To overcome this limitation field programmable gate arrays (FPGA) were developed.

In the earliest field programmable gate arrays, the functions of logic cells and the interconnections between cells were controlled by flipflops. The flip-flops were loaded with a configuration program entered from the outside of the chip. Once this program was loaded, the standard chip was customized to perform specific functions.

In later designs various means for customizing the array functions have been utilized. Among the methods proposed are the utilization of "anti fuses", which is the reverse of using fuses or "cutpoints." Another common logic circuit today utilizes static ram flip-flops to control the array functions. Typically long shift registers with shift and hold function's are used in such devices to load the control bits into the arrays. Another type of field programmable gate array utilizes EPROM or EEPROM cells to define the logical function to be performed by the device.

While meeting with substantial success, prior devices have also met with certain limitations. For example, such devices typically occupy more semiconductor area than would be desirable and, therefore, are more costly and difficult to manufacture.

From the above it is seen that improved field programmable gate arrays and methods of operating such devices are needed. The invention provides a dynamic memory integrated circuit structure, which, in preferred examples, has particular application in FPGAs.

In accordance with the invention, a dynamic memory integrated circuit structure comprises:

a storage capacitor, a first plate of said storage capacitor coupled to a gate of an access transistor, a second plate of said storage capacitor coupled to a first terminal of said access transistor; a read transistor, said read transistor having a first terminal coupled to a second terminal of said access transistor and second terminal coupled to a bit line; a restore transistor, said restore transistor having a first terminal coupled to said bit line and a second terminal coupled to said first plate of said storage capacitor; and an inverter circuit having an input selectively coupled to said bit line and an output selectively coupled back to said bit line.

This structure may be used in improved configurable logic devices in which the charge level of a capacitance is used to control the state of the controlled nodes in a gate array or other logic device. The capacitance's only function is to hold a is charge long enough to "remember" if it represents a one or a zero until it is read and refreshed.

The control of gates and switches by the capacitances requires a steady and well defined signal level on the capacitance that is not generally compatible with conventional dynamic ram capacitors. Examples are described which overcome the effect of the dynamic voltage variations in a storage capacitance so that dynamic memory cells reliably control switches and gates in a programmable logic devices. Several alternative methods are presented, all of which mask the voltage transients imposed on the memory capacitors typical of DRAMs. In preferred embodiments, the refresh of the dynamic memory cells and the "read" of the cells by the logic device may occur simultaneously since voltage transients on the stored capacitance are minimized during refresh. Accordingly, in most preferred embodiments, the refresh and read need not be synchronized to avoid the simultaneous occurrence of these events.

The described examples can result in programmable logic with substantially smaller memory cell size. For example, a typical SRAM cell in presently manufactured devices could occupy about 335 square microns. SRAM area on a typical programmable logic chip would be in the range of 31% of chip area. By contrast, the described examples may result in estimated cell areas of between about 45 and 67 square microns. Therefore, device size would be reduced by about 80% of 31%, or about 25-.. Obviously, with significant chip size reductions, attendant changes will result in device capability and/or yield.

There follows a description of examples of configurable logic devices and also of a dynamic memory structure embodying the present invention 9 incorpbrated in such a logic device.

Figs. 1A and 1B are overall illustrations of a is dynamic configurable logic device (DCLD); Pigs. 2A and 2B illustrate a look-up table device for use in association with a programmable logic device operating under the control of dynamic memory cells; Fig. 3 illustrates one form of a memory cell; Figs. 4A and 4B illustrate disturbance of a "one' and a "zero" on a memory cell; Figs. 5 to 10 illustrate other forms of memory cells; Fig. 11 illustrates aspects of the sense and load portions of the memory in the DCLD; Figs. 12 and 12A illustrate the programming portion of the device in greater detail; Fig. 13 illustrates details of a data loading circuit; Fig. 14 illustrates a half cell design which embodies the present invention; Fig. 15 illustrates the use of dummy memory cells; Figs. 16A and 16B illustrate other DCLD arrangements; Fig. 17 illustrates a circuit for producing Vdd+; Fig. 18 illustrates a bootstrap circuit; Fig. 19 illustrates a Vdd++ generation circuit; Fig. 20 illustrates a strobe using Vdd++; and Figs. 21 and 22 illustrate another arrangement.

Although the invention claimed herein relates only to a particular form of dynamic memory integrated circuit structure, the structure has particular, though not exclusive, application to DCLDs. Various arrangements of DCLDs will be described in the following which include memory cell designs which are - 5 is not examples of the claimed invention. It will be apparent to those skilled in the art which of the described DCLD arrangements can incorporate examples of the invention.

Reference should also be made to the following co-pending applications which claim subject matter disclosed in this application:- Application No. 9518093.1 (the parent application) which claims programmable logic in an integrated circuit comprising:

logic means for outputting signals representative of desired logical functions of inputs to said integrated circuit; means for inputting data to an array of capacitance means for storage of selected voltage levels thereon representing said data, said data being representative of a desired logical function of said logic means; means for refreshing selected voltages in said array of capacitance means, each of said capacitance means comprising a control voltage node coupled to said logic means to supply said data to control said logic means to provide said desired logical function; means for supplying said data from said control nodes while refreshing said selected voltages in said array of capacitance means, whereby logic functions may be performed with said logic means when said capacitance means are being refreshed, and means for reading stored data from said capacitance means whereby data stored in said capacitance means may be verified.

Application No. T.TI0i44.8 (a further Divisiona application) which claims a method of operating a dynamic memory comprising the steps of:

precharging a selected bit line in said dynamic 6 is memory to a selected value with a precharge circuit, said bit line coupled to a sense amplifier comprising a pull up portion coupled to a selectable high voltage source and a pull down portion coupled to a low voltage source; decoupling said bit line from said precharge circuit, whereby said bit line floats; coupling said bit line to a memory cell by bringing at least one word line to a first word line voltage level while applying a first high voltage to said pull up portion; and thereafter, applying a second, higher voltage to said pull up portion while raising a voltage on said at least one word line to a second, higher word line voltage level.

CONTENTS I. II.

III.

iv.

V.

vi.

General Memory Cells Sense/Load/Refresh Additional Features A. Dummy Cell Embodiment B. Half Cell Dynamic Memory C. Four-Phase/Floating Bit Line Embodiment Peripheral Circuits A. Pump Circuit B. Bootstrap Circuit C. Secondary Pump Signal/Noise Level Considerations A. Noise Level Reduction.

I. Genera, Dynamic mwory cells are used in the operation of logic such as a wogrammable gate array. The effect of the dynamic voltage variations in the memory cells of a dynamic mamry device can be averccme such that the dynamic rramry cells can reliably control switches and gates in mvgrammable logic devices, such as FPGAs.

Several alternative methods are presented, with a common goal of masking out the voltage transients imposed on the memory capacitors typical for dynamic memory. An overriding goal iz of course to reduce the circuit area and thereby the cost of controlling the functions of the FPGAs.

Fig. 1A is an overall illustration of one embodiment of a dynamic memory conf igurable logic device 1. As shown. the device provides an array of dynamic memory cells 3 that are periodically refreshed by programming/refresh means 6. all contained on a single intecrazed circuic structure 10. The integrated circulc structure furtner includes logic devicets) 1.2 that are controlled by various control nodes CN in the dynamic memory. The logic device 12 provides outputs that are logical functions of inputs wherein the logical functions are based on the state of control nodes W in the dynamic memory. Of course. in most devices the memory and the logic will be.physically intermixed such that the memory will be in close pr=imity to the controlled device.

Fig. IB provides a simplified version of a device such as the one shown in Fig.!A in which logic inputs are selectively passed throuch switches controlled by dynamic memory cells. As shown therein. various inputs such as inputs IN, and. optionally, art.-.oconal inputs IN, are provided to the device. it will be recognized that many such inputs will normally be provided. although only two are illustrated for simplicity. often. both the true and complement c! inputs will be generated and provided to the logic device as indicated in the Figure.

As dynamic memory cells M are used w direcz selected 4nputs to one or both of AND gate(s)!3 andlor OR gate(s) 15. For examnle. if it is desired to provide the AND gate 13 with IN as a X product tern. M,, and M3 are programmed high. if it is desired to provide IN, as an input to OR gate 15. M, is also programmed high. Similarly, M, can be used to steer 1b4, cc the inputs of gates 13 and v 15. etc. MS may be used to transfer data tclfrcm a horizontal line -x.x lgr--Mlto a vertical bus 1-4ne 14 that intersects many innuz lines.

M3 and Ms are used fcr isolation of the gates when a signal is to be =ansferred to che vertical bus. but not to the input of a gate. -.'.n e device illustraced in Fic. iS can be viewed as d..mnamic nemory cells zo acdress various znmuzs J= use in AND cr ctner logic io 7 8 is gates and for connecting segments of data buses. horizontal and vertical.

Conversely. as illuscrated in Fig. 2A. the inputs can be used ro address selected memory cells. the scared value outputs of which are utilized in a logic function. Like the device illustrated above. this device also includes one or more arrays of dynamic memory cells 3. The me ry cells are programmed and periodically refreshed with programlrefresh circuit 6. Various inputs 1 are provided to a cell selection circuit 4. which selects a value stored in one or more of the memory cells f or output. For example. it all of the inputs are asserted, this may indicate that the valiAe of the 2n, th cell is to be output. 11 this cell has a high value. the output will be high. If this cell has a low value stored therein. the output will be low.

The outputs are normally combinatorial functions of the various input values. A simple example is provided below. Assume that two inputs are to be provided. The truth table that a particular user desires is:

Input 11 0 0 1 1 0 0 1 1 The combinatorial function described by this cable is O.A.BiA.a. Accordingly, four memory bits would be provided in the DRAM 3 in this simple example. Those with addresses& 11 (corresponding to A high and B high) and 01 (corresponding to A low and B high) would be set high. Others would be low. When either of these addresses is applied to the inputs. the output will be high; otherwise the output will be low. Accordingly, it is seen that dynamic memory may be used to implement combinatorial logic functions.

Additional functionality will normally be provided by the device. For example, output circuit 9 may be used to select betwe" registered and nonregi3tered output. Memory 3 may, therefore. have additional bits that serve an architecture control bits. For exantple. one architecture control bit may be used to select between registered and non-registered output in the output block 9.

Since the outputs are generated by providing the various inputs as an address to a particular memory bit in the array, the number of memory bits needed will depend at least partially on the number of inputs that are to be provided. Normally 2n or more memory bits will be provided, where n is the number of inputs to the array. Of course, the invention may readily be furt.her modified to provide multiple outputs. provide feedback. and the like. in which case much laxger numbers of bits may be utilized- Innut 12 Outrus 0 0 9 is -i 5 Fig. 23 provides a scnemat, c illustration of hardware that would be used in association wich the device shown In Fig. 2A in greater detail. A simple two input logical device is used for illustration. As shown therein. four memory bits 101 are used in the DRAM 3. The inputs I are connected cc define each of the possible co=inator-4al functions of the two inputs. For example. the output of the line 7 defines the function 11I2'B4 Accordingly. bit 34 is programmed to provide a high output to its control node CN in the case where 1, -1 is desired as onc of the product terms of the 2 =minatorial function. The outpuz 0 will be the logical OR of all of the product te=a designated by the variOU.S memory bits 8. For the particular truth table shown above. the control bits B3 and B4 would be set high and the remaining bits would be set low cc generate the logical function - 1112+1.12. Of course. additional ele nts may be provided. such as buffers on the memory cell control nodes CN or on che output nodes that are not shown for simplicity.

11. Memory cells Fig. 3 shows one typical dynamic memory cell 101.

A high or a low voltage is stored in a capacitance 103 depending on whether a ONE or a MM, respectively, is located on the memory cell. The memory cell voltage is Oreadw in the present invention via the control node CN that in located between a memory cell transistor 105 and the capacitance 103. The voltage scored on the memory cell capacitance will determine the logic function to be performed by a logic device. The capacitance 103 may take the to= of. for exa=le. a conventional capacitor or parasitic capacitance.

Due to the leakage of charge from che capac-.zance its charge must be retreshed periodically. Refreshing is acc=apli3hed by addressing the memory cell via a word line. reading the charge level stored thereon. and applying the correct refresh voltage to the bit line. For example. in the embodiment shown in Fig. 3 the word line is brought high. rendering cransistor 105 conductive and coupling the capacitor to the bit line. The appropriate high voltage is developed on the bit line via a sense amplifier 107 for restoration of the full charge on the capacitor when a 1 is stored. or the bit line is brought to ground when a 0 is stored.

At the m=ent of reading before refreshing a small amount of charge is drawn from the capacitor. This charge is replaced quickly, but the voltage on the capacitcr is momentarily disturbed as indicated in Fig. 4A. wherein the voltage level at the storage node,z shown cc be disturbed downwards when a "I" is stored on the capacitor. Conversely, as indicated in F-4C. 43, che voltage at the z=nzrc-; n=ce c.: a capaci=cr wicn a.,C. sr-crea c.nereen:.s normally is disturbed upwards since che bit lines are cypically prec.narged to an intermediate voltage becween the 0 and 1 levels. The cell as shown in Fig. 3 can be used directly if the circuit logic is syncnronized with the refresh cycle so that the logic system reads the capacitor voltage during times when the capacitor voltage is not disturbed for refresh. In practice this limics operating speed. increases circuit c=plexity, and otherwise negatively impacts the device. Therefore. it is desirable to utilize ocner merhods of refreshing the circuit while still maintaining the ability to utilize the capacitor voltage in a logic circuit, even when the cell voltage is impacted during a refresh operation.

The noise amplitude is reduced to acceptable levels such that the logic circuit will reliably read the capacitor voltage during either the disturbed or undisturbed portion of the cycles shown in Fig. 4. in general larger capacitors and shorter bitlines a, but will still rt in smaller overall chip areas than other logic devices.

Fig. 5 shows another memory cell that may be utilized.

In this embodiment. an extra transistor 501 is introduced with its gate connected to a stroben signal. The transistor 501 separates a memory capacitor C2 from a refresh capacitor C, except when the strobe signal is activated. Therefore. the circuit separates capacitor C2 from the capac4tor Cl during the time of the refresh disturbance. C2 may be a very small capacitor (such as about 10-20 fF using current device technology). and in some embodiments may only be the load capacitance of the controlled logic gate. while Cl is large enough (e.g., 30-50 fF using current device r-ec.lincloa_y) to provide a reliable reading in connection with the refresh cycle. During refresh. transistor 501 is off. and isolates the memory capacitor f=m the refresh disturbance. Therefore. also during refresh the voltage an capacitor C2 may be used in the device logic as a control signal. The strobe signal goes active after the capacitor Cl has been refreshed, such that the capacitor C2 is also refreshed. When the strobe is active. the voltage on C2 is supported by the charge fr= C,. The strobe can be a global signal or -4,- can be active only for a row chat has just been refreshed.

In either case che programming logic will preferably enable the strobe function so that both C2 and C, would be fully charged when the artcinal control pattern or data are written into the array. The advantace of this arrangement is cnat even 'f C2 is unusually large. which could occur for long co=ec=ing lines. C2 would be fully charged. individual st=cme lines fcr eacn row will reduce the dvn=i-- power consumption.

11 Fig. 6 illustrates another memory cell that may be used In this case. the.word line is is used as a strete by replacing the N-channel transistor 501 with a P- channel depletion mode transistor 601. Accordingly. during refresh. the ward line is high, providing charge to the capacitor C 1 After refresh. the word line is brought low. perraitting charge to f low f rom C, to C2. Again. the voltage at C, may be used at any time (during refresh or not) in the device logic.

The ref resh disturbance on the me=ry capacitor can also be filtered out using the traditional RC filter as indicated in Figs 8. and 9.In the embodiment in P 1g. 7. a resister R in formed between the memory cell capacitor C and the cell transistor 105. The relation between R and C will be set such that R is small enough to give suf f icient signal to the sense amplif ier. but lane enough to filter out the voltage swing on the bit line during the read refresh cycle such that the swing does not exceed a desired level. For example. using conventional. present technology R will be about 100 kC. The associated amplifier's speed of response will be increased when the bitline capacitance is low and the transistors in the amplifier are lane. This is accomplished if the number of bits per bit line is minimized. The memory cell capacitor and the resistor must still he relatively large.

In the embodiment eh in Fig. 8. a resistor R is provided between memory capactor C2 and refresh capacitor C,. The arrangement according to Fig. 8. with C, and C2 of approximately the same size. has the advantage that the instant signal to the amplifier is much larcer when the wordline is accessed. Therefore the ampl41Jer response time is shorter. shortening the duration of the distur-"ance on Cl. The filtering R-C2 time constant can therefore be shorzer. The size of resistor R depends to a high degree on the available processes. but with present device technology will be about 100 kg. The resistor can of course be replaced with a long and narrow switching transistor 105 an Indicated in Fig. 9.

Fig. 10 illustrates another memory cell according to one aspect of the invention. In this embodiment. depletion mode, N-channel transistors 1001 and 1002 are utilized. In essence. the devices 1001 and 1002 make up a resistorlcapacitor circuit similar to that shown in Fig. 8. The transistor 1001 has its gate tied to the sourceldrain of transistor 1003. The resistor Can be made up of two such devices connected as indicated in Fig. 8.

Ill. Sense/Load/Refrech A sense. load. and refresh c-4--c'jiz is illustrated in Fig. 11. This particular embodiment is adapted for the memory cell arrancement shown -- Fig. 5. M shown cl"ere are two rows of sense 12 ic 11101 and 1103. one row fCr C:e upper half of the array and one row f--r:-e lower half of the array respectively.. The device uzilizes!clded bit lines in which one bitline reads and restores cells addressed by even numbered word lines and the other ditline reads and restores cells addressed by odd numbered word lines. The bit lines extend in the same direction from the sense amplifier.

whIch provides alpha particle error protection and other beneiits.

Each is a CMOS sense wTlifier of the type well known to those of skill in the art of dynamic memory design and contains two cross-ccupled pairs of transistors including a cross-coupled pair of NMOS transistors 11-07 and a cross-coupled pair of PM05 transistors 1109.

Each row of amplifiers is powered by two buffer drivers 11-11 and 1112 with complement outputs. When the amplifiers are active. the sources of the N-channel transistors N1 and N2 are c=nected to around and the sources of the P-channel craisistcrs PI and P2 are connected to a positive supply voltage. As will be discussed later. this positive supply voltage is preferably higher than the Vdd n=ally used in the chip. Accordingly. when the a=!..;:!-,;ers are active (i.e., when 1112 produces a high potential and 1111 produces a low potential). the higher of the two bit lines in broug-.z -0 Vdd or above, while the!owe=, of the two bi: lines is brought:c ground.

When the polarity of the buffer drivers is reversed. the bit lines will be precharged to an intermediate voltage between 0 and V_ near the switchIng points of the c==ss-ccupled pairs. typically a potential close to half of the supply voltage. Transistor N3 is also zurned = durina a precharge mode. brinaing the ticline pair to the same potential.

During a refresh of a memonry cell. its ward line is brought high and the sense a=lifier is activated. At essentially the same time the selected word line is brought high, z.te strobe signal is br--ucnz low. The selected memory capacitor, if at low potential will pull its bitline low enough to cause the flip-flop to switc.-.:c the Icw potential on the selected bit line. On the other hand if the selected memory capacitor is at high potential the selected -,,-.t!-4ne will swing to the posicive potential. thus re-fresning the high charge on the memory capacitor.

Proarammina data are fed into the chip via a shift register When the recister has been filled. the shifting stops and Z!te recister holds izz data until che refresh starts. At the same tz. -ne as:he a=lifiers iiii and 1112 are activated. a Write uz)per" cr a Wrize Lower" sianal is applied. This will connect the -=pp=.==riace ncr- es = zne sni!z recister zn tne sense a=lifier and =ne sense z= store a i =r a state = the memory 13 C) is _; 5 canacizors along tne activated word line. For example. i! the data shifted into the shift register produce a low voltage at node 1.115 and WRITE UPPER is activated while WL1 is active. a low voltage level will he scored in memory cell 101. In alternative embodiments. reading of data by the logic array from the capacitors during the loading of data will be disabled.

The polar, ty requirement is dif f erent!or the bit lines asso=ated with the even and the odd word lines since, in preferred e=cd-4menzs. a single bit will comprise change of opposite polarity stored on bcch of the adjacenc bit.lines. Data are therefore c=rple-onented before feeding the shift registeLr for either the even or odd word lines. The lower half of the array is a mirror image of the upper half.

Fig. 12 illustrates a dynamic shift register 1201 used !or seauential addressing of the word lines as part of a refresh and data lcad fz.-.czicr..:a cnis particular embodiment. each ward line WLi.; has its own scrome line S;. The shift register 1201 is set up so that it can only circulate one ZERO bit. with all other bits - ONE (i.e.. high). The position where t.he zero. represented with a low level. occurs will bring the associated strobes low. For example.

when the low signal is at node 1203. other strobes such as S. will be high. During this mime. the memory capacitors C, will be refreshed.

When the strobe line later goes high. the zero shifts to the next position. and the memory cell C, will be connected to C2 by the high strobe line. The word line associated with the low strobe line will inicially be low. Then, when 02 is high. the word line (e.g.. WL0.

WL1. etc.) associated with the low strobe (e.g., STIROSE 0. 51. etc.) a-ces high via NOR 1211. permitting re-fresh of the associated canaciz--rs C, The hich word line then retu=. s to normal. and 0, is activated. clocking the low signal cc the next shift register location. Accordingly, memory capacitors C2 are refreshed along sinale word lines in a serial fashion beginning with ward line 0.

zrackina- the circulating zero.

Fig. i2A illustrates the t-4.ning of the 01, 02. WLI. VC.. VC2 and S! sicnals discussed above duri= the refresh of the C, and C2 capacitors along the WL1 word line as che low signal passes chrougn node!2C3. When 02 goes high, c.lie low voltage signal is generated at node i203. bringing 51 low and beginning refresh. Later. 01 goes hich taking the low bit cc the next stage. t2 then again goes high. bringing node 1203 high again. along with S!. Refresh occurs when WLI is high. When cne low signal reaches che iasr strcze -7-;ne S_ this generates the signal LAST WL bar -nJinultaneously. As shown. c.te voltace an C, is momentarily distu=zed wnen znw word;!-;ne -s hich. However.:.-e vclzac-:e on C, is!a-gely,=cL---wtur=ea.

14 0 Fig. 12A also shows the preferred timing for a global sz--cbe sianal. which replaces the individual strozes 5,...s n The ' w szrcL-e returns positive while the word line is still hign. securing full refresh on both C. and C-). The same tJming on individual szrctes can be arranced at a; lightly higher cost.

Fig. 12 also shows a two stage shift register 1205 that s used to keectrack of odd and even addresses. The Shift register is clacked with 01 and 02. If. for example. EVEN begins high, and after 0, and t2 have been high, the register will Clock the signal ODD high. This will repeat until LAST WL bar has gone high, resetting the register to its initialized state via mws 1207 and 1209. Alternative circuitry such as a coggl; fliP- flop may also be used for this purpose. it is assumed that the address shift register is duplicated for both halves of the array, for the case when the arranaement in F-4c.!I is used. An even number of word lines is illustrated. so that when the last ward line (WLn). which is odd. shifts the c_trculating low to the f irsz word line (WLO), the odd-even register shifts to generate the signal EVEN. Both shift registers have provisions to block forbidden bit combinations by secting a I to all but the f-4rsz position at the last word line rime. The registers can also be set:a WLO and EVEN when a load request is sent to the chip.

Fig. 13 shows an example of the type of control that can be used to communicate with outside for loading of data onto the chip. A load request signal LOAD REQ is applied by the user and is synchronized to the refresh clock which is internally generated on the chip. A signal LOAD ENABLE is returned to the programmer and will stay on one ciccK cycle beyond when LOAD REC stays active. LOAD REC is clocked into flip-flop 1301 with clock 02 and. thereafter. to recister 1303 with the next 02 clock. The user also provides a sianal to indicate whether data are to be written to the upper half of the chip. UPPER HALF. Using NAND 13IS, when WRI7E UPPER HALF and LOAD REC are high, the WRITE UPPER signal will be high during 02, allowing data to be written into the upper half of the array. Alternatively, when WRI-IE UPPER;is low. data may be written to the lower half of the array since WRITE LOWER will be high using NOR cares 1305 and 1307, resnectively.

This circuit also generates SEET WLO bar. When LAST WL bar is received. the wRiT"-c UPPER and WRI7E LOWER sicnals will be deactivated by the controlling system bu=,-4nc load request low.

he data shift register is advanced by clock signals from the prngrammer, 012 and 02D. This clock will be run in Dursts. each burst transferring as manv bits as the register holds (as many as the n..L=er in eacn r=w) As sncwn. zne data arc provided ar.:)A7A:N. and are inverted with XOR gaze 1-209 wic- a sicmal EVEN, c is which indicates that an even row is being addressed. For test purposes it is desirable to read scored data. READ TO SR is used to check the stored data values. READ DATA OUT may optionally be used to check the data after passing through the registers.

There is a window in the refresh cycle during which data can be loaded. This is defined by the LOAD WINDOW signal. that is produced by NAND 1311 and inverter 1315 based on 02 bar. As as long as LOAD REQ and the accepted LOAD REO output from flip-flop 1301 are active. the LCAD WINDOW is open once each refresh cycle (during 02 bar). Naturally, the clock frequency for loading data must be high enough to complete the loading before the window is closed.

When the last word line has been written a STOP LOAD signal is sent to the programmer via NOR gate 1313 based on LAST WL bar and the data outputs of the flip-flops 130111303. If at this time both the upper and the lower halves have been programmed the programmer brings the LOAD REQUEST signal down.

It may be desirable to verify that the correct data has been stored in the control memory. Read and modify operations may also be used to modify only selected cells. To accommodate this. provisions are added to che on- chip control logic and to the DATA IN shift register. For the external programming system where the chip is used to "know the row address. the last WL signal and one of the refresh clocks are connected to 1/0 pins. This is illustrated in Fig. 13. The system keeps a separate row count, thus permitting the system to read or write data from or to any row synchronously with the refresh cycle.

TO read data out. the procedure is as follows. The DATA IN shift register is shifting slowly during normal refresh cycles under control of the refresh clocks (this prevents floating gate situations cc cause excessive current drain). At the end of the 02 time associated with the row to be read. a READ TO SR pulse is applied to an input pin. As exemplified in Fig. 14. this copies the data read by the sense amplifier to the shift register. After the end of 02 and after the READ TO SR pulse. the internal 1 and 2 clocks are replaced with the fast shift clocks Old and 02d, causing the read data to be shifted out.

A read-modif y- write operation can be arranged as follows. The ol and 02 Clocks can be timed far enough apart so that two co=lete shifts of data can take place without interfering with either clock. Data are shifted out to the system bit by bit and returned to the input of the data register on che chip. As the bits pass through -the system. old data bits can be replaced with modified ones. if desired. After one complete cycle a data load pulse. reolacIng the 0.) 2.ZATALD oulse indicated in Fic.!4, transfers the new data to tne sense amnlifier. The new data is now on the sense 16 amplifiers cutput before che arrival c'.; the 1 clock used cc restore charge cc the memory capacitor. Alternatively che full content of the shift register can be shifted ouc.,ncdified and s hifted in durinc one refresn cycle. Only if more time consuming data =di!---az-,ons are made. will it be necessary to waic for the rev to return after a full sequence of refresh cycles.

iv. Addlit-inr.ia1 Features A. -Dumrv Cell Embodiment Fig. 15 illustrates an arrangement using the basic DRAM cell combined with adu=ny cells. A wordline will in a typical array be very long and with high capacitive load. The line. preicrably driven from a pumped voltage source. will have a slow rise time. The c-,me connecting a capacitor at low voltage level to its bit line is much earlier than the time at which a capacitor at high voltage is connected cc its bit line.

This time difference can be critical for the following reason. The clamping of the titline pairs brings both to che same potential. Just before the word lines are brought high. the clamping is reversed. The flip-flop goes ideally to a meta stable state with both nodes at the same potential. at che flip-flops switching potential. The switching pocencial is where the P-channel and the N-cha=el transistors draw the same current. Due to imprecise design and processing the ratio between device sizes in one leg of the flipflop may be different than that of the opposite leg. After clamping, this u=alance may be equivalent:c a signal already applied to a flip-flop node.

Left alone the flip-flcp nodes will proceed to switch n cl. - To minimize the effect of the e d4recticn of the untalance.

unbalance the signal from the capacitor should be applied as early an possible after switching the amplifier from the clamping state.

making it desirable to read both high and low voltage on applied storace capacitors at the same time. The fact is that if there is no signal from a low capacitor. then the associated capacitor must be at a hich level. Adding a dummy capacItcr on the not addressed bit line =n-4mizes the delay between the two readings. ".'he disadvantage of a du memory cell is that the effective signal from the storage capacitor is reduced by the signal from the dummy capacitor. The charge transferred from the dummy capacitor should be half of the -Charge transferred from the storage capacitor.

As shown in Fig. 1S. single capacitor memory cells are provided with single access transistors in each me=--y cell 1400. AS shown Fic. 15. z:ie voltages on the titlines are normally clamped to an inze--ned-ate voltage. such as V4Ai2. with a signal =-A".

::,-tar is aeneraced with a large buffering inverter i401.

1 7 Accordingly, both of the bit lines are connected together via transistor 1402 and the sources of pull-up transistors 1403 in sense amplif ier - 1404 are brought low when clamp is high.

When a word line is addressed for refresh. the ODD Dummy WL signal will be generated when the word line is odd. or the EVEN MUMMY WL signal will be generated when the word line is even. activating the access transistor in the corresponding d memory cell 1407 or 1409. respectively. These dummy capacitors will have low or ground voltage stored thereon. when the word line is addressed. the sources of PNDS transistors 1403 will be brought high and the bit lines will be disconnected. The " word line WL) and dummy word line (DWL) voltages will be brought high. Preferably the word line is raised above VCC In the case where the addressed storage capaci-tor has a low voltace thereon, the addressed storace capacitor voltace (C) will increase slightly, while drawing charge from the bit line. However, the charce drawn from the opposite bit line by the dummy m ry cell will be less. Accordingly, the dummy bit line will be higher than the bit line with the addressed cell. The switching will then proceed to completion.

As pointed out earlier the noise on a low capacitor can be held low with the right combination of capacitor size. number of bits on each bit line and the size of the transistors in the amplifier f1-4p-flop. There will be no noise on the high capacitor when the dummy capacitor is used.

In addition to the amplifier flip-flop and the du cells Fig. 15 also shows the circuitry 1411 for writing in new data and to read previous stored data. Such c4-rcuitz-jr is needed only if the user does not complement the input data.

B. Half Cell D"emic memory 1n the wt)odunent below, which is an example of the present invention, a very small storage capacitor can be used since the cell has its own amplifier. The bitl-ine capacitance can be large, as there are no speed reWirments for this application. Accogly, a half cell system may be used. Returning to Fig. 14. the memory cell 1501 includes transistors N1. N2. N3 and capacitor C, which is preferably the extended gate of transistor N2. Two word 'lines are used for each row of cells. one for reading (READ WL) and one for restoring (RESTORE WL) the charge on capacitors C. The a=lifier is basically an inverter. so that the read signal on the bit line can be reinverted and returned to the bit line at the restore time.

he operation of the read restore and data write operations are as follows. The address shift register works the same as described in the above embodiments. The f-Jrsz -nverter In the selected shi-,Oz register stage is set Cy cne o, clocx and the second 18 1 C inverter is reset by the -0c11owing 0, clock. The seleczed RFAZ WL is brouant hIgh by the same 01 clocx chac, resets the seccn-,,i inverter.

The READ WL zurns on che c;11 transistors NI. the camacitor has a hicn cnarge. z--ansiszc- N2 is in the cri state. which. causes che bit llne 5L to bc pulled icw. During 02 transistors N4 and NS in the ampl-!-4er!503 are also curnen on. N4 is a weak transistor. serving as a mullu-- 1cad in case cne cell camaciz--r 1-5 in a low c41,.arce state.

However. with a high charge an the cell capacitor. the gates of transistors PI and N6 are pulled to close to ground level and remain at this level when the gates of N4 and N5 are returned to ground at the end c'. a signal 02xjDATALD. At the next.01. the output of the inverter 1505. formed by transistors P! and N6. is connected cc che bit line via transistor N7.

With a short delay af ter o, (cc per.miz the bit line to cnance scate!. RESTC-RE WL is brcuant high via NOR ISC7 and connects zne ziz line to the storace --acacizcr C via cransistcr N3 restcring a hign cr low. as apprcpriate.

When data are written into a selected row, che content of the MATA -'?'N shift register is similarly applied to the input of the a=1-4!-.er inverter by the signal 02xDATAW.

The supply voltage!or most signals is the regular Vdd, but in order to get the lowest impedance and highest speed an the circults controlled by the cell capac-,zcrs some of the c-.=.--uits are connected to a pumped sumPly vdd'. This supply, which will be described later, delivers approximately 8 volts when Vdd ' 5 volts.

The inverter in the a=l-!-er and the NOR drivina che restore word line are supplied by Vdd. The 0, signal chat is applied to the gate zt N7:.s also at vdd-!evel. The hic.n voltage an zne szcrage capacizcr wil.' c.'-.ere,-,;cre ze one N- channel:.tresncid be.;cw Vdd or acprcxi.mate-ly 7 volt. Opticnally, -'-cc)zszrappina can be added to the sicnal on the gate of N7 and on tne RESTICRE WL.

ine Embcd4.,nent Fics. -16A to 16E illustrate ano arrangement.

:n Particular, Fig_. ISA illustrates the relevant Portions ci a fcur-phase Fig. 1-6B illustraces the relevant sicnals In che on a Z-J.-,iinc diacram. One i=ortant gear-u=e illustrated by way of the CIZC.--,t snewn in Fig.!6 is that z.te tit l-Jnes are clammed and then left tz float durina initial sensing- with '--cz:i zte hig,h WddA) and lcw (V. M sum lies cc the sense i6C2 left at a clam= jc-ltace,e.g., v) durina -ni-a sensinc.

19 rmains sec until the address shifts ouc of the UPPER FIELD. The signal CLAMP LEVEL is at about 1.5 v. Clocks CLI-CL4 are high (5 v) during the cimes indicated ac the bottom of the timing diagram (Fig. 16B). CL2 also serves as the CLAMP signal.

CLAMP sets the bit lines EL, and BL2 at this same voltage via clamping transistors 1603. During this time. the high and low voltage supplies to the sense uglifier are also set to the CI.AMP LMEL. The low voltage supply is set to CLAW LMEL since transistor 1605 is on. CL2 resets three. flip-flops in the circuit. This brings nodes 1623. 1631 and 1643 low. and 1625 and 1635 high. With 1625 high. nodes 1629 and 1627 are connected to the CLAMP LEVEL via transistors 1609 and 1605. Node 1627 is V5SA, which supplies the sources of the amplifiers N-channel transistors. which are now at about 1.5 v.

With node 1635 high. node 1637 WddA) is also at 1.5 v. The CLAMP signal (CL2) turns on transistors 1603 also bringing both bit lines EL and BLd to 1.5 v. The CLAMP also turns on transistor 1615. discharging the DUMMY capacitor to ground.

The DUMMY WL and WL are both at ground level during CL2. because 1641 was brought low and 1637 was brought high by the previous CL1. CL2 pulls node 1643 (WL) low.

During CL3. both the selected word line WL and the d word line for the UPPER HALF FIELD DMC4Y WL are brought to 1.5 v via circuits 1621 (WL connected to 1641) and 1613. respectively. A low value stored in the memory cell is illustrated in Fig. 163 and. accordingly, the bit line BL Is brought down significantly (due to the relatively large capacitance of the memory cell and the low value cored therein). Since a low value is stored in all dummy memory ells. the voltage of the d bit line BLD is also brought down. although not as low due to the relatively smaller capacitance of the dummy memory cell. An important feature is that. with the voltage on WL during CL3 and CL4 at the CLAMP LEVEL. the voltage on CN should never be higher ttan CLAMP LEVEL minus the threshold voltage on the selected transistor. This means that even if CN is small relative cc the bic line capacitance. the disturbance on CN will barely reach the threshold level on the circuits controlled by CN. On the otter hand, if Cl is larger than the bit line capacitance. then the disturbance will be less than the threshold level on the controlled circuits.

CL4 changes the state of nodes 1623 and 1625 bringing V99A to ground and VddA high to about 4 v via transistor 1607. The WL and D WL both remain at 1.5 v during CL4. The application of power on the amplifier causes the bit lines to switch in the relative direcr-4on preconditioned by the earlier displacement. BL will be pulled cc around. bringing CN along and BLd goes to 4 volt. while the d cell -jcltace remains at.7 v. CL4 according to one embodiment is i.s relatively longer than the other clocks to permit complete switching c.$ the high going bit line. while vddA at 4 V.

Thereafter. during CLI, the supply vddA is switched to VAd (8 v), pulling the high bit line up to Vdd CL1 brings node 1631 CO Vdd", which in turn brings node 1637 (VddA) to Vdd. The word line is also brought to vdd+ during CL1. but is preferably delayed enough relative to the positive going bitline so that a high storage node remains undisturbed. Tte dummy word line has already ser-ved its purpose during this time and may optionally be returned to ground an CL4. CL2 returns t he word line to g=und just before VddA is returned to the clamp level. As indicated in dashed lines. VddA may alternatively be brought up continuously over CL4 and CL1.

In more detail. the switching of the vcltages described above is accomplished as follows. Circuit 1619 controls VddA and v .A levels for the amplifier in the selected field. Circuit 1613 controls the dummy line voltage. The address shift register 1617 together with the circuits 1621 and 1611 selects and drives the word line.

Circuit 1.619 is active only when the field is selected. All non selected fields are in the clamp mode. CL2 applied to the circuit 1619 causes node 1623 to go to ground and node 1625 to go to Vdd. This connects VssA and node 1629 to the CLAMP LEVEL. CL2 also brings node 1631 of circuit 1633 to ground, toggling the high voltage latch. so that node 1635 goes to Vdd- The high node 1635 toggles the flip flop with node 1629 connected to V5s, so that the node 1637, which is supplying Vdd cc the amplifier.;s connected to the CLAM LEVEL. when the field is selected C11.4 pulls node 1625 in the circuit 1619 low. coggling node 1623 high. This connects node 1627 to ground and lif ts node 1629 to one threshold below 5 v (about 4 v). Node 1635 is still at Vdd-#-, so node 1637 goes to 4 V. If the field is selected. CL1 will finally pull node 1635 low, making node 1639 high. This in turn toggles the latch for VddA. so that the node 1637 goes to Vdd'.

Circuit 1613 in the clamped mode, initiated by CLI. is holding the DUMMY WL ac ground. With the UPPER HALF FIELD flip flop set (not shown) node 1637 is pulled low at CL3. This makes node 1639 high. connecting the DUMMY WL to the CLAMP LEVEL. Circuit 1621 functions similarly to circuit 1613 except that node 1641 is connected to the CLAMP LEVEL only when the associated address shift register position is set. Circuit 1611 is the latch. whose output. node 1643. is che ward line. C11 AND a set address shift register mcsicicn brings node 1643 110 the Vdd- level. while following CL2 returns node i643 to around. 3urina C:2 node 1643 remains at ground and will- stay at tnts level until:he address shift register returns:c this position. The latches used to switch the Vss-' between ground

21 and the CLAMP LEVEL of the dif f erent latches are used to maKe sure thac one gate is turned of-' before che otner is turned on. This -'izc.tes an the CLAMP LEVEL voltage. Of course. a simpler prevents 9.L arrancemenc nay be used if more current drain in the is acceptable.

is Perimheral Circuits A. PUMD-CirCUit Fig. 17 is a preferred pump circuit 1701 to provide the vdd voltage. The goal of the design is to avoid any risks of charge injection into the substrate. The oscillator includes of three inverters 1703. 1705. and 1707 with the last (1707) being a Schmidt Trigger. -,..e oscillating frequency generated by oscillator 1709 is relatively high. at least 100 MHz. Two powerful inverters 1703 and 1705 drive the pump circuit. whic.n may or may not be symmetric. The symmecriz conf -4curat-4cn was c.nosen here to minimize che noise generation. The physical location of chis circuit should be as close to the power pins as possible.

The current requirement has two components. First a DC component = supply gates and inverters. that have inputs at Vdd level and the P - channel devices connected to Vdde. The transient current associated with charging word and bit lines must also be considered. Fortunately refresh cycles are very long. permitting long rise and fall times. so the AC component is very small. The size of capacitors C, and C3 can be approximated by the formula 1 - 2xCxDVxf. where OV is the voltace drop below the voltage at no load. and f is the frequency. Additional voltage drops are due to the cransist=rs N1 through N4. These transistors should be large to:-,ini. -r,ize chis vclcace drop cemponent. For a load current of 2mA eacn capacitor:i and C should be approximately 1OpE at 100 MHz. 3 Capacitor C2 can be smaller then the other two.

it was mentioned earlier that some signals (e.g., wordl_4ne and scrobe) c=uld benefit from bcczszramping. Fig. iS shows a bootstraw circuit that njay be used.

The input IN is applied directly to the gate of a source follower 1801. which after a small delay in the first inverter i803 lifts the aucput to approximately an threshold below the supply voltage. After a furt.l,.er delay c.n=ough the second inverter 1305 the lower end of C, swings positive to the supply level.

A voltage 00 VddxCl-l(C1 - C2) is therefore added to the first level.:n m.ost cases che Icid camac-zance c ' 2 1.5 aulte large.

recuirinc a arce C- The source!=!lower will also 1 nave rive 7erv --z.-ce.nszanza.-.ecus zurrenz:z precnarge zne cuzmuz noce.

22 :Z boczszran circuic is used. wnen ene circuic is suppliec- -Irctn a pump.

very high peak currents must be avoided. A small source drive- zransiszc-. must be used in cc.=inat-4cn with a long delay in the seccnd inverter. The second inverter would in that case be replaced with a delay This delay circult may be a gaze utilizina some of the clocks in the dynamic control circuitry.

C. Secondary ou= In Fig. 19 the pump 1707 has been duplicated to generate a voltage. Vdd'", which is a few volts higher than the vddm voltage. i.e.. Vdd. Using vdd will permit the ward line and transfer signals cc cc high enough to achieve gate control signals ac Vddl levels without resorting to Bootstrap circuits.

Fig. 20 shows an alternative way to utilize the vdd,.o voltage.:n Ficr. 20 STROBE. which is supposed to go low when the word -1-4ne is selectedd. is pulled down by transistor N1. ?I is still turned on with a gate voltage Vdd - vdd-- since tte nigh shift register output is only at the vdd level. To minimize che associated current P! is long and narrow. Fortunately no current -'s d_rawn by non-selected wordlines since N1 is then turned off and the strobe is pulled to the vdd--- level.

The NAND gate connecting cc the word line -4s supplied from vdd.... and ground. so full CMOS performance results (no current in the on and of f states). '2 is generated by an inverter with P2 supplied f-cm vddl", while the gate swings between vdd and cround.

This is a single c-,rc,-,-4t common all ward lines. so allowance can be made for this current drain from Vdd'-- A designer wil need to balance between the need cc make P! and P2 small!cr nini.num current and che rise time requirements on whe lines to be driven.

V1. Sianal/Noise Level Considerations Minimizing the level of the momentary disturbance on the cant--=llina memory canac-ccr is desirable in the above circuits.

There is. however, a certain level of noise that is acceptable by the controlled in one common type of mult-4-,lexer. one cut of K incoming signals is rcuted throuch N-channel transistors to one autpuc. The selected transistor is fully turned on, with its gate at vcc level.

which here is assumed to be 5 volts. The sicrnal on the input of the selected transistor may be 5 volts if coming from a =S logic or 4 volts if c=inc from another multimlexer of z.te same cype.:n this case the selected transistor will with some delay output a signal at 4 volCS. but the transistor will in the final state '-e barely zurned on. One of the nct selectet::ransistcrs has an inpuz level a= 2 volt. tut:he gaze is exposed zo a re-,,;--esn noise 23 pulse of Vncise peaK amp!-.tude - 2Vth (1.4 V;. the threshold v cl"-ace fcr:ne selected transiszcr a: 4 volc - 1 valc and V- for the non-se-;ecte.-,4:ransistcr - 0.7 volt, the autpuc would drop 1 volt to 3 volt. There are of course worse cases. where more than one non selected transistor with their inputs at ground all are refreshed at:he same time. With 2 transistors pulling down under chase ccnd-4z-,ons che voltage would drop approximately 1.5 volt to 2.5 volt and with 4 transistors pulling down. the drop would be 2 volt, bringing the output to 2 volt. The stated numbers are generally based on the equations applicable to MOS transistors.

If pumped voltages are used to b:Ring the voltage on the ccnzr--1 capacitors above Vdd. then the situation changes. With the conc:.=! voltage at 7 volts. an incoming signal at 5 volt and one distu--=-4ncinput would drop the output to 4.6 volt. Two disturbed sicnals as discussed above would drop the output to 4.3 volt and tou.discurzed inputs would drop che output to 3.8 volt.

:n the discussion above, the assumption was made that the d.4st.-r=ance was much slower than the speed of the circuits that are with the attempts co make a fast amplifier. a noise pulse may actually be filtered in a multiplexer. It is also assumed ciaz ch.e disturbance on the contrailing capacitors peaked at 0.7 volts above the threshold level of the controlled transistors. If the eireshold voltage on the transistor is 0.7 volts. the peak would be at 1.4 volts. Disregarding the discharge contribution from the amplifier itself on the bitilne and assuming that the cell cavaci=ance ecuals the bicline capacitance. this would mean that the clamped voltage would equal 2.8 volt. By lowering the clamped voicace and maxing sure that che clamped voltage equals the pctent-4a-l at:ne switc.-.ina point of the a=l-if-4er flip-flc-,-.:he disturbance levell =. c:e scorage capacincr can be reduced.:n the example above. reducing the clamp level to 2 volt would drop the noise peak to vo---. (VG-V-7,' is then 0.3 volt compared to 0.7 volt before. This reduces the noise current:c 18% of that in the example above.

Fig. 21 shows partly in block form an alternative cc the devices discussed above. A au.= 21Z1 is continuously running and sump-!-4--s power -.a N-wells associated wich the high voltage latches 2103 and the Vdd supply for latch 2102. Latch 2102 has an outp,-z 2109. tnat is low during clamp zime and h,-gh durina read time. Out=u.z 22.09 supplies vdd for sense amplifiers 2104 and!cr word line select latc.nes 2103. A recirculatIng sh-4-1t register 212i selects the word 1--4.ne cc --e used. The selected latc.h Is set by the =OCK signal and reset by its cc=lenent - fLb-d-K. Outpuc 2109 of latch 2102 goes nich cn ==K f cr everv selected word ne and goes lcw f cr every is driven d-4recti-y t==.n =:e no-r W 2. 'd L mal V., ncz shown i- 24 2S _; 5 the C2D or zne EVEN dummy word line lazcn A data input shift register 2108 is also shown.

- The operation of the refresn cycle of the device in Fic.:1 is best furzbier described in connection with Fig. 22. Clamping action takes place during d-T.7j(f4. Node 2109 is low during so the power is turned off to all high voltage latches and to the sense amplifiers. fWj(fK also pulls all bit lines to cround.

Fig. 22 shows two cases. In the f irst case. ward line 2114 is selected and the associated bit 2113 is low. After the clamminc, which brought both bit lines 2112 and 2111 to ground level. the C1OCK signal starts the read-refresh phase. Node 2109 goes high, but its rise time is controlled by careful selection of the P-channel transistor pulling up node 2109 in relation to the load imptosed by the latches connected thereto. The word line 2114, which is very Iona and connects to a large number of cells. has a slower slope than node 2109. 7he du=w. ward lines DMIMY WL have about the same rise time as the word lines. In this case. node 2109 moves positive until the P-channel transistors are turned on. Nodes 2111 and 2112 are pulled up in parallel except!or a slichz difference caused by size differences between the P-channel transistors. When nodes 2111 and 2112 reach the threshold level of the N-channel transistors, the pullum of nodes 21-11 and 2112 is slowed down. If the word line had not been madehigh. nodes 2111 and 2112 would have reached the level of the f!4p- flops switching point and stayed there until the slight urdnalance had caused the flip-flop to flip to one side. The word line 2114 par-ential is. however, increasinc concurrently with node 2109. As soon as 2114 reacnes the threshold level. the zrar.sistcr in the cell connects &"ill and the stcrace canacitcr.

de 2112. As 2114 his slows node 2111 in re-latlen c-- no goes.-.-Jgher. the untalancing current increases. When::his cur-rent ------ s the build in unbalance of the flip-flop. the desired switc:inc proceeds at an accelerated rate. The advantage of this apprcacn is that at this relatively low voltage on node 2109. the currenz in the P-channel transistors is small and there-"y the differential c,r--enz is also small. The current from the szcrage c; pacizcr need only overcome this small differential current.

The d.,i.-zny word line (EVEN) goes positive at the same cr slower rate than tne word line. The dummy capacitor is only half as large as che szcrace capacitor. so the capac-zcr, so the capacitor at 2113 d=inates.

:n the second case. szcrace node 2116 is hJah. word line 211S is selected and the ODD dummy ward!-;ne is selected. The d.=.-nv camac.-zcr in 21-06 now holds back node 2111 and causes node 2112 rc fliF hian. Node 21116 is d-4szur--ed cr.lv Lf 2LIS at any tine is ncre znan one VCP. above 2112. This could happen only if zte slope c:

2115 is very close to that of 2109. But even at that eventuality, the negative excursion of node 2116 would be minimal compared to the case without dummy capacitors. Any charge lost by capacitor 2116 due to leakage or the potential cause discussed above will be replaced at the time wordline 2115 reaches the Ydd +. The voltage will be (Vdd+ - Vth).

- 26

Claims (7)

1. A dynamic memory integrated circuit structure comprising: a storage capacitor, a first plate of said storage capacitor coupled to a gate of an access transistor, a second plate of said storage capacitor coupled to a first terminal of said access transistor; a read transistor, said read transistor having a first terminal coupled to a second terminal of said access transistor and second terminal coupled to a bit line; a restore transistor, said restore transistor having a first terminal coupled to said bit line and a second terminal coupled to said first plate of said storage capacitor; and an inverter circuit having an input selectively coupled to said bit line and an output selectively coupled back to said bit line.

2. The dynamic memory as recited in Claim 1 further comprising: a f irst, restore word line coupled to a gate of said restore transistor; and a second, read word line coupled to a gate of said read transistor.

3. The dynamic memory as recited in Claim 1 or Claim 2 further comprising: a control circuit for selectively coupling said bit line to an input of said inverter circuit at a first time during an operating cycle and coupling an output of said inverter circuit back to said bit line at a second time in an operating cycle.

4. The dynamic memory as recited in Claim 3 wherein a gate of said read transistor is couple to a control line for activation of said read transistor during said first time and a gate of said restore transistor is coupled to an output of said inverter during said second time.

5. The dynamic memory as recited in any preceding claim further comprising a weak pullup transistor coupled to said bit line, said weak pullup transistor pulling said bit line to a high level when said bit line is brought high by said storage capacitor, and leaving said bit line at a relatively lower level when said bit line is brought low by said storage capacitor.

is

6. The dynamic memory as recited in any preceding claim wherein said first plate of said storage capacitor is a control node in a programmable logic device.

7. A dynamic memory integrated circuit structure as claimed in Claim 1 and as further described with reference to Figure 14 of the accompanying drawings.